The document discusses techniques for thermomechanical modeling of 3D integrated circuits. It introduces Cielution's product pipeline including CielSpot for package thermal modeling and compact model generation, CielSpot-CTM for thermally aware IC layout, and CielMech for thermo-mechanical analysis. Cielution provides expertise in thermal and mechanical simulation along with tools expertise in ANSYS, Icepak, Fluent, etc. The document highlights challenges like warpage in 3D IC assembly and demonstrates Cielution's tools for modeling assembly processes, predicting warpage evolution, and validating compact thermal models against detailed simulations within 1% error.

1. Techniques and Tools for Collaborative Thermal and
Mechanical Modeling of 3D Ics
Kamal Karimanal
Cielution LLC

2. About Cielution
© Cielution

3. Cielution Product Pipeline
CielSpot™
• Package Thermal Modeling
• Package Compact Model
Generation
CielSpot-CTM™
• Thermally Aware IC Layout
o Traditional Packages
o 3D Stacked Assemblies
CielMech™
• Thermo-Mechanical
Analysis of Assembly
o Warpage Mitigation
o Packaging Yield
Enhancement
o Interconnect Reliability

4. Cielution Services
Expertise Areas
• Thermal and Mechanical Simulation
• Chip, Package Board and System Level
Engineering.
Tools Expertise
• ANSYS, Icepak, Fluent, CFX,
Flotherm
Business Model
• Fixed Cost Fixed Time Projects
• Best suited for when a clearly defined
problem statement exists
• Suited for Scripting and Automation
Projects
• ANSYS APDL, Fluent UDF, Icepak
Macro, Desktop & Web based UI
development. • Hourly rate
• Suited to situations when the problem
statement is likely to evolve.
• For temporary resource crunch
situations
• Open to On & Off customer site options
© Cielution

5. Motivation for Thermo-Mechanical Simulation
3D IC roadmap has introduces brand new
Thermal and Mechanical challenges.
Test Chip & Test vehicle programs effective, but
expensive
• May not offer information for root cause identification
Thermo Mechanical modeling is an effective filter
before finalizing test vehicle design and testing
plans.
Hence, appropriate engineering simulation tools,
methodologies and capabilities will empower
modeling professionals as well as other
technologists enabling 3D IC technology.
(c) Cielution LLC

6. Mechanical Stress Modeling of
3D ICs
(c) Cielution LLC

7. High Level Classification of Mechanical Simulation Drivers
Assembly Process Technology Development
• Warpage assessment & feasibility of assembly
• New process evaluation
o CUF? NUF? MUF? Thermo Compression? • Material choices & related process temperature implications
Package Design
• Implications of the following:
o Encapsulation, substrate and stiffener dimensions
o Material Choice
Yield
• Low K Dielectric failure assessment
• Delamination Risk During Processing
Long term Reliability
• Solder Joint Reliability
• Underfil delamination mitigation
• Board Level Reliability of interconnects (Shock/Drop)
TSV/Device level Mobility impact study
(c) Cielution LLC

8. Warpage – A major Assembly Challenge
Thinned Wafer/chip
Warpage Estimation
Techniques
• Stoney Equation
o 50 um thick silicon is not
much thicker than the Front
and Back Side RDL Films
(~5 to 10 um each). Validity
of Stoney equation is
questionable.
o Errors ~ 30 to 50% have
been observed for 50
micron thick wafers with 5
micron thick films (Stoney
compared to FEA)
• FEA Simulation
R, radius of curvature
Film Stress, s
tSi
tf
2 1
f Si '
Stoney s Formula
(c) Cielution LLC
t
si
t R
E
f
  

9. Chip Stacking Case Study
(c) Cielution LLC

10. Stack up Description
Logic Die
(23mmX16mm)
Substrate
FSRDL Films
BSRDL Films
4X4 Memory
Stacks (10X6.5)
(c) Cielution LLC
Memory Chips
Underfill Regions
Logic Die

11. 3D Assembly Flow I: D2D
Step 1: Mem Stack to Logic
(@ reflow Temperature 230 C)
Step 2: Capillary Underfill Step 3: Chip Stack to Substrate
(@ reflow Temperature 230 C)
Step 4: Capillary Underfill Step 5: Overmolding or Lid Attach
(c) Cielution LLC

12. Warpage Evolution for D2D Flow

13. Assembly Flow II: P2D
Step 1: Mem Stack to Logic
(@ reflow Temperature 230 C)
Step 2: Capillary Underfill Step 3: Memory Stack Attach
(c) Cielution LLC
Step 4: Capillary Underfill Step 5: Overmolding

14. Warpage Evolution for P2D Flow

15. CielMech™ for Thermo-
Mechanical Modeling
Automation
(c) Cielution LLC

16. CielMech: High Level Workflow
Stack Info
CielMech™
Package
Info
Process Info
Automated Geometry,
Meshing & Problem Setup
Automated Reports, Images
& custom Post Processing
(c) Cielution LLC
Intelligent Solver Controls
Solve in ANSYS
Access to Model in the ANSYS native format

17. Case Study - Thermal Simulation
of 3D SOCs
(c) Cielution LLC

18. 3D Stack on interposer
4 Stacked Dies(8X6)
Logic 2(22x16)
Interposer (36x24)
(c) Cielution LLC
Substrate (40 X 28)
All Dimensions in mm

19. Packaging & Cooling Scenario
h = 25 W/sq.m/K, Tamb=20C
Power Distribution Scenario A (total
Power=12.7W)
(c) Cielution LLC
1 W
1 W
1 W
1 W
2 W

20. Temperature Profile for II-a
(c) Cielution LLC

21. Power Profile II-B (total Power=12.7W)
1 W
1 W
2 W
(c) Cielution LLC
1 W
1 W

22. Power Profile for II b
Temperature increased by 26% due to hot spot proximity
(c) Cielution LLC

23. Moral?
Heat distribution plays an important role in chip temperature rise.
Hot spot proximity between chips produce unintended consequences
after heterogeneous integration.
• This is a new twist which will obsolete the existing thermal management
methodologies based on qja
Predicted temperature from thermal model are highly sensitive to:
• Packaging, Heat sinking, 3D layout of stacked chips, orthotropic nature of
laminates, and interconnect arrays.
Above sensitivities can only be captured by thermal models using 3D
numerical discretization.
• Spreading and t/KA resistance formulation based approaches have
inherent assumptions which tend to introduce unknown uncertainties.
However, the fast turn around & automation needed by IC design flow
can only be addressed by effective compact models.
(c) Cielution LLC

24. A Boundary Condition Dependent Compact Model for 3D IC packages
[DT] = [C] * [Q]
• [DT] - Distribution of temperature rise over ambient (T rise
vector)
• [C] – Coefficient Matrix
• [Q] – Power (heat distribution) vector.
Linear superposition based compact modeling
approaches for non uniform heat loads are well
documented:
• Linear Superposition Speeds Thermal Modeling (Part I & Part
II), Stout, R., Power Electronics Technology, January 2007.
• Karimanal, K.,Chip-Package Thermal Co-Simulation
Technique for Thermally Aware Chip Design (Itherm, 2010)
• Park, J. H. et al. “fast thermal analysis of vertically integrated
circuits (3-d ICs)using power blurring method”, (ASME
Interpack 09)
(c) Cielution LLC

25. CielSpot – A 3D IC Package
Focused Thermal Modeling
Software As A Service (SAAS)
(c) Cielution LLC

26. CielSpot: High Level Workflow
Stack Info
CielSpot™
Package
Info
Material Properties
Automated Geometry,
Meshing & Problem Setup Automated Thermal Snapshots
& Temperature data
Compact Thermal
Model
(c) Cielution LLC
Intelligent Solver Controls
Solve in
Commercial
Thermal Solver
Access to Model in the commercial solver’’s native format

27. CielSpot Usage: Compact for Fast Solve Without CFD/FEA
Pmap for Chip 1
Pmap for Chip 2
Pmap for Chip 2
…
Etc…
Input Data: CTM CielSpot CTM
Automated Thermal
Snapshots &
Temperature data
(c) Cielution LLC

28. Collaborative Thermal Modeling using CielSpot™
OSAT Proprietary Details. Need Third Party Solver
Packaging CielSpot
Org.
Compact Model Library
Package Details &
Typical Heatsinking
Scenarios
Package A
Package C
(c) Cielution LLC
Fabless
Customer
Power Map
for Each Chip
Package B
CielSpot
CTM™
Application Proprietary Details. Don’t Need Third Party Solver
Data Cannot be
Reverse Engineered

29. Demo of CielSpot for Compact
Model Extraction
(c) Cielution LLC

30. Demo of CielSpot CTM for Quick
Estimation of Temperature
Distribution
(c) Cielution LLC

31. Package used for Validation
Copper Lid
Logic Die (25X15X0.4) 2 X two layer memory
Substrate Stacks (9.5X11X0.05)
(c) Cielution LLC

32. Validation of Compact
Modeling Methodology
(c) Cielution LLC

33. Packaging & Cooling Scenario I
Heat Sink
Copper Heat Spreader
(c) Cielution LLC
PCB
Package housing
3D IC stack

34. Validation Results
FEA (ANSYS) Prediction of Temperature
Distribution on Memory-I
CielSpot-CTM Prediction of
Temperature Distribution on Memory-I
(c) Cielution LLC

35. Distribution of Errors
Predicted Temperature Rise_vs. Error
1.50%
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
50 55 60 65 70 75
Predicted Temperature
Error %
(c) Cielution LLC

36. Conclusions
Demonstrated Methodologies for Thermal and
Mechanical Modeling of 3D ICs
• Need for Automation and Collaboration addressed
with IC packaging focused interface products to
ANSYS
o CielSpot™
o CielSpot-CTM™
o CielMech™
Validated CielSpot-CTM against detailed model
• Less than 1% Errors in peak temperature prediction
Compared D2D and P2D process flows using
CielMech
• Warpage evolution is controllable by various knobs
o FS & BS film material & process
o MC and substrate design parameters and material choice
o Underfill cure temperature and material choice