This document discusses integrating irreversible Boolean gates into reversible circuits using the NCT library. It begins with background on reversible circuits and defines relevant terms. Reversible circuits can be represented as permutations, allowing the use of group theory for synthesis. The NCT library consists of NOT, CNOT, and Toffoli gates and is universal for 3-bit reversible circuits. Optimization rules are applied to synthesized circuits to minimize quantum cost. The document aims to integrate three irreversible Boolean functions into a single 3-bit reversible circuit while maintaining reversibility.
Low Power Implementation of Boothโs Multiplier using Reversible GatesIJMTST Journal
ย
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designersโ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Boothโs multiplier in reversible mode. So that power is optimised Boothโs multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
ย
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
Power Optimization using Reversible Gates for Boothโs MultiplierIJMTST Journal
ย
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designersโ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Boothโs multiplier in reversible mode. So that power is optimised Boothโs multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Computational Engineering Research(IJCER)ijceronline
ย
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGICBUKYABALAJI
ย
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in fields of Digital Signal Processing, Quantum
Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main purposes
of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage outputs.
This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed architecture
Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Key Words:Quantum Computing, Reversible Logic,
Garbage outputs, Constant Inputs.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
Low Power Implementation of Boothโs Multiplier using Reversible GatesIJMTST Journal
ย
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designersโ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Boothโs multiplier in reversible mode. So that power is optimised Boothโs multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
ย
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
Power Optimization using Reversible Gates for Boothโs MultiplierIJMTST Journal
ย
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designersโ endeavours are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Boothโs multiplier in reversible mode. So that power is optimised Boothโs multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
International Journal of Computational Engineering Research(IJCER)ijceronline
ย
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGICBUKYABALAJI
ย
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in fields of Digital Signal Processing, Quantum
Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main purposes
of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage outputs.
This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed architecture
Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Key Words:Quantum Computing, Reversible Logic,
Garbage outputs, Constant Inputs.
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
ย
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
ย
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
ย
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
ย
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywordsโ advanced computing, Reversible logic circuits, reversible logic gates and comparator
Direct Design of Reversible Combinational and Sequential Circuits Using PSDRM...IJRES Journal
ย
Reversible logic will be a favourable logic by dissipating less heat than the thermo dynamic limit for
the emerging computing technologies. Also it has become very promising for low power designs. Reversible
designs of Combinational and Sequential circuits are built by replacing the latches, flip-flops and associated
combinational gates of the traditional irreversible designs by their reversible counter parts. But this replacement
technique is not very promising because it leads to high quantum cost and garbage outputs. So, in this paper we
presented both the direct design and replacement designs of 5-bit up down counter and universal shift register
which are practically important using reversible logic and PSDRM expressions. Replacement design is done by
replacing the RTL design using reversible designs. Direct design is done by representing the state transitions and
the output functions of the circuits using PSDRM expressions which are obtained from truth table or state
transition table. Thus my direct design of a 5-bit updown counter and universal shift register save 42.66%,
9.79% quantum cost and 93.75%, 40% garbage outputs respectively than the replacement design.
Multiple Resonant Multiconductor Transmission line Resonator Design using Cir...Sasidhar Tadanki
ย
In this thesis, a new design procedure to determine resonant conditions for a multiconductor transmission line (MTL) resonator is proposed. The MTL is represented as a multiport network using its port admittance matrix. Closed form solutions for different port resonant modes are calculated by solving the eigenvalue problem of the admittance matrix using the block matrix algebra. A port admittance matrix can be formulated to take one of the following forms depending on the type of MTL structure: i) a circulant matrix, ii) a circulant block matrix (CB), or iii) a block circulant circulant block matrix (BCCB). A circulant matrix can be diagonalized by a simple Fourier matrix, and a BCCB matrix can be diagonalized by using matrices formed from Kronecker products of Fourier matrices. For a CB matrix, instead of diagonalizing to compute the eigenvalues, a powerful technique called โreduced dimension methodโ can be used. Application of block matrix algebra helps reduce the computational complexity and also simplifies the formulation of the analytical solutions.
To demonstrate the effectiveness of the proposed methods (2n port model and reduced dimension method), a two-step approach was adopted. First, a standard published Radio Frequency (RF) coil is analyzed using the proposed models. The obtained resonant conditions are then compared with the published values and are verified by full-wave numerical simulations. Second, two new dual-tuned RF coils for magnetic resonance (MR) imaging, a surface coil design using the 2n port model and a volume coil design using the reduced dimensions method, are proposed, constructed, and bench tested. Their validation is carried out by employing 3D EM simulations as well as undertaking MR imaging in clinical scanners. Imaging experiments were conducted on phantoms, and the investigations indicate that these RF coils achieve good performance characteristics and a high signal-to-noise ratio in the regions of interest.
Now a dayโs reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
DETECTION AND ELIMINATION OF NON-TRIVIAL REVERSIBLE IDENTITIESIJCSEA Journal
ย
Non-Trivial Reversible Identities (NTRIs) are reversible circuits that have equal inputs and outputs. NTRIs of arbitrary size cannot be detected, in general, using ptimization algorithms in the literature. Existence of NTRIs in a circuit will cause a slow down by increasing the number of gates and the quantum cost. NTRIs might arise because of an integration of two or more optimal reversible circuits. In this paper, an algorithm that detects and removes NTRIs in polynomial time will be proposed. Experiments that show the bad effect of NTRIs and the enhancement using the proposed algorithm will be presented.
Design of Multiplexers, Decoder and a Full Subtractor using Reversible GatesIJLT EMAS
ย
This paper shows an effective design of combinational circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage outputs in implementing each combinational circuit.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
ย
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
ANALYSIS OF ELEMENTARY CELLULAR AUTOMATA BOUNDARY CONDITIONSijcsit
ย
We present the findings of analysis of elementary cellular automata (ECA) boundary conditions. Fixed and variable boundaries are attempted. The outputs of linear feedback shift registers (LFSRs) act as continuous inputs to the two boundaries of a one-dimensional (1-D) Elementary Cellular Automata (ECA) are analyzed and compared. The results show superior randomness features and the output string has passed the Diehard statistical battery of tests. The design has strong correlation immunity and it is inherently amenable for VLSI implementation. Therefore it can be considered to be a good and viable candidate for parallel pseudo random number generation
We propose a concept of quantum computing which incorporates an additional kind of uncertainty, i.e. vagueness (fuzziness), in a natural way by introducing new entities, obscure qudits (e.g. obscure qubits), which are characterized simultaneously by a quantum probability and by a membership function. To achieve this, a membership amplitude for quantum states is introduced alongside the quantum amplitude. The Born rule is used for the quantum probability only, while the membership function can be computed from the membership amplitudes according to a chosen model. Two different versions of this approach are given here: the \textquotedblleft product\textquotedblright\ obscure qubit, where the resulting amplitude is a product of the quantum amplitude and the membership amplitude, and the \textquotedblleft Kronecker\textquotedblright\ obscure qubit, where quantum and vagueness computations are to be performed independently (i.e. quantum computation alongside truth evaluation). The latter is called a double obscure-quantum computation. In this case, the measurement becomes mixed in the quantum and obscure amplitudes, while the density matrix is not idempotent. The obscure-quantum gates act not in the tensor product of spaces, but in the direct product of quantum Hilbert space and so called membership space which are of different natures and properties. The concept of double (obscure-quantum) entanglement is introduced, and vector and scalar concurrences are proposed, with some examples being given.
Online first: https://www.intechopen.com/online-first/obscure-qubits-and-membership-amplitudes
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
ย
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
A Novel Design of 4 Bit Johnson Counter Using Reversible Logic Gatesijsrd.com
ย
In recent years, reversible logic circuits have attracted considerable attention in improving some fields like nanotechnology, quantum computing, cryptography, optical computing and low power design of circuits due to its low power dissipating characteristic. In this paper we proposed the design of 4-bit Johnson counter which uses reversible gates and derived quantum cost, constant inputs, garbage output and number of gates to implement it.
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
ย
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSI...VLSICS Design
ย
In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.
Optimized study of one bit comparator using reversible logic gateseSAT Journals
ย
Abstract In digital electronics, the power dissipation is the major problem. So that the reversible gate can be implemented in microelectronics and electronics which have low power dissipation in the digital designing because, in the reversible state in reversible logic it will use no energy. Hence reversible logic has ability to reduce the power dissipation in digital designing. In the Reversible logic, reversibility have a special condition which is reversible computing and reversible computing is based on the principle of BIJECTION DEVICE with a same no. of input and output which means one to one mapping. Reversible logic has numerous applications in the field of electronics and microelectronics which are ultra low power in nanoscale computing, quantum computing, emerging nanotechnology cellular automata and the other approach of reversible logic is ballistic computation, mechanical computation which are the basic technology. This paper presents an optimization of reversible comparator using the existing reversible gates and proposed new Reversible one bit comparator using BVF gate. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost. Keywordsโ advanced computing, Reversible logic circuits, reversible logic gates and comparator
Direct Design of Reversible Combinational and Sequential Circuits Using PSDRM...IJRES Journal
ย
Reversible logic will be a favourable logic by dissipating less heat than the thermo dynamic limit for
the emerging computing technologies. Also it has become very promising for low power designs. Reversible
designs of Combinational and Sequential circuits are built by replacing the latches, flip-flops and associated
combinational gates of the traditional irreversible designs by their reversible counter parts. But this replacement
technique is not very promising because it leads to high quantum cost and garbage outputs. So, in this paper we
presented both the direct design and replacement designs of 5-bit up down counter and universal shift register
which are practically important using reversible logic and PSDRM expressions. Replacement design is done by
replacing the RTL design using reversible designs. Direct design is done by representing the state transitions and
the output functions of the circuits using PSDRM expressions which are obtained from truth table or state
transition table. Thus my direct design of a 5-bit updown counter and universal shift register save 42.66%,
9.79% quantum cost and 93.75%, 40% garbage outputs respectively than the replacement design.
Multiple Resonant Multiconductor Transmission line Resonator Design using Cir...Sasidhar Tadanki
ย
In this thesis, a new design procedure to determine resonant conditions for a multiconductor transmission line (MTL) resonator is proposed. The MTL is represented as a multiport network using its port admittance matrix. Closed form solutions for different port resonant modes are calculated by solving the eigenvalue problem of the admittance matrix using the block matrix algebra. A port admittance matrix can be formulated to take one of the following forms depending on the type of MTL structure: i) a circulant matrix, ii) a circulant block matrix (CB), or iii) a block circulant circulant block matrix (BCCB). A circulant matrix can be diagonalized by a simple Fourier matrix, and a BCCB matrix can be diagonalized by using matrices formed from Kronecker products of Fourier matrices. For a CB matrix, instead of diagonalizing to compute the eigenvalues, a powerful technique called โreduced dimension methodโ can be used. Application of block matrix algebra helps reduce the computational complexity and also simplifies the formulation of the analytical solutions.
To demonstrate the effectiveness of the proposed methods (2n port model and reduced dimension method), a two-step approach was adopted. First, a standard published Radio Frequency (RF) coil is analyzed using the proposed models. The obtained resonant conditions are then compared with the published values and are verified by full-wave numerical simulations. Second, two new dual-tuned RF coils for magnetic resonance (MR) imaging, a surface coil design using the 2n port model and a volume coil design using the reduced dimensions method, are proposed, constructed, and bench tested. Their validation is carried out by employing 3D EM simulations as well as undertaking MR imaging in clinical scanners. Imaging experiments were conducted on phantoms, and the investigations indicate that these RF coils achieve good performance characteristics and a high signal-to-noise ratio in the regions of interest.
Now a dayโs reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
DETECTION AND ELIMINATION OF NON-TRIVIAL REVERSIBLE IDENTITIESIJCSEA Journal
ย
Non-Trivial Reversible Identities (NTRIs) are reversible circuits that have equal inputs and outputs. NTRIs of arbitrary size cannot be detected, in general, using ptimization algorithms in the literature. Existence of NTRIs in a circuit will cause a slow down by increasing the number of gates and the quantum cost. NTRIs might arise because of an integration of two or more optimal reversible circuits. In this paper, an algorithm that detects and removes NTRIs in polynomial time will be proposed. Experiments that show the bad effect of NTRIs and the enhancement using the proposed algorithm will be presented.
Design of Multiplexers, Decoder and a Full Subtractor using Reversible GatesIJLT EMAS
ย
This paper shows an effective design of combinational circuits such as 2:1, 4:1 multiplexers, 2:4 decoder and a full subtractor using reversible gates. This paper also evaluates number of reversible gates used and garbage outputs in implementing each combinational circuit.
International Journal of Engineering and Science Invention (IJESI) inventionjournals
ย
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
ANALYSIS OF ELEMENTARY CELLULAR AUTOMATA BOUNDARY CONDITIONSijcsit
ย
We present the findings of analysis of elementary cellular automata (ECA) boundary conditions. Fixed and variable boundaries are attempted. The outputs of linear feedback shift registers (LFSRs) act as continuous inputs to the two boundaries of a one-dimensional (1-D) Elementary Cellular Automata (ECA) are analyzed and compared. The results show superior randomness features and the output string has passed the Diehard statistical battery of tests. The design has strong correlation immunity and it is inherently amenable for VLSI implementation. Therefore it can be considered to be a good and viable candidate for parallel pseudo random number generation
We propose a concept of quantum computing which incorporates an additional kind of uncertainty, i.e. vagueness (fuzziness), in a natural way by introducing new entities, obscure qudits (e.g. obscure qubits), which are characterized simultaneously by a quantum probability and by a membership function. To achieve this, a membership amplitude for quantum states is introduced alongside the quantum amplitude. The Born rule is used for the quantum probability only, while the membership function can be computed from the membership amplitudes according to a chosen model. Two different versions of this approach are given here: the \textquotedblleft product\textquotedblright\ obscure qubit, where the resulting amplitude is a product of the quantum amplitude and the membership amplitude, and the \textquotedblleft Kronecker\textquotedblright\ obscure qubit, where quantum and vagueness computations are to be performed independently (i.e. quantum computation alongside truth evaluation). The latter is called a double obscure-quantum computation. In this case, the measurement becomes mixed in the quantum and obscure amplitudes, while the density matrix is not idempotent. The obscure-quantum gates act not in the tensor product of spaces, but in the direct product of quantum Hilbert space and so called membership space which are of different natures and properties. The concept of double (obscure-quantum) entanglement is introduced, and vector and scalar concurrences are proposed, with some examples being given.
Online first: https://www.intechopen.com/online-first/obscure-qubits-and-membership-amplitudes
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
ย
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
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Abstract: The World Wide Web is a huge source of hyperlinked information contained in hypertext documents.
Search engines use web crawlers to collect these web documents from web for storage and indexing. The prompt
growth of the World Wide Web has posed incomparable challenges for the designers of search engines and web
crawlers; that help users to retrieve web pages in a reasonable amount of time. In this paper, a review on need
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Radio's is used in FUPD analysis for impact loading. The deformation of FUPD bar and plastic strains in
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compliance requirements as per IS 14812-2005. Additionally, failure analysis of the FUPD attachment points
with chassis is determined. Physical testing can be reduced significantly with this approach which ultimately
reduces the total cycle time as well as the cost involved in product development.
IOSR Journal of Applied Physics (IOSR-JAP) is an open access international journal that provides rapid publication (within a month) of articles in all areas of physics and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in applied physics. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
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which is interfacing with asynchronous SRAM 64kX8 memory. The target controller provides the control signals
to the SRAM for read and writes cycles. The master sends the address, data and other control signals. Based on
these signals the controller initiates the read and write cycles we have designed PCI block diagram which
represents how the master controls target and target interfaces with memory. We also designed state machine to
generate control signals for target controller by which the controller initiates the read and write cycles. PCI
implements a 32-bit multiplexed Address and Data bus (AD [31:0]).The simulation results presented in this
paper represents read and write transactions between slave and memory according to commands generated by
controller. We have been used Xilinx ISE project navigator 0.40d to simulate project code which is written in
Verilog Hardware Description Language. We have been tested our functionality by writing test bench and then
compared that results with actual functionality.
Keywords โ Asynchronous SRAM, PCI, PCI connector
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
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Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
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Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
โselectโ each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the โmechanicalโ type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
In this paper, we propose a new technique for implementing a low power high speed multiplier based on Sleepy Stack Technique and consisting of
minimum number of transistors. Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). An 4 bit x 4 bit
multiplier has also been implemented using the design of only using basic combinational circuits and its performance has been analyzed and
compared with similar multipliers designed with peer combinational design available in literature. The explored method of implementation achieves
a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional
CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.
Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)VLSICS Design
ย
Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This parity preserving gate allows any single fault to be detected at the circuitโs primary outputs. By using one PPPG a fault tolerant reversible full adder circuit can be realized. The proposed fault tolerant full adder (PFTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. The PFTFA gate is also used to implement high speed adders which are efficient basic building blocks of logic circuits. It has also been demonstrated that the proposed high speed adders are efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VLSICS Design
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Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator ave been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different novel reversible circuit design style is compared with the existing ones. The relativeresults shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present style in terms of number of gates, garbage outputs and constant input.
Fault modeling and parametric fault detection in analog VLSI circuits using d...IJECEIAES
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In this article we describe new model for determination of fault in circuit and also we provide detailed analysis of tolerance of circuit, which is considered one of the important parameter while designing the circuit. We have done mathematical analysis to provide strong base for our model and also done simulation for the same. This article describes detailed analysis of parametric fault in analog VLSI circuit. The model is tested for different frequencies for compactness and its flexibility. The tolerance analysis is also done for this purpose. All the simulation are done in MATLAB software.
Design of Complex Adders and Parity Generators Using Reversible GatesIJLT EMAS
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This paper shows efficient design of an odd and even parity generator, a 4-bit ripple carry adder, and a 2-bit carry look ahead adder using reversible gates. Number of reversible gates used, garbage output, and percentage usage of outputs in implementing each combinational circuit is derived. The CLA used 10 reversible gates with 14 garbage outputs, with 50% percentage performance usage.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
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The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
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This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
Optimum Network Reconfiguration using Grey Wolf OptimizerTELKOMNIKA JOURNAL
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Distribution system Reconfiguration is the process of changing the topology of the distribution
network by opening and closing switches to satisfy a specific objective. It is a complex, combinatorial
optimization problem involving a nonlinear objective function and constraints. Grey Wolf Optimizer (GWO)
is a recently developed metaheuristic search algorithm inspired by the leadership hierarchy and hunting
strategy of grey wolves in nature. The objective of this paper is to determine an optimal network
reconfiguration that presents the minimum power losses, considering network constraints, and using GWO
algorithm. The proposed algorithm was tested using some standard networks (33 bus, 69 bus, 84 bus and
118 bus), and the obtained results reveal the efficiency and effectiveness of the proposed approach.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
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The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation vโs kink energy, maximum energy dissipation vโs kink energy, minimum energy dissipation
vโs kink energy and average output node polarization vโs temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
EVOLUTION OF STRUCTURE OF SOME BINARY GROUP-BASED N-BIT COMPARATOR, N-TO-2N D...VIT-AP University
ย
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.
Similar to Integration of Irreversible Gates in Reversible Circuits Using NCT Library (20)
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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โข Indigenized local Support/presence in India.
โข Easy in configuration using DIP switches.
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Final project report on grocery store management system..pdfKamal Acharya
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Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
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Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
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Integration of Irreversible Gates in Reversible Circuits Using NCT Library
1. IOSR Journal of Computer Engineering (IOSR-JCE)
e-ISSN: 2278-0661, p- ISSN: 2278-8727Volume 14, Issue 6 (Sep. - Oct. 2013), PP 69-79
www.iosrjournals.org
www.iosrjournals.org 69 | Page
Integration of Irreversible Gates in Reversible Circuits Using
NCT Library
Mohamed Osman1
, Ahmed Younes2
, Moustafa H.Fahmy2
1
(Mathematics and Computer Science, Faculty of Science / Damanhour University, Egypt)
2
(Mathematics and Computer Science, Faculty of Science / Alexandria University, Egypt)
Abstract : The reversible circuit synthesis problem can be reduced to permutation group. This allows
Schreier-Sims Algorithm for the strong generating set-finding problem to be used to synthesize reversible
circuits using the NCT library. Applying novel optimization rules to minimize the number of gates gives better
quantum cost than that shown in the literature. Applications on how to integrate any three irreversible Boolean
functions on a single 3-bit reversible circuit will be shown.
Keywords: Reversible Circuit, Quantum Cost, Circuit Optimization, Group Theory
I. INTRODUCTION
Reversible logic [1,2] is an active area of research. It has many applications in quantum computing
[3,4], low-power CMOS [5,6] and many more. Synthesis and optimization of Boolean reversible circuits cannot
be done using classical methods [7]. Optimization of Boolean systems on non-standard computers that promise
to do computation more powerfully [8] than classical computers, such as quantum computers, is essential to
explore the novel applications that can be applied on such systems.
The study of reversible logic synthesis problem using group theory is arising rapidly. Investigation on
the universality of the basic building blocks of reversible circuits has been done [9,10]. A relation between
Young subgroups and the reversible logic synthesis problem has been proposed [11]. A comparison between the
decomposition of reversible circuit and quantum circuit using group theory has been shown [12]. GAP-based
algorithms that synthesize reversible circuits for various types of gate with various gate costs have been
proposed [13]. Tight bounds on the synthesis of 3-bit reversible circuits using ๐๐ถ๐ library has been shown in
[14].
The first aim of the paper is to synthesize 3-bit reversible circuits using ๐๐ถ๐ library with better
quantum cost than that shown in the literature. The second aim is to use the synthesized circuits to design a
reversible circuit that simulates the function of irreversible Boolean functions such as ๐ด๐๐ท, ๐๐ , ๐๐๐,
๐๐๐ , ๐๐ด๐๐ท and ๐๐๐ in a single zero-garbage reversible circuit by integrating any three Boolean functions as
long as this integration keep the reversibility of the circuit.
The paper is organized as follows: Sect. 2 gives a short background on the synthesis of reversible
circuit problem and shows the reduction the problem to permutation group. Sect. 3 shows the optimization rules
applied on reversible circuits obtained using Schreier-Sims Algorithm for the strong generating set-finding
problem [15] to decrease the quantum cost of the circuits. Sect. 4 shows the results of the experiments. Sect. 5
shows the results of integrating irreversible Boolean functions in a single 3-bit reversible circuit. The paper ends
up with a summary and conclusion in Sect. 6.
II. BACKGROUND
This section will review the basic definitions of reversible circuits, the definition of quantum cost of
reversible circuits and the basic notions for reversible circuit synthesis, the relationship between reversible logic
circuits and permutation group theory.
2.1 BASIC DEFINITIONS
Definition 1: Let ๐ = {0, 1}. A Boolean function f with n input variables ๐ฅ1, . . . , ๐ฅ ๐ and n output
variables ๐ฆ1, . . . , ๐ฆ๐ , is a function ๐ โถ ๐ ๐
โ ๐ ๐
, where ๐ฅ1, . . . , ๐ฅ ๐ โ ๐ ๐
is called the input vector and
(๐ฆ1, . . . , ๐ฆ๐ ) โ ๐ ๐
is called the output vector.
Definition 2: An n-input n-output Boolean function is reversible (๐ ร ๐ function) if it maps each input
vector to a unique output vector, i.e. a one-to-one, onto function (bijection). There are 2 ๐
! reversible ๐ ร ๐
Boolean functions. For n = 3, there are 40320 3-in/out reversible functions.
Definition 3: An n-input n-output (n-in/out) reversible gate (or circuit) is a gate that realizes a ๐ ร ๐
reversible function.
2. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 70 | Page
Definition 4: When an m-in/out reversible gate U is applied on an n-in/out reversible circuit such
that ๐ โค ๐, then U will be denoted as ๐๐1๐2โฆ ๐๐
๐
where {๐1, ๐2, . . . , ๐ ๐ } are the m wires spanned by U in order.
Definition 5: A set of reversible gates that can be used to build a reversible circuit is called a gate
library L.
Definition 6: A universal reversible gate library ๐ฟ ๐ is a set of reversible gates such that a cascading of
gates in ๐ฟ ๐ can be used to synthesize any reversible circuit with n-in/out.
Definition 7: A universal reversible gate sub library ๐๐ฟ ๐ is a set of reversible gates such that ๐๐ฟ ๐ โ ๐ฟ ๐
that can be used to build any reversible circuit with n-in/out.
Definition 8: Let a finite set ๐ด = {1, 2, . . . , ๐} and a bijection ๐ฟ โถ ๐ด โ ๐ด, then ๐ฟ can be written as,
1
๐ฟ (1)
2
๐ฟ (2)
3
๐ฟ (3)
โฆ
โฆ
๐
๐ฟ (๐)
(1)
i.e. ๐ฟ is a permutation of A. Let A be an ordered set, then the top row can be eliminated and ๐ฟ can be written as,
๐ฟ 1 , ๐ฟ 2 , ๐ฟ 3 , โฆ , ๐ฟ (๐) (2)
Any reversible circuit with n-in/out can be considered as a permutation ๐ฟ and (2) is called the
specification of this reversible circuit such that ๐ = 2 ๐
.
The set of all permutations on A forms a symmetric group on A under composition of mappings [16],
denoted by ๐ ๐ [17]. A permutation group G is a subgroup of the symmetric group ๐ ๐ [16]. A universal
reversible gate library ๐ฟ ๐ is called the generators of the group. Another important notation of a permutation is
the product of disjoint cycles [17]. For example, 1,2,3,4,5,6,7,8
1,2,4,3,7,6,8,5
will be written as 3, 4 (5, 7, 8). The identity
mapping โ()โ is called the unit element in a permutation group. A product ๐ โ ๐ of two permutations ๐ and
๐ means applying mapping ๐ then ๐, which is equivalent to cascading ๐ and ๐.
2.2 REVERSIBLE CIRCUITS
The ๐ถ ๐
๐๐๐ gate is used as the main reversible gate to build any reversible circuit, since it is proved to
be universal for reversible logic synthesis [7]. The ๐ถ ๐
๐๐๐ gate is defined as shown in Fig.1.
Figure 1: ๐ถ ๐
๐๐๐ gate. The control bit line is denoted by ๏ท, and the target bit line is denoted by โจ.
The action of ๐ถ ๐
๐๐๐ gate is defined as follows, if the control bit lines are set to 1 then the target bit
line is flipped, otherwise the target bit line is left unchanged. Some special cases of the ๐ถ ๐
๐๐๐ gate are defined
as follows, ๐ถ1
๐๐๐ gate with no control bit is called ๐๐๐ gate. ๐ถ2
๐๐๐ with one control bit is called ๐ถ๐๐๐
gate. ๐ถ3
๐๐๐ with two control bits is called Toffoli gate. For the sake of readability ๐ถ1
๐๐๐, ๐ถ2
๐๐๐ and
๐ถ3
๐๐๐ will be written shortly as ๐, ๐ถ and ๐ respectively where the control and/or target bits will be shown in
the subscript of the gate and the total number of bits will be shown in the superscript. The ๐, ๐ถ and ๐ gates can
be used to form a universal library for 3-in/out reversible circuits known as ๐๐ถ๐ library. The main ๐๐ถ๐ library
consists of 12 gates as shown in Fig.2.
3. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 71 | Page
Figure 2: The main ๐๐ถ๐ library consists of 12 gates
A gate library with ๐ gates is not universal for 3-in/out reversible circuits since it can realize only 8
possible circuits from the 40320 circuits [18]. For n-in/out reversible circuits, there are n possible ๐ gates. There
are 3 possible ๐ gates as shown in Fig.3.
Figure 3: The 3 possible ๐ gates for 3-bit reversible circuits.
๐1
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1 โ 1, ๐ฅ2, ๐ฅ3 โก 1, 5 2, 6 3, 7 4, 8 ,
๐2
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2 โ 1, ๐ฅ3 โก 1, 3 2, 4 5, 7 6, 8 ,
๐3
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2, ๐ฅ3 โ 1 โก 1, 2 3, 4 5, 6 7, 8 .
(3)
A gate library with ๐ถ gates can realize a total of 168 reversible circuits [18]. There are 6 possible
๐ถ gates for the 3-in/out reversible circuits as shown in Fig.4.
Figure 4: The 6 possible ๐ถ gates for 3-bit reversible circuits.
๐ถ12
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2โจ๐ฅ1, ๐ฅ3 โก 5, 7 6, 8 ,
๐ถ13
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2, ๐ฅ3โจ๐ฅ1 โก 5, 6 7, 8 ,
๐ถ23
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2, ๐ฅ3โจ๐ฅ2 โก 3, 4 7, 8 ,
๐ถ21
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1 โ ๐ฅ2, ๐ฅ2, ๐ฅ3 โก 3, 7 4, 8 ,
๐ถ32
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2 โ ๐ฅ3, ๐ฅ3 โก 2, 4 6, 8 ,
๐ถ31
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1โจ๐ฅ3, ๐ฅ2, ๐ฅ3 โก 2, 6 4, 8 .
(4)
The ๐ gate is the smallest reversible gate that is proved to be universal for non-reversible computation
as it is proved to function as ๐๐ด๐๐ท gate by initializing the target bit to 1 [7]. A gate library with ๐ gate is not
universal for reversible computation since it can realize only 24 possible 3-in/out reversible circuits [18]. There
are three possible ๐ gates for the 3-in/out reversible circuits as shown in Fig.5.
4. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 72 | Page
Figure 5: The 3 possible Toffoli (๐) gates for 3-bit reversible circuits.
๐123
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2, ๐ฅ3โจ๐ฅ1 ๐ฅ2 โก 7, 8 ,
๐132
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1, ๐ฅ2โจ๐ฅ1 ๐ฅ3, ๐ฅ3 โก 6, 8 ,
๐321
3
: ๐ฅ1, ๐ฅ2, ๐ฅ3
๐ฆ๐๐๐๐๐
๐ฅ1โจ๐ฅ2 ๐ฅ3, ๐ฅ2, ๐ฅ3 โก 4, 8 .
(5)
For 3-bits reversible circuits, there are 40320 possible 3-in/out reversible circuits. The ๐ gate, the ๐ถ
gate and the ๐ gate (๐๐ถ๐ library) can used to synthesize all 40320 possible 3-in/out reversible circuits.
2.3 QUANTUM COST
The quantum cost of a reversible circuit refers to optimization measurement as well as the number of
๐ถ ๐
๐๐๐ gates used in the circuit. The quantum cost of a reversible circuit is measured by the number of
elementary gates required to build the ๐ถ ๐
๐๐๐ gate [19], i.e. the number of 2-qubit gates used in its
implementation as a quantum circuit. In this paper, the cost of ๐ gate is ignored as in [13] to be able to compare
results, i.e. the cost of ๐ is equal zero, and the cost of any 2-qubit gate is 1 and the quantum cost of ๐ is equal 5
as shown in Fig.6.
Figure 6: Decomposition of a ๐ gate as 5 elementary gates.
When implementing a reversible circuit, there are four elementary quantum gates that will be used: ๐
gate, ๐ถ gate, Controlled-V and Controlled-V+
gates, where ๐๐+
= ๐+
๐ = ๐ผ , ๐๐ = ๐+
๐+
= ๐, and ๐ผ is the
identity gate [19].
III. OPTIMIZATION RULES TO REDUCE QUANTUM COST
Optimization rules will be used to identify and classify similarity of gates among a circuit when
decomposed to a sequence of quantum gates. Decomposition of 3-bit reversible circuits can be used to decrease
the quantum cost. Optimization is done by removing and/or combining (merging) adjacent gates act on the same
qubit lines [20]. For example, the cost of the sequence of reversible gates [๐123
3
, ๐ถ12
3
] is 4 instead of 6 as shown
in Fig.7, the cost of the sequence of reversible gates [๐123
3
, ๐ถ21
3
] is 5 instead of 6 as shown in Fig.8 and the cost
of the sequence of reversible gates [๐321
3
, ๐132
3
] is 9 instead of 10, because the sequence of gate ๐ถ32
3
and gate ๐32
3
can be combined as one gate [๐ถ32
3
๐32
3
] [20] as shown in Fig.9. The optimization rules used in this paper to
decrease the quantum cost of the 3-bits reversible circuits are shown in Table 1.
Figure 7: Decomposition of 3-bit reversible circuit [๐123
3
, ๐ถ12
3
] as 4 elementary gates.
Figure 8: Decomposition of 3-bit reversible circuit [๐123
3
, ๐ถ21
3
] as 5 elementary gates.
5. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 73 | Page
Figure 9: Decomposition of 3-bit reversible circuit [๐321
3
, ๐132
3
] as 9 elementary gates.
Table 1: Comparison of quantum cost using the proposed optimization rules and the existing work [21].
NCT Circuits
Quantum Cost
[21] Proposed
rules
3
12
3
123CT 6 4
3
21
3
123CT 6 5
3
13
3
132CT 6 4
3
31
3
132CT 6 5
3
23
3
321CT 6 5
3
32
3
321CT 6 4
3
132
3
321TT 10 9
3
132
3
123TT 10 9
3
123
3
132TT 10 9
IV. EXPERIMENTAL RESULTS
Experiments on 3-bits reversible circuitsโ synthesis are presented using the ๐๐ถ๐ library, the Schreier-
Sims algorithm [14] is implemented using the group-theory algebraic software GAP [22]. This algorithm deals
with minimal number of generator problems, which is more reasonable in practice because the gates have
different costs. Some papers discussed these problems by other methods such as [13] and [14] but the Schreier-
Sims algorithm realized in GAP [22] gives the similar minimal length problems result as shown in [13] and [14]
and better results to minimize the quantum cost by applying the optimization rules as will be shown later.
Table 2 and Table 3 show the results for the main ๐๐ถ๐ gate library as a universal reversible library for
reversible computation since it can realize the 40320 possible 3-in/out reversible circuits. Table 3 gives the same
result as Table 2 with more details on the cost of minimum length. The main ๐๐ถ๐ gate library synthesizes the
best maximum length circuits, where the best maximum length = 8 gates with cost = 21 and maximum cost = 25
with circuit length = 7. Using group-theory algebraic software GAP [22] shows that the average length of a
reversible circuit synthesized with ๐๐ถ๐ library is 5.865 which is similar to that shown in [13] and [14].
Table 4 and Table 5 show the results for the sub-libraries of the main ๐๐ถ๐ gate library which
synthesize the best maximum cost circuits, where the best maximum cost = 17 with circuit length = 7 and
maximum length = 12 with cost = 14. Table 5 gives the same result as Table 4 with more details on the length of
minimum cost. Using group-theory algebraic software GAP [22] and apply the optimization rules to calculate
the quantum cost of reversible circuits show that the average cost of reversible circuits synthesized with ๐๐ถ๐
library is 11.459.
Table 2: Number of circuits with minimum length
Mini-
length
NCT-
Circuits
NCT-
Circuits[14]
NCT-
Circuits[13]
0 1 1 1
1 12 12 12
2 102 102 102
3 625 625 625
4 2780 2780 2780
5 8921 8921 8921
6 17049 17049 17049
7 10253 10253 10253
8 577 577 577
Total 40320 40320 40320
Average 5.865 5.865 5.865
7. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 75 | Page
V. INTEGRATION OF IRREVERSIBLE BOOLEAN FUNCTIONS IN A REVERSIBLE CIRCUIT
This section shows that if a set of irreversible Boolean function can be integrated by an even parity
permutation that has a cycle representation, then the set of irreversible Boolean functions can be realized by a
reversible circuit using ๐๐ถ๐ library. This provides a concrete realizations for several families of Boolean
functions such as ๐ด๐๐ท ๐ฅ1 โง ๐ฅ2 , ๐๐ ๐ฅ1 โจ ๐ฅ2 , ๐๐๐ ๏ ๐ฅ1 , ๐๐๐ ๐ฅ1โจ๐ฅ2 , ๐๐ด๐๐ท ๐ฅ1 โ ๐ฅ2 , ๐๐๐ ๐ฅ1 โ ๐ฅ2 .
For the sake of readability, this will be written shortly as ๐ด๐๐ท, ๐๐ , ๐๐๐, ๐๐๐ , ๐๐ด๐๐ท, and ๐๐๐ respectively.
There exist 8 basics combination of three different irreversible Boolean functions which are
{{๐ด๐๐ท, ๐๐ , ๐๐๐}, {๐ด๐๐ท, ๐๐๐, ๐๐๐ }, {๐ด๐๐ท, ๐๐๐, ๐๐๐ }, {๐๐ , ๐๐๐, ๐๐๐ }, {๐๐ , ๐๐๐, ๐๐ด๐๐ท},
{๐๐๐, ๐๐๐ , ๐๐ด๐๐ท}, {๐๐๐, ๐๐๐ , ๐๐๐ }, {๐๐๐, ๐๐ด๐๐ท, ๐๐๐ }} . Each basic combination of three different
irreversible Boolean functions has 6 possible permutations, and then we have totally 48 possible combinations
of three different irreversible Boolean functions. For example, the reversible circuit to implement the set
{๐ด๐๐ท, ๐๐ , ๐๐๐} has six different forms, i.e. (๐ด๐๐ท, ๐๐ , ๐๐๐) means that the first output line will be
๐ด๐๐ท ๐ฅ1 โง ๐ฅ2 , the second output line will be ๐๐ ๐ฅ1 โจ ๐ฅ2 and the third line will be ๐๐๐ ๏ ๐ฅ1 which is
different from (๐ด๐๐ท, ๐๐๐, ๐๐ ) which means that the first output line will be ๐ด๐๐ท ๐ฅ1 โง ๐ฅ2 , the second output
line be ๐๐๐ ๏ ๐ฅ1 and the third output line will be ๐๐ ๐ฅ1 โจ ๐ฅ2 as shown in Fig.10.
Setting the input to ๐ฅ1, ๐ฅ2, 0 , i.e. the third bit is initialized to 0, all the possible combinations of three
different irreversible Boolean functions can be integrated by an even parity permutation that has a cycle
representation and can be realized by reversible circuit as will be shown in Table 6. For example, the
combination of (๐ด๐๐ท, ๐๐ , ๐๐๐) can be integrated by a cyclic permutation equal (1, 2) (3, 4, 5) and can be
realized by reversible circuit [๐ถ12
3
, ๐ถ13
3
, ๐321
3
, ๐3
3
, ๐ถ12
3
] with best minimum cost equal 8 as shown in Fig.10.
Figure 10: The reversible circuit realizes the combination of (๐ด๐๐ท, ๐๐ , ๐๐๐) with the input ๐ฅ1, ๐ฅ2, 0 .
Setting the input to ๐ฅ1, ๐ฅ2, 1 , i.e. the third bit is initialized to 1, all the possible combinations of three
different irreversible Boolean functions can be integrated by an even parity permutation that has a cycle
representation and can be realized by reversible circuit as will be shown in Table 7. For example, the
combination of three different irreversible Boolean functions (๐๐ , ๐ด๐๐ท, ๐๐๐) can be integrated by a cyclic
permutation equal (4, 6, 5) (7, 8) and can be realized by reversible circuit [๐ถ12
3
, ๐ถ13
3
, ๐321
3
, ๐ถ12
3
] with best
minimum cost equal 8 as shown in Fig.11.
3 3 51 8 4 174 12 6 2366 15 8 700
3 4 282 8 5 1283 12 7 2018 15 9 273
3 5 75 8 6 1531 12 8 799 15 10 33
4 2 3 8 7 513 12 9 186 16 4 3
4 3 12 8 8 56 12 10 5 16 5 122
4 4 78 8 9 8 13 3 1 16 6 756
4 5 387 9 2 3 13 4 8 16 7 1321
4 6 48 9 3 22 13 5 170 16 8 1110
5 1 3 9 4 74 13 6 1378 16 9 670
5 2 18 9 5 332 13 7 1395 16 10 120
5 3 57 9 6 1318 13 8 618 17 5 11
5 4 120 10 2 3 13 9 292 17 6 203
5 5 140 10 3 43 13 10 109 17 7 424
5 6 202 10 4 228 13 11 12 17 8 323
5 7 1 10 5 618 14 3 4 17 9 369
6 2 18 10 6 908 14 4 42 17 10 353
6 3 123 10 7 579 14 5 180 17 11 155
6 4 298 10 8 153 14 6 445 17 12 13
6 5 429 10 9 13 14 7 545
6 6 215 11 3 18 14 8 254
10. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 78 | Page
Table 8: Comparison between the possible combinations of Boolean functions which realize the reversible
circuits with best minimum cost and length while the inputs ๐ฅ1, ๐ฅ2, 0 and ๐ฅ1, ๐ฅ2, 1 .
Input ๐ฅ1, ๐ฅ2, 0
Basic Possible
Combinations
Reversible
Circuits implementation
Mini-Cost Length
(AND, OR, NOT) [๐ถ12
3
, ๐ถ13
3
, ๐321
3
, ๐3
3
, ๐ถ12
3
] 8 5
(AND, XOR ,NOT) [ ๐ถ13
3
, ๐132
3
, ๐321
3
, ๐3
3
] 11 4
(NOT, NOR,AND) ๐2
3
, ๐ถ12
3
, ๐ถ31
3
, ๐123
3
, ๐132
3
, ๐1
3 11 6
(XOR, OR, NOT) [๐3
3
, ๐321
3
, ๐ถ12
3
, ๐ถ23
3
, ๐132
3
] 12 5
(NOT, NAND,OR) [๐1
3
, ๐2
3
, ๐321
3
, ๐123
3
, ๐ถ12
3
, ๐ถ32
3
, ๐3
3
] 10 7
(XOR, NOT, NAND) [๐2
3
, ๐3
3
, ๐ถ21
3
, ๐132
3
, ๐123
3
, ๐1
3
, ๐2
3
] 10 7
(NOT, XOR, NOR) [๐2
3
, ๐3
3
, ๐132
3
, ๐ถ31
3
, ๐3
3
, ๐123
3
, ๐2
3
] 10 7
(NAND, NOR, NOT) [๐2
3
, ๐123
3
, ๐1
3
, ๐ถ21
3
, ๐ถ31
3
, ๐ถ13
3
] 8 6
Input ๐ฅ1, ๐ฅ2, 1
Basic Possible
Combinations
Reversible
Circuits implementation
Mini-Cost Length
(OR, AND, NOT) [๐ถ12
3
, ๐ถ13
3
, ๐321
3
, ๐ถ12
3
] 8 4
(AND, NOT, XOR) [๐ถ23
3
, ๐ถ12
3
, ๐321
3
, ๐ถ32
3
, ๐ถ23
3
] 7 5
(NOT, NOR, AND) [๐1
3
, ๐3
3
, ๐123
3
, ๐132
3
, ๐ถ31
3
, ๐ถ13
3
] 10 6
(OR, XOR, NOT) [๐ถ12
3
, ๐ถ13
3
, ๐321
3
] 7 3
(NOT, OR, NAND) [๐1
3
, ๐ถ31
3
, ๐123
3
, ๐132
3
, ๐1
3
] 10 5
(NAND ,NOT, XOR) [๐1
3
, ๐ถ21
3
, ๐ถ12
3
, ๐1
3
, ๐ถ13
3
, ๐321
3
, ๐3
3
] 8 7
(NOR, XOR, NOT) [๐1
3
, ๐ถ31
3
, ๐ถ12
3
, ๐ถ13
3
, ๐1
3
, ๐321
3
] 8 6
(NOR, NAND, NOT) [๐1
3
, ๐123
3
, ๐ถ32
3
, ๐3
3
, ๐ถ31
3
, ๐ถ13
3
] 8 6
VI. CONCLUSION
By reducing the representation of the reversible circuit synthesis problem to permutation group,
Schreier-Sims Algorithm for the strong generating set-finding problem is used to synthesize reversible circuits
with minimal length. Applying the proposed optimization rules on the synthesized circuits gives better quantum
cost to be 11.459 better than other results shown in the literature. The minimal length of a reversible circuit is
obtained by using the main ๐๐ถ๐ library which the minimal quantum cost is obtained from using a sub library
from the main ๐๐ถ๐ library.
Digital logic design is a well established area of research where classical Boolean functions in used in
the construction process. Classical Boolean functions are mainly irreversible and cannot be used directly in the
reversible circuitsโ synthesis. It was shown how to integrate any three Boolean functions in a single reversible
circuit using the ๐๐ถ๐ library. It was shown that the order of the Boolean function in the output vector affects the
efficiency of the circuit. There are two ways to initialize the input vector, ๐ฅ1, ๐ฅ2, 0 and ๐ฅ1, ๐ฅ2,1 . It was
shown that initializing the input vector to ๐ฅ1, ๐ฅ2, 1 gives better results with respect to the length and the
quantum cost of the circuit.
ACKNOWLEDGEMENTS
We would like to thank Dr Ragab Omar, Department of Mathematics, Faculty of Science, Damanhour
University, Egypt for their help and encouragement.
References
[1]. C. Bennett, Logical reversibility of computation. IBM Journal of Research and Development, 17(6):525-532 (1973).
[2]. E. Fredkin, and T. Toffoli, Conservative logic, International Journal of Theoretical Physics, 21:219-253 (1982).
[3]. J. Gruska, Quantum computing, McGraw-Hill, London (1999).
[4]. M. Nielsen, and I. Chuang, Quantum computation and quantum information, Cambridge University Press, Cambridge, United
Kingdom (2000).
[5]. A. De Vos, B. Desoete, A. Adamski, P. Pietrzak, M. Sibinski, and T. Widerski, Design of reversible logic circuits by means of
control gates, Proc. 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and
Simulation, pages 255-264 (2000).
[6]. A. De Vos, B. Desoete, F. Janiak, and A. Nogawski, Control gates as building blocks for reversible computers, Proc. 11th
International Workshop on Power and Timing Modeling, Optimization and Simulation, pages 9201--9210 (2001).
[7]. T. Toffoli. Reversible computing. InW. de Bakker, and J. van Leeuwen, editors, Automata, Languages and Programming, page 632.
Springer, New York, 1980. Technical Memo MIT/LCS/TM-151, MIT Lab for Computer Science.
[8]. D. Simon, On the power of quantum computation, Proc. 35th Annual Symposium on Foundations of Computer Science, pages 116-
123 (1994).
[9]. A. De Vos, B. Raa, and L. Storme, Generating the group of reversible logic gates, Journal of Physics A: Mathematical and General,
35(33): 7063-7078 (2002).
[10]. L. Storme, A. De Vos, and G. Jacobs, Group theoretical aspects of reversible logic gates, Journal of Universal Computer Science,
5(5): 307-321 (1999).
[11]. A. De Vos, and Y. V. Rentergem, From group theory to reversible computers. International Journal of Unconventional Computing,
4(1): 79-88 (2008).
11. Integration of Irreversible Gates in Reversible Circuits Using NCT Library
www.iosrjournals.org 79 | Page
[12]. A. De Vos and S. De Baerdemacker, Symmetry groups for the decomposition of reversible computers, quantum computers, and
computers in between. Symmetry, 3(2): 305-324 (2011).
[13]. G. Yang, X. Song, W. N.N. Hung, M. A. Perkowski, and C.-J. Seo, Synthesis of reversible circuits with minimal costs, CALCOLO,
45:193โ206, 2008.
[14]. A. Younes, Tight bounds on the synthesis of 3-bit reversible circuits: NFT library, arXiv:1304.5804v2 (2013).
[15]. A. Seress, Permutation group algorithms, Cambridge University Press (2002).
[16]. M.I. Kargapolov, and Ju.I. Merzljakov, Fundamentals of the theory of groups, Berlin: Springer (1979).
[17]. J.D. Dixon, and B. Mortimer, Permutation groups, New York: Springer (1996).
[18]. A. Younes, A single universal n-bit gate for reversible circuit synthesis, arXiv: 1306.1254v1 (2013).
[19]. A. Barenco, C. H. Bennett, R. Cleve, D. P. DiVincenzo, N. Margolus, P. Shor, T. Sleator, J. A. Smolin, and H. Weinfurter,
Elementary gates for quantum computation, Physical Review A, 52(5):3457โ 3467 (1995).
[20]. J.A. Smolin and D.P. DiVincenzo, Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate, Physical
Review A, 53, 2855-2856 (1996).
[21]. D. Maslov, Reversible logic synthesis benchmarks, [Online], Available: http://www.cs.uvic.ca/โผdmaslov/.
[22]. The GAP Group. GAP โ Groups, algorithms, and programming, Version 4.6.3; 2013. Available: http://www.gap-system.org