This document presents a proposed real-time controller for efficiently retrieving multimedia data from secured digital high capacity cards. The controller is implemented entirely using hardware description language on an FPGA chip, without any other external hardware or high-level languages. The controller contains 5 modules - Card Initialization Module, Idle Module, Card Access Module, Card Store Module, and Decision Making Module. Experimental results show the architecture uses less hardware and clock cycles for card initialization and single/multi-block read/write operations with microSD and SDHC cards of different sizes.
Fpga based 128 bit customised vliw processor for executing dual scalarvector ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
FPGA Hardware Accelerator for Machine Learning
Machine learning publications and models are growing exponentially, outpacing Moore's law. Hardware acceleration using FPGAs, GPUs, and ASICs can provide performance gains over CPU-only implementations for machine learning workloads. FPGAs allow for reprogramming after manufacturing and can accelerate parts of machine learning algorithms through customized hardware while sharing computations between the FPGA and CPU. Vitis AI is a software stack that optimizes machine learning models for deployment on Xilinx FPGAs, providing pre-optimized models, tools for optimization and quantization, and high-level APIs.
IRJET- SD Card based File System for CNC Machine using TMS320F2837XD Proc...IRJET Journal
This document describes a system that implements an SD card-based file system for a CNC machine using a TMS320F2837xD dual-core DSP processor. The system uses an SD card for mass storage of files, interfaced with the DSP processor via SPI communication. Software is developed using C code in Code Composer Studio to implement FAT32 file handling functions and convert text-based CNC files into a machine-readable format for tool processing and operation by the CNC machine. This reduces file and tool processing times compared to previous systems.
Hardware Acceleration for Machine LearningCastLabKAIST
This document provides an overview of a lecture on hardware acceleration for machine learning. The lecture will cover deep neural network models like convolutional neural networks and recurrent neural networks. It will also discuss various hardware accelerators developed for machine learning, including those designed for mobile/edge and cloud computing environments. The instructor's background and the agenda topics are also outlined.
International Journal of Computational Engineering Research(IJCER) ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
xCORE products are designed from the ground up to solve problems that are beyond traditional microcontrollers:
- Multiple deterministic processor cores that can execute several tasks simultaneously and independently.
- External interfaces and peripherals are implemented in software – you choose the exact combination of interfaces you need.
- Perform static timing analysis and hardware-like simulations on your designs, using unique development tools that use the determinism of the architecture.
- Test on real hardware and collect real-time data from a running application.
The unparalleled responsiveness of the xCORE I/O ports is rooted in some fundamental features:
- Single cycle instruction execution
- No interrupts
- No cache
- Multiple cores allow concurrent independent task execution
- Hardware scheduler performs 'RTOS-like' functions
IIT-Madras is developing an adaptive fabric-based architecture called ASF to support exascale systems. ASF will integrate memory, computing, storage and networking through a unified hybrid memory and I/O fabric. It will allow CPUs to dynamically configure interconnects and allow computation to move to where data is located. The intelligence will reside in adaptive fabric routers. IIT-Madras is defining components like the memory fabric, compute fabric, storage nodes, and microkernel OS to take advantage of the adaptive fabric.
The Shakti processor roadmap outlines seven microarchitecture variants for the family of RISC-V processors being developed by IIT Madras' Computer Architecture and Systems Lab. The variants include C-class microcontrollers, I-class general purpose processors, M-class mobile/desktop processors, S-class server processors, H-class high performance computing processors, and experimental T-class security processors. Each variant is tailored for different performance and functionality requirements, with optional features like memory protection, floating point units, and acceleration modules. The toolchain will include GCC and Linux for most variants, with message passing and a lightweight L4 microkernel also supported.
Fpga based 128 bit customised vliw processor for executing dual scalarvector ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
FPGA Hardware Accelerator for Machine Learning
Machine learning publications and models are growing exponentially, outpacing Moore's law. Hardware acceleration using FPGAs, GPUs, and ASICs can provide performance gains over CPU-only implementations for machine learning workloads. FPGAs allow for reprogramming after manufacturing and can accelerate parts of machine learning algorithms through customized hardware while sharing computations between the FPGA and CPU. Vitis AI is a software stack that optimizes machine learning models for deployment on Xilinx FPGAs, providing pre-optimized models, tools for optimization and quantization, and high-level APIs.
IRJET- SD Card based File System for CNC Machine using TMS320F2837XD Proc...IRJET Journal
This document describes a system that implements an SD card-based file system for a CNC machine using a TMS320F2837xD dual-core DSP processor. The system uses an SD card for mass storage of files, interfaced with the DSP processor via SPI communication. Software is developed using C code in Code Composer Studio to implement FAT32 file handling functions and convert text-based CNC files into a machine-readable format for tool processing and operation by the CNC machine. This reduces file and tool processing times compared to previous systems.
Hardware Acceleration for Machine LearningCastLabKAIST
This document provides an overview of a lecture on hardware acceleration for machine learning. The lecture will cover deep neural network models like convolutional neural networks and recurrent neural networks. It will also discuss various hardware accelerators developed for machine learning, including those designed for mobile/edge and cloud computing environments. The instructor's background and the agenda topics are also outlined.
International Journal of Computational Engineering Research(IJCER) ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
xCORE products are designed from the ground up to solve problems that are beyond traditional microcontrollers:
- Multiple deterministic processor cores that can execute several tasks simultaneously and independently.
- External interfaces and peripherals are implemented in software – you choose the exact combination of interfaces you need.
- Perform static timing analysis and hardware-like simulations on your designs, using unique development tools that use the determinism of the architecture.
- Test on real hardware and collect real-time data from a running application.
The unparalleled responsiveness of the xCORE I/O ports is rooted in some fundamental features:
- Single cycle instruction execution
- No interrupts
- No cache
- Multiple cores allow concurrent independent task execution
- Hardware scheduler performs 'RTOS-like' functions
IIT-Madras is developing an adaptive fabric-based architecture called ASF to support exascale systems. ASF will integrate memory, computing, storage and networking through a unified hybrid memory and I/O fabric. It will allow CPUs to dynamically configure interconnects and allow computation to move to where data is located. The intelligence will reside in adaptive fabric routers. IIT-Madras is defining components like the memory fabric, compute fabric, storage nodes, and microkernel OS to take advantage of the adaptive fabric.
The Shakti processor roadmap outlines seven microarchitecture variants for the family of RISC-V processors being developed by IIT Madras' Computer Architecture and Systems Lab. The variants include C-class microcontrollers, I-class general purpose processors, M-class mobile/desktop processors, S-class server processors, H-class high performance computing processors, and experimental T-class security processors. Each variant is tailored for different performance and functionality requirements, with optional features like memory protection, floating point units, and acceleration modules. The toolchain will include GCC and Linux for most variants, with message passing and a lightweight L4 microkernel also supported.
Reliable Hydra SSD Architecture for General Purpose ControllersIJMER
The Solid State Disks (SSDs) had almost replaced the traditional Hard Disk Drives (HDDs) in modern computing systems. SSDs possess advanced features such as low power consumption, faster random access and greater shock resistance. In general, NAND Flash memories are used for bulk storage applications. This project focus on an advanced SSD architecture, called Reliable Hydra to enhance the SSD performance. Hydra SSDs overcomes the discrepancy between slow flash memory bus and fast host interfaces like SATA, SCSI, USB etc. It uses multiple high level memory controllers to execute flash memory operation without the intervention of FTL (Flash Translation Layer). It accelerates the processing of host write requests by aggressive write buffering. Memories are subjected to bit flipping errors, so this project also considers the incorporation of matrix code for increasing the reliability and hence yield of the system. The highly sophisticated controllers for real time systems in the industrial, robotics, medical and scientific applications require high performance and reliable memories. The aim of this project is to design Reliable Hydra SSD architecture for controller applications to enhance the performance. The design architecture is to be coded in VHDL using Xilinx ISE tools.
GENERIC SOPC PLATFORM FOR VIDEO INTERACTIVE SYSTEM WITH MPMC CONTROLLERijesajournal
Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context,
a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC.
The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the
deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Smartphone fpga based balloon payload using cots componentseSAT Journals
Abstract
This paper describes a low cost architecture of multi sensor remote sensing balloon payload design for prototyping student’s micro-satellite payload project. Commercial off the Shelf (COTS) components are being used to implement the payload instrumentation. COTS components provide high processing performance, low power consumption, high reliability, low cost and are easily available. The main architecture of the system consists of commercially available Smartphone, FPGA (field-programmable gate-array) and microcontroller connected together along with sensors and telemetry systems.
Presently available smart phones are combination of multiple advanced sensors, different communication channels, powerful operating system and multi-core processors with large non-volatile memory. This also supports high resolution imaging devices for remote sensing application. The smart phone is interfaced to a microcontroller to expand its I/O to interface sensors and FPGA. FPGA supported high speed onboard parallel processing needs and complex controls. Flexible configurations for data acquisition system is provided using built-in A/D converters, counters and timers available in FPGA and microcontroller. The proposed system is an experimental balloon payload for monitoring atmospheric parameters like temperature, humidity, air pollution etc. This can also monitor city traffic, agricultural field and city landscape for security and surveillance.
Keywords: Tethered Balloon, Sensors, Payload, Smartphone, FPGA, Microcontroller
Silicon Motion's PCIe FerriSSD : High speed and reliability for digital signageSilicon Motion
The document discusses the requirements for storage devices used in digital signage equipment. Consumer-grade storage is not suitable due to insufficient performance, reliability, and longevity required by digital signage. The Silicon Motion PCIe FerriSSD storage solution is presented as ideal for digital signage as it provides high read/write speeds for streaming 4K video, error correction to ensure flawless content display, and technology to maintain storage capacity over the long operational lifetimes required of digital signage equipment.
The Open Channel architecture is providing a new model for the control and operation of individual SSD devices in data centers which serve multiple tenants and applications.
Top 10 Supercomputers With Descriptive Information & AnalysisNomanSiddiqui41
Top 10 Supercomputers Report
What is Supercomputer?
A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second (FLOPS) instead of million instructions per second (MIPS). Since 2017, there are supercomputers which can perform over 1017 FLOPS (a hundred quadrillion FLOPS, 100 petaFLOPS or 100 PFLOPS
Supercomputers play an important role in the field of computational science, and are used for a wide range of computationally intensive tasks in various fields, including quantum mechanics, weather forecasting, climate research, oil and gas exploration, molecular modeling (computing the structures and properties of chemical compounds, biological macromolecules, polymers, and crystals), and physical simulations (such as simulations of the early moments of the universe, airplane and spacecraft aerodynamics, the detonation of nuclear weapons, and nuclear fusion). They have been essential in the field of cryptanalysis.
1. The Fugaku Supercomputer
Introduction:
Fugaku is a petascale supercomputer (while only at petascale for mainstream benchmark), at the Riken Center for Computational Science in Kobe, Japan. It started development in 2014 as the successor to the K computer, and started operating in 2021. Fugaku made its debut in 2020, and became the fastest supercomputer in the world in the June 2020 TOP500 list, as well as becoming the first ARM architecture-based computer to achieve this. In June 2020, it achieved 1.42 exaFLOPS (in HPL-AI benchmark making it the first ever supercomputer that achieved 1 exaFLOPS. As of November 2021, Fugaku is the fastest supercomputer in the world. It is named after an alternative name for Mount Fuji.
Block Diagram:
Functional Units:
Functional Units, Co-Design and System for the Supercomputer “Fugaku”
1. Performance estimation tool: This tool, taking Fujitsu FX100 (FX100 is the previous Fujitsu supercomputer) execution profile data as an input, enables the performance projection by a given set of architecture parameters. The performance projection is modeled according to the Fujitsu microarchitecture. This tool can also estimate the power consumption based on the architecture model.
2. Fujitsu in-house processor simulator: We used an extended FX100 SPARC instruction-set simulator and compiler, developed by Fujitsu, for preliminary studies in the initial phase, and an Armv8þSVE simulator and compiler afterward.
3. Gem5 simulator for the Post-K processor: The Post-K processor simulator3 based on an opensource system-level processor simulator, Gem5, was developed by RIKEN during the co-design for architecture verification and performance tuning. A fundamental problem is the scale of scientific applications that are expected to be run on Post-K. Even our target applications are thousands of lines of code and are written to use complex algorithms and data structures. Altho
Driving cycle tracking device big data storing and managementIJECEIAES
This document describes the development of a driving cycle tracking device (DC-TRAD) that collects and stores big data to help construct accurate driving cycles. The DC-TRAD uses an ESP32 microcontroller connected to a NEO-7 GPS module to collect location, speed, date and time data. This data is uploaded and stored instantly in a MySQL database using phpMyAdmin through an IoT platform. The stored big data can then be accessed and viewed through a website log to help analyze driving behavior and conditions for applications like vehicle emissions testing and manufacturing more efficient vehicles.
IRJET- ALPYNE - A Grid Computing FrameworkIRJET Journal
The document describes Alpyne, a grid computing framework built using Python. It aims to make setting up a grid computing system easy by providing libraries, APIs, and applications. Key features include load balancing across nodes based on their computing power, high availability, failure management, and a web UI. The framework uses Docker containers for virtualization and MongoDB for data storage, with modular interfaces that can be replaced. It aims to more easily support Python applications on grids compared to existing frameworks like Hadoop and Spark.
Designing of telecommand system using system on chip soc for spacecraft contr...IAEME Publication
The emerging developments in semiconductor technology have made possible to design
entire system onto a single chip, commonly known as System-On-Chip (SoC). The increase in Space
System‘s capabilities by the On-board data processing capabilities can be overcome by optimizing
the SoCs to provide cost effective, high performance, and reliable data. This is achieved by
embedding pre-designed functions into a single SoC, which utilizes specialized reusable core (IP
cores) architecture into complex chip. This paper is concerned with the design of Telecommand
system for transfer of signals from ground station to space station by the integration of SRAM (Static
Random Access Memory), ARM (Advanced RISC Machine) Processor, EDAC unit (Error Detection
and Correction) and CCSDS (Consultative Committee for Space Data System) decoder system. In
this paper we designed the Telecommand SoC by using Verilog code. The implementations have
been done using XILINX FPGA platform and the functionality of the system is verified using
Modelsim simulation. The results are analyzed for SPARTAN 3E device and ARM board and two
devices are being controlled by the signal transfer.
Designing of telecommand system using system on chip soc for spacecraft contr...IAEME Publication
This document describes the design of a telecommand system using a System on Chip (SoC) for spacecraft control applications. It involves integrating various components onto a single chip, including SRAM, an ARM processor, and an Error Detection and Correction (EDAC) unit. The telecommand data is received and stored in the SRAM. The EDAC unit uses a Hamming code to detect and correct any errors in the data before it is processed by the ARM processor. The processor then collects onboard data signals and produces the output result. Verilog code is used to design the SoC, which is implemented and tested on a Xilinx FPGA platform and ARM board. The SoC allows two devices to be controlled by
SECURE FILE STORAGE IN THE CLOUD WITH HYBRID ENCRYPTIONIRJET Journal
The document proposes a new public audit program for secure cloud storage using a dynamic hash table (DHT) data structure. A DHT would store data integrity information in the Third Party Auditor (TPA) to reduce computational costs and communication overhead compared to previous schemes. The approach combines public-key-based homomorphic authenticators with a TPA-generated random mask to achieve data protection and batch verification. This allows the cloud storage system to meet security requirements for data confidentiality, integrity, and availability while improving audit efficiency.
HYBRID MODEL IN THE BLOCK CIPHER APPLICATIONS FOR HIGH-SPEED COMMUNICATIONS N...IJCNCJournal
The article proposes two different designs for the new block cipher algorithm of 128-bit block size and key lengths of 128-bit or 192-bit or 256-bit. The basic cipher round is designed in a parallel model to help improve the encryption/decryption speed. The differences of this design compared to the previous one
developed on Switchable Data Dependent Operations (SDDOs) lies in the hybrid of the controlled elements (CEs) in the structure. Each design has a specific strength that makes the selection more compatible with the objectives of each particular application. The designs all meet the high security standards and possess the ability to fight off the attacks currently known. The designs match the limited environment of the wireless network by integrating effectively when implemented on Field-programmable gate array (FPGA) with both iterative and pipeline architectures for high effective integration.
HYBRID MODEL IN THE BLOCK CIPHER APPLICATIONS FOR HIGH-SPEED COMMUNICATIONS N...IJCNCJournal
The article proposes two different designs for the new block cipher algorithm of 128-bit block size and key lengths of 128-bit or 192-bit or 256-bit. The basic cipher round is designed in a parallel model to help improve the encryption/decryption speed. The differences of this design compared to the previous one developed on Switchable Data Dependent Operations (SDDOs) lies in the hybrid of the controlled elements (CEs) in the structure. Each design has a specific strength that makes the selection more compatible with
the objectives of each particular application. The designs all meet the high security standards and possess the ability to fight off the attacks currently known. The designs match the limited environment of the wireless network by integrating effectively when implemented on Field-programmable gate array (FPGA) with both iterative and pipeline architectures for high effective integration.
GridGain Systems provides an in-memory data grid (IMDG) that offers extremely low latency access to application data stored fully in memory. Key features of GridGain's IMDG include support for distributed ACID transactions, scalable data partitioning, integration with in-memory compute grids, and datacenter replication to ensure high availability. The IMDG allows applications to work directly with domain objects and provides SQL querying capabilities for fast analysis of in-memory data.
Performance of State-of-the-Art Cryptography on ARM-based MicroprocessorsHannes Tschofenig
Position paper for the NIST Lightweight Cryptography Workshop, 20th and 21st July 2015, Gaithersburg, US.
The link to the workshop is available at: http://www.nist.gov/itl/csd/ct/lwc_workshop2015.cfm
Design and Implementation of Quintuple Processor Architecture Using FPGAIJERA Editor
The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.
Exploiting Multi Core Architectures for Process Speed UpIJERD Editor
The document discusses exploiting multi-core architectures to speed up processing of satellite data. It describes developing a multithreaded application using a master-slave model to parallelize preprocessing steps like extracting auxiliary data, Reed-Solomon decoding, and decompression. Performance analysis shows the application scales dynamically based on system resources and achieves maximum speedup when assigning 7 threads per core. While theoretical speedup is limited by Amdahl's law, accounting for parallelization overhead provides a more realistic performance measure.
Re-SPark: Reservation based Smart Parking system using FRDM KL-25ZIRJET Journal
The document describes a prototype of a smart parking system called Re-SPark that uses a sensor network and mobile application to allow users to reserve parking spots in advance. The system detects the occupancy status of individual parking spots using infrared sensors and transmits the data to a database via a wireless module. Users can then access the real-time parking availability data through a mobile app or website to reserve vacant spots. The prototype implementation consists of hardware with IR sensors connected to a microcontroller board and Wi-Fi module, as well as an Android app to allow users to reserve spots and receive confirmation through QR codes.
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
More Related Content
Similar to IRJET-An Efficient Real-Time Controller for Retrieving Multimedia Data from Secured Digital High Capacity Card
Reliable Hydra SSD Architecture for General Purpose ControllersIJMER
The Solid State Disks (SSDs) had almost replaced the traditional Hard Disk Drives (HDDs) in modern computing systems. SSDs possess advanced features such as low power consumption, faster random access and greater shock resistance. In general, NAND Flash memories are used for bulk storage applications. This project focus on an advanced SSD architecture, called Reliable Hydra to enhance the SSD performance. Hydra SSDs overcomes the discrepancy between slow flash memory bus and fast host interfaces like SATA, SCSI, USB etc. It uses multiple high level memory controllers to execute flash memory operation without the intervention of FTL (Flash Translation Layer). It accelerates the processing of host write requests by aggressive write buffering. Memories are subjected to bit flipping errors, so this project also considers the incorporation of matrix code for increasing the reliability and hence yield of the system. The highly sophisticated controllers for real time systems in the industrial, robotics, medical and scientific applications require high performance and reliable memories. The aim of this project is to design Reliable Hydra SSD architecture for controller applications to enhance the performance. The design architecture is to be coded in VHDL using Xilinx ISE tools.
GENERIC SOPC PLATFORM FOR VIDEO INTERACTIVE SYSTEM WITH MPMC CONTROLLERijesajournal
Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. In this context,
a prototype system is developed based on the Xilinx Virtex-5 FPGA with the integration of embedded processors, embedded memory, DDR, interface technologies, Digital Clock Managers (DCM) and MPMC.
The MPMC is an essential component for design performance tuning and real time video processing. We demonstrate the importance role of this interface in multi video applications. In fact, to successful the
deployment of DRAM it is mandatory to use a flexible and scalable interface. Our system introduces diverse modules, such as cut video detection, video zoom-in and out. This provides the utility of using this architecture as a universal video processing platform according to different application requirements. This platform facilitates the development of video and image processing applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Smartphone fpga based balloon payload using cots componentseSAT Journals
Abstract
This paper describes a low cost architecture of multi sensor remote sensing balloon payload design for prototyping student’s micro-satellite payload project. Commercial off the Shelf (COTS) components are being used to implement the payload instrumentation. COTS components provide high processing performance, low power consumption, high reliability, low cost and are easily available. The main architecture of the system consists of commercially available Smartphone, FPGA (field-programmable gate-array) and microcontroller connected together along with sensors and telemetry systems.
Presently available smart phones are combination of multiple advanced sensors, different communication channels, powerful operating system and multi-core processors with large non-volatile memory. This also supports high resolution imaging devices for remote sensing application. The smart phone is interfaced to a microcontroller to expand its I/O to interface sensors and FPGA. FPGA supported high speed onboard parallel processing needs and complex controls. Flexible configurations for data acquisition system is provided using built-in A/D converters, counters and timers available in FPGA and microcontroller. The proposed system is an experimental balloon payload for monitoring atmospheric parameters like temperature, humidity, air pollution etc. This can also monitor city traffic, agricultural field and city landscape for security and surveillance.
Keywords: Tethered Balloon, Sensors, Payload, Smartphone, FPGA, Microcontroller
Silicon Motion's PCIe FerriSSD : High speed and reliability for digital signageSilicon Motion
The document discusses the requirements for storage devices used in digital signage equipment. Consumer-grade storage is not suitable due to insufficient performance, reliability, and longevity required by digital signage. The Silicon Motion PCIe FerriSSD storage solution is presented as ideal for digital signage as it provides high read/write speeds for streaming 4K video, error correction to ensure flawless content display, and technology to maintain storage capacity over the long operational lifetimes required of digital signage equipment.
The Open Channel architecture is providing a new model for the control and operation of individual SSD devices in data centers which serve multiple tenants and applications.
Top 10 Supercomputers With Descriptive Information & AnalysisNomanSiddiqui41
Top 10 Supercomputers Report
What is Supercomputer?
A supercomputer is a computer with a high level of performance as compared to a general-purpose computer. The performance of a supercomputer is commonly measured in floating-point operations per second (FLOPS) instead of million instructions per second (MIPS). Since 2017, there are supercomputers which can perform over 1017 FLOPS (a hundred quadrillion FLOPS, 100 petaFLOPS or 100 PFLOPS
Supercomputers play an important role in the field of computational science, and are used for a wide range of computationally intensive tasks in various fields, including quantum mechanics, weather forecasting, climate research, oil and gas exploration, molecular modeling (computing the structures and properties of chemical compounds, biological macromolecules, polymers, and crystals), and physical simulations (such as simulations of the early moments of the universe, airplane and spacecraft aerodynamics, the detonation of nuclear weapons, and nuclear fusion). They have been essential in the field of cryptanalysis.
1. The Fugaku Supercomputer
Introduction:
Fugaku is a petascale supercomputer (while only at petascale for mainstream benchmark), at the Riken Center for Computational Science in Kobe, Japan. It started development in 2014 as the successor to the K computer, and started operating in 2021. Fugaku made its debut in 2020, and became the fastest supercomputer in the world in the June 2020 TOP500 list, as well as becoming the first ARM architecture-based computer to achieve this. In June 2020, it achieved 1.42 exaFLOPS (in HPL-AI benchmark making it the first ever supercomputer that achieved 1 exaFLOPS. As of November 2021, Fugaku is the fastest supercomputer in the world. It is named after an alternative name for Mount Fuji.
Block Diagram:
Functional Units:
Functional Units, Co-Design and System for the Supercomputer “Fugaku”
1. Performance estimation tool: This tool, taking Fujitsu FX100 (FX100 is the previous Fujitsu supercomputer) execution profile data as an input, enables the performance projection by a given set of architecture parameters. The performance projection is modeled according to the Fujitsu microarchitecture. This tool can also estimate the power consumption based on the architecture model.
2. Fujitsu in-house processor simulator: We used an extended FX100 SPARC instruction-set simulator and compiler, developed by Fujitsu, for preliminary studies in the initial phase, and an Armv8þSVE simulator and compiler afterward.
3. Gem5 simulator for the Post-K processor: The Post-K processor simulator3 based on an opensource system-level processor simulator, Gem5, was developed by RIKEN during the co-design for architecture verification and performance tuning. A fundamental problem is the scale of scientific applications that are expected to be run on Post-K. Even our target applications are thousands of lines of code and are written to use complex algorithms and data structures. Altho
Driving cycle tracking device big data storing and managementIJECEIAES
This document describes the development of a driving cycle tracking device (DC-TRAD) that collects and stores big data to help construct accurate driving cycles. The DC-TRAD uses an ESP32 microcontroller connected to a NEO-7 GPS module to collect location, speed, date and time data. This data is uploaded and stored instantly in a MySQL database using phpMyAdmin through an IoT platform. The stored big data can then be accessed and viewed through a website log to help analyze driving behavior and conditions for applications like vehicle emissions testing and manufacturing more efficient vehicles.
IRJET- ALPYNE - A Grid Computing FrameworkIRJET Journal
The document describes Alpyne, a grid computing framework built using Python. It aims to make setting up a grid computing system easy by providing libraries, APIs, and applications. Key features include load balancing across nodes based on their computing power, high availability, failure management, and a web UI. The framework uses Docker containers for virtualization and MongoDB for data storage, with modular interfaces that can be replaced. It aims to more easily support Python applications on grids compared to existing frameworks like Hadoop and Spark.
Designing of telecommand system using system on chip soc for spacecraft contr...IAEME Publication
The emerging developments in semiconductor technology have made possible to design
entire system onto a single chip, commonly known as System-On-Chip (SoC). The increase in Space
System‘s capabilities by the On-board data processing capabilities can be overcome by optimizing
the SoCs to provide cost effective, high performance, and reliable data. This is achieved by
embedding pre-designed functions into a single SoC, which utilizes specialized reusable core (IP
cores) architecture into complex chip. This paper is concerned with the design of Telecommand
system for transfer of signals from ground station to space station by the integration of SRAM (Static
Random Access Memory), ARM (Advanced RISC Machine) Processor, EDAC unit (Error Detection
and Correction) and CCSDS (Consultative Committee for Space Data System) decoder system. In
this paper we designed the Telecommand SoC by using Verilog code. The implementations have
been done using XILINX FPGA platform and the functionality of the system is verified using
Modelsim simulation. The results are analyzed for SPARTAN 3E device and ARM board and two
devices are being controlled by the signal transfer.
Designing of telecommand system using system on chip soc for spacecraft contr...IAEME Publication
This document describes the design of a telecommand system using a System on Chip (SoC) for spacecraft control applications. It involves integrating various components onto a single chip, including SRAM, an ARM processor, and an Error Detection and Correction (EDAC) unit. The telecommand data is received and stored in the SRAM. The EDAC unit uses a Hamming code to detect and correct any errors in the data before it is processed by the ARM processor. The processor then collects onboard data signals and produces the output result. Verilog code is used to design the SoC, which is implemented and tested on a Xilinx FPGA platform and ARM board. The SoC allows two devices to be controlled by
SECURE FILE STORAGE IN THE CLOUD WITH HYBRID ENCRYPTIONIRJET Journal
The document proposes a new public audit program for secure cloud storage using a dynamic hash table (DHT) data structure. A DHT would store data integrity information in the Third Party Auditor (TPA) to reduce computational costs and communication overhead compared to previous schemes. The approach combines public-key-based homomorphic authenticators with a TPA-generated random mask to achieve data protection and batch verification. This allows the cloud storage system to meet security requirements for data confidentiality, integrity, and availability while improving audit efficiency.
HYBRID MODEL IN THE BLOCK CIPHER APPLICATIONS FOR HIGH-SPEED COMMUNICATIONS N...IJCNCJournal
The article proposes two different designs for the new block cipher algorithm of 128-bit block size and key lengths of 128-bit or 192-bit or 256-bit. The basic cipher round is designed in a parallel model to help improve the encryption/decryption speed. The differences of this design compared to the previous one
developed on Switchable Data Dependent Operations (SDDOs) lies in the hybrid of the controlled elements (CEs) in the structure. Each design has a specific strength that makes the selection more compatible with the objectives of each particular application. The designs all meet the high security standards and possess the ability to fight off the attacks currently known. The designs match the limited environment of the wireless network by integrating effectively when implemented on Field-programmable gate array (FPGA) with both iterative and pipeline architectures for high effective integration.
HYBRID MODEL IN THE BLOCK CIPHER APPLICATIONS FOR HIGH-SPEED COMMUNICATIONS N...IJCNCJournal
The article proposes two different designs for the new block cipher algorithm of 128-bit block size and key lengths of 128-bit or 192-bit or 256-bit. The basic cipher round is designed in a parallel model to help improve the encryption/decryption speed. The differences of this design compared to the previous one developed on Switchable Data Dependent Operations (SDDOs) lies in the hybrid of the controlled elements (CEs) in the structure. Each design has a specific strength that makes the selection more compatible with
the objectives of each particular application. The designs all meet the high security standards and possess the ability to fight off the attacks currently known. The designs match the limited environment of the wireless network by integrating effectively when implemented on Field-programmable gate array (FPGA) with both iterative and pipeline architectures for high effective integration.
GridGain Systems provides an in-memory data grid (IMDG) that offers extremely low latency access to application data stored fully in memory. Key features of GridGain's IMDG include support for distributed ACID transactions, scalable data partitioning, integration with in-memory compute grids, and datacenter replication to ensure high availability. The IMDG allows applications to work directly with domain objects and provides SQL querying capabilities for fast analysis of in-memory data.
Performance of State-of-the-Art Cryptography on ARM-based MicroprocessorsHannes Tschofenig
Position paper for the NIST Lightweight Cryptography Workshop, 20th and 21st July 2015, Gaithersburg, US.
The link to the workshop is available at: http://www.nist.gov/itl/csd/ct/lwc_workshop2015.cfm
Design and Implementation of Quintuple Processor Architecture Using FPGAIJERA Editor
The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.
Exploiting Multi Core Architectures for Process Speed UpIJERD Editor
The document discusses exploiting multi-core architectures to speed up processing of satellite data. It describes developing a multithreaded application using a master-slave model to parallelize preprocessing steps like extracting auxiliary data, Reed-Solomon decoding, and decompression. Performance analysis shows the application scales dynamically based on system resources and achieves maximum speedup when assigning 7 threads per core. While theoretical speedup is limited by Amdahl's law, accounting for parallelization overhead provides a more realistic performance measure.
Re-SPark: Reservation based Smart Parking system using FRDM KL-25ZIRJET Journal
The document describes a prototype of a smart parking system called Re-SPark that uses a sensor network and mobile application to allow users to reserve parking spots in advance. The system detects the occupancy status of individual parking spots using infrared sensors and transmits the data to a database via a wireless module. Users can then access the real-time parking availability data through a mobile app or website to reserve vacant spots. The prototype implementation consists of hardware with IR sensors connected to a microcontroller board and Wi-Fi module, as well as an Android app to allow users to reserve spots and receive confirmation through QR codes.
Similar to IRJET-An Efficient Real-Time Controller for Retrieving Multimedia Data from Secured Digital High Capacity Card (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Gas agency management system project report.pdfKamal Acharya
The project entitled "Gas Agency" is done to make the manual process easier by making it a computerized system for billing and maintaining stock. The Gas Agencies get the order request through phone calls or by personal from their customers and deliver the gas cylinders to their address based on their demand and previous delivery date. This process is made computerized and the customer's name, address and stock details are stored in a database. Based on this the billing for a customer is made simple and easier, since a customer order for gas can be accepted only after completing a certain period from the previous delivery. This can be calculated and billed easily through this. There are two types of delivery like domestic purpose use delivery and commercial purpose use delivery. The bill rate and capacity differs for both. This can be easily maintained and charged accordingly.
Design and optimization of ion propulsion dronebjmsejournal
Electric propulsion technology is widely used in many kinds of vehicles in recent years, and aircrafts are no exception. Technically, UAVs are electrically propelled but tend to produce a significant amount of noise and vibrations. Ion propulsion technology for drones is a potential solution to this problem. Ion propulsion technology is proven to be feasible in the earth’s atmosphere. The study presented in this article shows the design of EHD thrusters and power supply for ion propulsion drones along with performance optimization of high-voltage power supply for endurance in earth’s atmosphere.
Applications of artificial Intelligence in Mechanical Engineering.pdfAtif Razi
Historically, mechanical engineering has relied heavily on human expertise and empirical methods to solve complex problems. With the introduction of computer-aided design (CAD) and finite element analysis (FEA), the field took its first steps towards digitization. These tools allowed engineers to simulate and analyze mechanical systems with greater accuracy and efficiency. However, the sheer volume of data generated by modern engineering systems and the increasing complexity of these systems have necessitated more advanced analytical tools, paving the way for AI.
AI offers the capability to process vast amounts of data, identify patterns, and make predictions with a level of speed and accuracy unattainable by traditional methods. This has profound implications for mechanical engineering, enabling more efficient design processes, predictive maintenance strategies, and optimized manufacturing operations. AI-driven tools can learn from historical data, adapt to new information, and continuously improve their performance, making them invaluable in tackling the multifaceted challenges of modern mechanical engineering.
Generative AI Use cases applications solutions and implementation.pdfmahaffeycheryld
Generative AI solutions encompass a range of capabilities from content creation to complex problem-solving across industries. Implementing generative AI involves identifying specific business needs, developing tailored AI models using techniques like GANs and VAEs, and integrating these models into existing workflows. Data quality and continuous model refinement are crucial for effective implementation. Businesses must also consider ethical implications and ensure transparency in AI decision-making. Generative AI's implementation aims to enhance efficiency, creativity, and innovation by leveraging autonomous generation and sophisticated learning algorithms to meet diverse business challenges.
https://www.leewayhertz.com/generative-ai-use-cases-and-applications/
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
Software Engineering and Project Management - Software Testing + Agile Method...Prakhyath Rai
Software Testing: A Strategic Approach to Software Testing, Strategic Issues, Test Strategies for Conventional Software, Test Strategies for Object -Oriented Software, Validation Testing, System Testing, The Art of Debugging.
Agile Methodology: Before Agile – Waterfall, Agile Development.