This document discusses input/output (I/O) in computer systems. It describes how I/O modules bridge the gap between peripherals and the processor/memory bus by acting as an interface. I/O modules handle control/timing, buffering data, and error detection to accommodate differences in speed between devices and the CPU. The document outlines various I/O techniques including programmed I/O where the CPU directly controls I/O, and interrupt-driven I/O where devices interrupt the CPU when an operation completes.
This document summarizes input/output (I/O) and discusses I/O problems, I/O modules, external devices, typical I/O data rates, and I/O module functions. It then describes I/O module control and timing, processor communication, device communication, and I/O techniques including programmed I/O, interrupt-driven I/O, and direct memory access (DMA).
This document discusses computer input/output (I/O) architecture. It describes the challenges posed by peripherals that operate at different speeds and formats than the CPU. I/O modules interface between the CPU/memory and peripherals. They handle control, communication, buffering and error handling. Data can be transferred via programmed I/O where the CPU directly controls transfers, interrupt-driven I/O where devices interrupt the CPU, or direct memory access (DMA) where an I/O controller handles transfers without CPU involvement. Overall the document provides an overview of common I/O techniques and module designs used to interface peripherals with the computer system.
For students wk4_computer_function_and_interconnectionlimyamahgoub
This chapter discusses the top-level view of computer function and interconnection. It explains that a program is a sequence of steps and operations that are executed through different control signals. The central processing unit consists of a control unit and arithmetic logic unit. Data and instructions are input and output through input/output components, while temporary storage is provided by main memory. The computer components are interconnected through buses that transfer data, addresses, and control signals between the CPU, memory, and input/output devices.
03 top level view of computer function and interconnectionSher Shah Merkhel
The document summarizes key topics from Chapter 3 of William Stallings' Computer Organization and Architecture textbook, including:
- The components of a computer including the control unit, ALU, main memory, and I/O.
- How programs are executed through an instruction cycle of fetching and executing instructions.
- Mechanisms for flow control including interrupts, program counters, and jumps.
- How the different computer components are interconnected through buses for data, addresses, and control signals.
- Common bus architectures and how arbitration works to allow shared access to buses.
This chapter discusses input/output (I/O) in computer systems. It covers the challenges posed by different peripheral devices having varying data amounts, speeds, and formats. I/O modules are used to interface between the CPU/memory and peripherals. The chapter describes various I/O module functions and the steps involved in I/O operations. It then discusses three main techniques for I/O - programmed I/O, interrupt-driven I/O, and direct memory access (DMA). Specific I/O components like the 8259A interrupt controller and 8237A DMA controller are also covered. The chapter concludes by examining external device types and I/O communication standards like FireWire and InfiniBand
This document provides information about assembling a computer system, including its basic components and classification of computers. It discusses the hardware components of a typical computer such as the motherboard, CPU, RAM, power supply, storage devices, and input/output components. It also covers computer software, data, and communication components. The document explains how to assemble some of the core hardware components like installing the motherboard, CPU, RAM, and power supply. It concludes by classifying computers into categories like mainframes, supercomputers, minicomputers, and personal computers based on their size, power and other characteristics.
This document provides an overview of input/output organization. It discusses peripheral devices, input and output interfaces, asynchronous data transfer, modes of transfer, interrupts, direct memory access, I/O processors, and serial communication. It describes common input devices like keyboards and optical scanners and output devices like printers and displays. It also covers I/O interfaces, buses, isolated versus memory mapped I/O, and programmable I/O interfaces.
Topic 5 Digital Technique basic computer structureBai Haqi
This document provides an overview of basic computer structure and components. It discusses:
1. The main components of a computer including the CPU, memory, interface, and input/output.
2. Types of memory including ROM, RAM, static RAM, and dynamic RAM.
3. The operation of the bus system which connects the central components.
4. Single and multi-address instruction words.
5. Applications of computers in aircraft systems such as the flight management computer.
This document summarizes input/output (I/O) and discusses I/O problems, I/O modules, external devices, typical I/O data rates, and I/O module functions. It then describes I/O module control and timing, processor communication, device communication, and I/O techniques including programmed I/O, interrupt-driven I/O, and direct memory access (DMA).
This document discusses computer input/output (I/O) architecture. It describes the challenges posed by peripherals that operate at different speeds and formats than the CPU. I/O modules interface between the CPU/memory and peripherals. They handle control, communication, buffering and error handling. Data can be transferred via programmed I/O where the CPU directly controls transfers, interrupt-driven I/O where devices interrupt the CPU, or direct memory access (DMA) where an I/O controller handles transfers without CPU involvement. Overall the document provides an overview of common I/O techniques and module designs used to interface peripherals with the computer system.
For students wk4_computer_function_and_interconnectionlimyamahgoub
This chapter discusses the top-level view of computer function and interconnection. It explains that a program is a sequence of steps and operations that are executed through different control signals. The central processing unit consists of a control unit and arithmetic logic unit. Data and instructions are input and output through input/output components, while temporary storage is provided by main memory. The computer components are interconnected through buses that transfer data, addresses, and control signals between the CPU, memory, and input/output devices.
03 top level view of computer function and interconnectionSher Shah Merkhel
The document summarizes key topics from Chapter 3 of William Stallings' Computer Organization and Architecture textbook, including:
- The components of a computer including the control unit, ALU, main memory, and I/O.
- How programs are executed through an instruction cycle of fetching and executing instructions.
- Mechanisms for flow control including interrupts, program counters, and jumps.
- How the different computer components are interconnected through buses for data, addresses, and control signals.
- Common bus architectures and how arbitration works to allow shared access to buses.
This chapter discusses input/output (I/O) in computer systems. It covers the challenges posed by different peripheral devices having varying data amounts, speeds, and formats. I/O modules are used to interface between the CPU/memory and peripherals. The chapter describes various I/O module functions and the steps involved in I/O operations. It then discusses three main techniques for I/O - programmed I/O, interrupt-driven I/O, and direct memory access (DMA). Specific I/O components like the 8259A interrupt controller and 8237A DMA controller are also covered. The chapter concludes by examining external device types and I/O communication standards like FireWire and InfiniBand
This document provides information about assembling a computer system, including its basic components and classification of computers. It discusses the hardware components of a typical computer such as the motherboard, CPU, RAM, power supply, storage devices, and input/output components. It also covers computer software, data, and communication components. The document explains how to assemble some of the core hardware components like installing the motherboard, CPU, RAM, and power supply. It concludes by classifying computers into categories like mainframes, supercomputers, minicomputers, and personal computers based on their size, power and other characteristics.
This document provides an overview of input/output organization. It discusses peripheral devices, input and output interfaces, asynchronous data transfer, modes of transfer, interrupts, direct memory access, I/O processors, and serial communication. It describes common input devices like keyboards and optical scanners and output devices like printers and displays. It also covers I/O interfaces, buses, isolated versus memory mapped I/O, and programmable I/O interfaces.
Topic 5 Digital Technique basic computer structureBai Haqi
This document provides an overview of basic computer structure and components. It discusses:
1. The main components of a computer including the CPU, memory, interface, and input/output.
2. Types of memory including ROM, RAM, static RAM, and dynamic RAM.
3. The operation of the bus system which connects the central components.
4. Single and multi-address instruction words.
5. Applications of computers in aircraft systems such as the flight management computer.
This document discusses different input/output techniques for computer systems. It describes three main I/O techniques: programmed I/O, interrupt-driven I/O, and direct memory access. Programmed I/O involves the CPU waiting for I/O operations to complete, interrupt-driven I/O uses interrupts to notify the CPU when an operation is done, and DMA allows data transfers without CPU involvement. The document also outlines functions of I/O modules, which connect I/O devices to system buses, and different addressing and mapping schemes for I/O devices.
The document discusses input/output (I/O) organization in computers. It describes how the I/O subsystem provides communication between external devices and the central processing system. Common peripheral devices include monitors, keyboards, printers, and magnetic tapes. The document outlines different I/O techniques including programmed I/O, interrupt-driven I/O, and direct memory access. It also discusses I/O interfaces, addressing schemes, and how interrupts work to signal device completion.
The document provides an overview of computer organization and architecture. It discusses that computer architecture focuses on the logical structure and behavior of a computer system, while computer organization deals with the physical implementation and operational attributes. The document also outlines the evolution of computers from early vacuum tube-based systems to modern multicore processors, noting increased processing speed, smaller component sizes, and larger memory capacities over time. It describes the classic Von Neumann architecture with separate memory and processing units, and how this basic structure is still prevalent in modern systems.
This document provides information about the course AIT 204 - Computer Organization and Architecture (COA). The course is worth 3 credits and is taught by Dr. Y R Ghodasara and Prof. K.C. Kamani at the College of Agricultural Information Technology at Anand Agricultural University in Anand, India. The document discusses input/output systems and the different types of I/O devices. It also covers I/O bus standards and compares north bridge and south bridge buses. Finally, it discusses multi-processor architectures including dual core, quad core and distributed computing models like cluster, grid and cloud computing.
Computer Architecture and Organization.pptxLearnersCoach
Computer architecture is the definition of basic attributes of hardware components and their interconnections, in order to achieve certain specified goals in terms of functions and performance. Computer Architecture refers to those attributes of a system that have a direct impact on the logical execution of a program. Examples:
- the instruction set
- the number of bits used to represent various data types
- I/O mechanisms
- memory addressing techniques
Read More: https://www.learnerscoach.co.ke/introduction-to-computer-architecture/
Computer organization: the design and physical arrangement of various hardware units to work in tandem, in a orderly manner, in order to achieve the goals specified in the architecture.
Read More: https://www.learnerscoach.co.ke/introduction-to-computer-architecture-part2/
This document discusses different techniques for data transfer between the CPU and I/O devices, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It describes the basic functioning of an I/O module, comparing programmed I/O to interrupt-driven I/O. It then provides details on DMA, including how it allows high-speed transfer of data directly between memory and I/O devices without CPU involvement. The document also covers I/O interfaces, asynchronous data transfer methods like handshaking, and serial transmission techniques.
This document provides an overview of input/output (I/O) hardware and software principles. It discusses various I/O devices including disks, clocks, and terminals. It describes I/O hardware components like controllers and memory-mapped I/O. It outlines I/O software layers including interrupt handlers, device drivers, operating system I/O functions, and user-level I/O. It also provides details on specific I/O topics such as disk formatting, error handling, scheduling algorithms, and terminal input/output software.
This document discusses operating system I/O systems. It covers I/O hardware including devices, ports, buses and controllers. It describes how operating systems manage I/O through techniques like interrupts, DMA, blocking/non-blocking I/O, buffering and caching. The kernel I/O subsystem handles requests, scheduling, error handling and protection. Interfaces like STREAMS provide communication between processes and devices. I/O performance is important to overall system performance.
The document provides an overview of computer systems, including definitions, components, and organization. It begins by defining a computer as a device that accepts digital data as input and processes it according to a program. It then discusses computer architecture and organization, explaining that architecture is concerned with how hardware components are connected, while organization focuses on how the system is structured and behaves for users and programmers. The document proceeds to describe the basic components of a computer system, including processors, memory, storage, buses, and input/output devices. It provides examples of computer architectures like the Von Neumann architecture. Overall, the document serves as an introductory overview of key concepts in computer systems.
The document discusses input/output (I/O) problems in computer systems and solutions to those problems. Some key issues addressed are the variety of peripheral devices with different data rates and formats, and the mismatch between peripheral and processor speeds. The document describes I/O modules that interface between the CPU/memory and peripherals. I/O modules handle control, buffering, error detection and allow different I/O techniques like programmed I/O, interrupt-driven I/O and direct memory access (DMA) to transfer data efficiently.
This document provides an overview and introduction to a course on digital design and computer architecture. It discusses the following key topics:
- The Von Neumann architecture and its five main components: CPU, memory, I/O, storage, and interconnection.
- The instruction cycle, including fetching, decoding, and executing instructions, as well as exceptions.
- Instruction architecture, including operation codes, addressing modes, and the hardware and software design required.
- Digital logic gates and how they are used to build circuits and implement computer functions.
This document provides information about a computer systems course, including the lecturer, textbook, and recommended reading. It then summarizes the key topics that will be covered in the course, including computer structure, central processing unit components like registers and instruction cycles, memory hierarchy with caches, input/output techniques like programmed I/O and interrupt-driven I/O, and other concepts.
The document provides a top-level overview of the major components and functioning of a computer system. It discusses how programs are executed through instruction cycles that involve fetching and executing instructions from memory. It describes the role of the control unit in coordinating operations and issuing control signals. The major components of a computer - CPU, memory, and I/O - are interconnected through buses that transfer data, addresses, and control signals. Interrupts allow other devices to interrupt normal instruction processing.
Basics of Computer! BATRA COMPUTER CENTRE IN AMBALAjatin batra
Are you searching for computer training in Ambala?
Now your search ends here.... Batra computer centre is Ambala based computer training centre and provides you the best computer training in Ambala Cantt. We offer you training in courses like training in Basics of Computer, training in Programming languages C & C++, training in Web designing & Development, training in SEO and many more...
This document provides an overview of operating system I/O subsystems. It discusses I/O hardware, including devices, buses, controllers and device drivers. It describes how operating systems handle I/O requests through mechanisms like interrupts, DMA, polling, blocking/non-blocking I/O and asynchronous I/O. The document also outlines kernel data structures for managing I/O and discusses STREAMS, performance optimization techniques, and the life cycle of an I/O request from the application to hardware.
The document discusses high speed input/output (I/O) and recommendations to improve I/O. It covers computer architecture components like the system bus and I/O modules. Common I/O techniques like programmed I/O, interrupt-driven I/O, and direct memory access are described. The document recommends using advanced I/O tools like FPGAs, IEEE 1394, and cryptographic accelerators to enable high speed I/O. It also suggests a new I/O-centric operating system architecture that removes memory and CPU from the data path to improve data flow between peripheral devices. The focus should be on designing operating systems that are more friendly to high speed I/O.
This document discusses computer hardware and the flow of information in a computer system. It describes the basic components of a computer including the central processing unit, memory, input/output devices, and storage. It explains how data moves through the computer architecture via the bus system. The typical Von Neumann architecture is illustrated with five main functional units: the central processing unit, arithmetic logic unit, control unit, memory, and input/output units. The document also covers computer memory organization, computer buses including the system bus and expansion buses, and common external bus types like ISA, PCI, AGP, USB, and IDE.
Introduction to computer applications funnyvideo55
The document discusses the components and processes of a basic computer system. It describes the information processing cycle of input, processing, output, and storage. The major components of a system unit are the central processing unit, memory chips, motherboard, buses, ports, and adapter cards. The document explains the functions of these components and how they work together to process information.
The document provides an overview of microprocessors and microcontrollers. It discusses the history of microprocessors from early 4-bit processors to modern 64-bit processors. A microprocessor contains a central processing unit while a microcontroller contains additional components like memory and input/output interfaces integrated into a single chip. Microcontrollers require less external hardware than microprocessors. The document describes the basic architecture of microprocessors and microcontrollers including components like registers, buses, and memory. It compares the von Neumann and Harvard architectures. Interrupts and memory-mapped I/O are also discussed.
This document discusses schema refinement through normalization. Schema refinement aims to eliminate data redundancy and anomalies like insertion, update, and deletion anomalies. It introduces normalization as a technique to decompose tables and refine the schema. Redundancy can lead to problems like redundant storage, update anomalies if one copy of data is changed without updating others, and insertion and deletion anomalies where adding or removing data could impact unrelated information. The document uses an example of a student details table to illustrate these problems and how decomposition can address redundancy.
joins in dbms its describes about how joins are important and necessity in d...AshokRachapalli1
Joins in DBMS allow combining data from multiple tables. Inner joins return rows where the join condition is satisfied, while outer joins also return rows with no matches and fill unmatched columns with NULL. Natural joins automatically join on common columns with matching names and domains, while theta joins use any comparison operator in the join condition. Equi joins specifically use equality comparisons.
This document discusses different input/output techniques for computer systems. It describes three main I/O techniques: programmed I/O, interrupt-driven I/O, and direct memory access. Programmed I/O involves the CPU waiting for I/O operations to complete, interrupt-driven I/O uses interrupts to notify the CPU when an operation is done, and DMA allows data transfers without CPU involvement. The document also outlines functions of I/O modules, which connect I/O devices to system buses, and different addressing and mapping schemes for I/O devices.
The document discusses input/output (I/O) organization in computers. It describes how the I/O subsystem provides communication between external devices and the central processing system. Common peripheral devices include monitors, keyboards, printers, and magnetic tapes. The document outlines different I/O techniques including programmed I/O, interrupt-driven I/O, and direct memory access. It also discusses I/O interfaces, addressing schemes, and how interrupts work to signal device completion.
The document provides an overview of computer organization and architecture. It discusses that computer architecture focuses on the logical structure and behavior of a computer system, while computer organization deals with the physical implementation and operational attributes. The document also outlines the evolution of computers from early vacuum tube-based systems to modern multicore processors, noting increased processing speed, smaller component sizes, and larger memory capacities over time. It describes the classic Von Neumann architecture with separate memory and processing units, and how this basic structure is still prevalent in modern systems.
This document provides information about the course AIT 204 - Computer Organization and Architecture (COA). The course is worth 3 credits and is taught by Dr. Y R Ghodasara and Prof. K.C. Kamani at the College of Agricultural Information Technology at Anand Agricultural University in Anand, India. The document discusses input/output systems and the different types of I/O devices. It also covers I/O bus standards and compares north bridge and south bridge buses. Finally, it discusses multi-processor architectures including dual core, quad core and distributed computing models like cluster, grid and cloud computing.
Computer Architecture and Organization.pptxLearnersCoach
Computer architecture is the definition of basic attributes of hardware components and their interconnections, in order to achieve certain specified goals in terms of functions and performance. Computer Architecture refers to those attributes of a system that have a direct impact on the logical execution of a program. Examples:
- the instruction set
- the number of bits used to represent various data types
- I/O mechanisms
- memory addressing techniques
Read More: https://www.learnerscoach.co.ke/introduction-to-computer-architecture/
Computer organization: the design and physical arrangement of various hardware units to work in tandem, in a orderly manner, in order to achieve the goals specified in the architecture.
Read More: https://www.learnerscoach.co.ke/introduction-to-computer-architecture-part2/
This document discusses different techniques for data transfer between the CPU and I/O devices, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It describes the basic functioning of an I/O module, comparing programmed I/O to interrupt-driven I/O. It then provides details on DMA, including how it allows high-speed transfer of data directly between memory and I/O devices without CPU involvement. The document also covers I/O interfaces, asynchronous data transfer methods like handshaking, and serial transmission techniques.
This document provides an overview of input/output (I/O) hardware and software principles. It discusses various I/O devices including disks, clocks, and terminals. It describes I/O hardware components like controllers and memory-mapped I/O. It outlines I/O software layers including interrupt handlers, device drivers, operating system I/O functions, and user-level I/O. It also provides details on specific I/O topics such as disk formatting, error handling, scheduling algorithms, and terminal input/output software.
This document discusses operating system I/O systems. It covers I/O hardware including devices, ports, buses and controllers. It describes how operating systems manage I/O through techniques like interrupts, DMA, blocking/non-blocking I/O, buffering and caching. The kernel I/O subsystem handles requests, scheduling, error handling and protection. Interfaces like STREAMS provide communication between processes and devices. I/O performance is important to overall system performance.
The document provides an overview of computer systems, including definitions, components, and organization. It begins by defining a computer as a device that accepts digital data as input and processes it according to a program. It then discusses computer architecture and organization, explaining that architecture is concerned with how hardware components are connected, while organization focuses on how the system is structured and behaves for users and programmers. The document proceeds to describe the basic components of a computer system, including processors, memory, storage, buses, and input/output devices. It provides examples of computer architectures like the Von Neumann architecture. Overall, the document serves as an introductory overview of key concepts in computer systems.
The document discusses input/output (I/O) problems in computer systems and solutions to those problems. Some key issues addressed are the variety of peripheral devices with different data rates and formats, and the mismatch between peripheral and processor speeds. The document describes I/O modules that interface between the CPU/memory and peripherals. I/O modules handle control, buffering, error detection and allow different I/O techniques like programmed I/O, interrupt-driven I/O and direct memory access (DMA) to transfer data efficiently.
This document provides an overview and introduction to a course on digital design and computer architecture. It discusses the following key topics:
- The Von Neumann architecture and its five main components: CPU, memory, I/O, storage, and interconnection.
- The instruction cycle, including fetching, decoding, and executing instructions, as well as exceptions.
- Instruction architecture, including operation codes, addressing modes, and the hardware and software design required.
- Digital logic gates and how they are used to build circuits and implement computer functions.
This document provides information about a computer systems course, including the lecturer, textbook, and recommended reading. It then summarizes the key topics that will be covered in the course, including computer structure, central processing unit components like registers and instruction cycles, memory hierarchy with caches, input/output techniques like programmed I/O and interrupt-driven I/O, and other concepts.
The document provides a top-level overview of the major components and functioning of a computer system. It discusses how programs are executed through instruction cycles that involve fetching and executing instructions from memory. It describes the role of the control unit in coordinating operations and issuing control signals. The major components of a computer - CPU, memory, and I/O - are interconnected through buses that transfer data, addresses, and control signals. Interrupts allow other devices to interrupt normal instruction processing.
Basics of Computer! BATRA COMPUTER CENTRE IN AMBALAjatin batra
Are you searching for computer training in Ambala?
Now your search ends here.... Batra computer centre is Ambala based computer training centre and provides you the best computer training in Ambala Cantt. We offer you training in courses like training in Basics of Computer, training in Programming languages C & C++, training in Web designing & Development, training in SEO and many more...
This document provides an overview of operating system I/O subsystems. It discusses I/O hardware, including devices, buses, controllers and device drivers. It describes how operating systems handle I/O requests through mechanisms like interrupts, DMA, polling, blocking/non-blocking I/O and asynchronous I/O. The document also outlines kernel data structures for managing I/O and discusses STREAMS, performance optimization techniques, and the life cycle of an I/O request from the application to hardware.
The document discusses high speed input/output (I/O) and recommendations to improve I/O. It covers computer architecture components like the system bus and I/O modules. Common I/O techniques like programmed I/O, interrupt-driven I/O, and direct memory access are described. The document recommends using advanced I/O tools like FPGAs, IEEE 1394, and cryptographic accelerators to enable high speed I/O. It also suggests a new I/O-centric operating system architecture that removes memory and CPU from the data path to improve data flow between peripheral devices. The focus should be on designing operating systems that are more friendly to high speed I/O.
This document discusses computer hardware and the flow of information in a computer system. It describes the basic components of a computer including the central processing unit, memory, input/output devices, and storage. It explains how data moves through the computer architecture via the bus system. The typical Von Neumann architecture is illustrated with five main functional units: the central processing unit, arithmetic logic unit, control unit, memory, and input/output units. The document also covers computer memory organization, computer buses including the system bus and expansion buses, and common external bus types like ISA, PCI, AGP, USB, and IDE.
Introduction to computer applications funnyvideo55
The document discusses the components and processes of a basic computer system. It describes the information processing cycle of input, processing, output, and storage. The major components of a system unit are the central processing unit, memory chips, motherboard, buses, ports, and adapter cards. The document explains the functions of these components and how they work together to process information.
The document provides an overview of microprocessors and microcontrollers. It discusses the history of microprocessors from early 4-bit processors to modern 64-bit processors. A microprocessor contains a central processing unit while a microcontroller contains additional components like memory and input/output interfaces integrated into a single chip. Microcontrollers require less external hardware than microprocessors. The document describes the basic architecture of microprocessors and microcontrollers including components like registers, buses, and memory. It compares the von Neumann and Harvard architectures. Interrupts and memory-mapped I/O are also discussed.
This document discusses schema refinement through normalization. Schema refinement aims to eliminate data redundancy and anomalies like insertion, update, and deletion anomalies. It introduces normalization as a technique to decompose tables and refine the schema. Redundancy can lead to problems like redundant storage, update anomalies if one copy of data is changed without updating others, and insertion and deletion anomalies where adding or removing data could impact unrelated information. The document uses an example of a student details table to illustrate these problems and how decomposition can address redundancy.
joins in dbms its describes about how joins are important and necessity in d...AshokRachapalli1
Joins in DBMS allow combining data from multiple tables. Inner joins return rows where the join condition is satisfied, while outer joins also return rows with no matches and fill unmatched columns with NULL. Natural joins automatically join on common columns with matching names and domains, while theta joins use any comparison operator in the join condition. Equi joins specifically use equality comparisons.
Database languages are used to define, manipulate, and control access to data in a database management system. There are four main types of database languages: Data Definition Language (DDL) defines the database structure; Data Manipulation Language (DML) reads, inserts, updates, and deletes data; Data Control Language (DCL) controls user access privileges; and Transaction Control Language (TCL) manages transactions and rolling back or committing changes to the database.
The document discusses register transfer languages (RTL) which are used to specify the operations and timing of digital circuits. It covers micro-operations which define data transfers, RTL which specifies when micro-operations occur, and how RTL specifications can be realized through hardware implementation or simulated using VHDL. Examples are provided of RTL specifications for simple counters and controllers to illustrate these concepts.
The document discusses different levels of computer memory and cache memory. It describes four levels of memory:
1) Register - Stores data accepted by the CPU.
2) Cache memory - Faster memory that temporarily stores frequently accessed data from main memory.
3) Main memory - The memory the computer currently works on but data is lost when powered off.
4) Secondary memory - External memory that stores data permanently but is slower than main memory.
It then discusses cache memory in more detail, describing it as very high-speed memory that stores copies of frequently used data from main memory to reduce average access time. It explains the concepts of cache hits, misses, and hit ratio. Finally, it
The document discusses different types of addressing modes used in computer instructions, including implied, immediate, direct, indirect, register direct, register indirect, relative, indexed, base register, auto-increment, and auto-decrement addressing modes. It provides examples and explanations of each addressing mode type.
The document discusses input/output (I/O) organization in a computer system. It describes I/O interfaces that allow communication between internal storage and external devices. Data transfer can occur via programmed I/O, interrupt-initiated I/O, or direct memory access (DMA). DMA allows direct transfer between I/O devices and memory without CPU involvement by using a DMA controller. An I/O processor (IOP) is also described, which is a dedicated processor that handles I/O operations and transfers data between devices and memory.
Virtual memory allows programs to access memory addresses that do not physically exist, expanding the available address space. It works by dividing memory into pages that are stored on disk until needed, then copied into RAM. When a program accesses a non-present page, a page fault occurs and the operating system handles copying the correct page into memory transparently to the program. This allows more programs to run than would otherwise fit in physical memory.
This document discusses techniques for reducing cache misses and improving memory performance. It introduces the concepts of compulsory, capacity and conflict misses. Methods covered for reducing misses include increasing block size, associativity, using victim caches, pseudo-associativity, hardware/software prefetching, and compiler optimizations like merging arrays, loop interchange, fusion and blocking. Both hardware and software prefetching are described as well as the tradeoffs between binding and non-binding prefetching.
Disk-based storage uses a memory hierarchy to balance performance and cost. Large, slower disks are used for persistent storage due to their low cost per byte, while smaller, faster memory like DRAM is used for temporary storage. A disk contains platters that spin, allowing read/write heads to access sectors organized into tracks on the platters. Disk access time is dominated by seek time to position the heads and rotational latency waiting for the desired sector to spin under the head. Disks present a logical block interface to the operating system, while sectors are mapped to physical locations on disk surfaces.
Digital systems perform elementary operations called micro operations on information stored in registers. There are two main types: arithmetic micro operations that change information, such as addition, subtraction, and shift operations; and logic micro operations that perform binary operations on bit strings, like AND, OR, and XOR. Common components that perform these micro operations include binary adders, adder-subtractors, incrementers, and the Arithmetic Logic Shift Unit.
The document discusses computer instruction formats and addressing modes. It provides details on:
- Instruction codes contain operation codes and addresses to specify operations and memory/register locations.
- There are two addressing modes - direct addressing uses the operand's address while indirect uses a pointer.
- A basic instruction format has 12 bits for the address, 1 bit for the mode, and 3 bits for the operation code.
- An instruction cycle has four phases - fetch, decode, read effective address, and execute the instruction.
There are two main types of computer network architectures: peer-to-peer and client/server. Peer-to-peer networks connect computers of equal status without a central server, making them useful for small networks but less secure. Client/server networks have a central server that manages resources and authorization for client computers, providing better security, performance, and backup but at a higher cost than peer-to-peer.
A computer network can be categorized based on its size as PAN, LAN, MAN, or WAN. A PAN covers an area of about 30 feet and connects personal devices like laptops and phones. A LAN connects computers within a building using cables, providing faster data transfer and higher security than larger networks. A MAN interconnects multiple LANs within a city using telephone lines to connect organizations like businesses, schools, and governments. A WAN spans large geographic areas like countries and states, with the internet being the largest example, connecting networks globally.
Data encoding converts data into a signal form for transmission. It represents digital data with digital or analog signals. Common encoding methods include unipolar, bipolar, and polar encoding. Unipolar encoding uses a single voltage level to represent 1s and 0s, while bipolar uses two voltage levels. Specific techniques include NRZ, RZ, and biphase encoding. NRZ encodes without returning to zero between bits, while RZ returns to zero mid-bit. Biphase encodings like Manchester and differential Manchester use signal transitions to represent data and synchronize clocks. Block coding maps groups of bits to code words, like 4B/5B encoding which maps 4 data bits to 5-bit code words.
Flow control is a data link layer mechanism that regulates the amount of data sent by the sender to ensure the receiver can process it. It works by having the sender wait for acknowledgment from the receiver before sending more data. Common flow control methods include stop-and-wait, which only allows one packet to be sent at a time, and sliding window protocols, which allow multiple packets to be sent before waiting for acknowledgment. Flow control prevents buffer overflows and frame losses at the receiver.
This document summarizes a lecture on register transfer language and microoperations. It introduces register transfer language as a way to describe the transfer of data between registers using microoperations. Common microoperations include register transfer, arithmetic operations, logic operations, and shift operations. Specific circuit implementations for operations like addition, subtraction, and incrementing are discussed. Memory transfer microoperations for reading from and writing to memory are also covered.
This document provides an introduction and overview of the Python programming language. It outlines the key topics that will be covered in a Python tutorial, including basic data types, variables, control structures, functions, classes, exceptions, modules and packages, and the standard library. The document consists of slides from a 2002 presentation on Python given by Guido van Rossum, the creator of Python. It encourages attendees to follow along with the tutorial using the interactive Python shell.
This document provides an overview of the OSI reference model, which is an internationally standardized architecture for how network communication should work. It describes the seven layers of the OSI model from the physical layer up to the application layer. Each layer provides services to the layer above it and receives services from the layer below. The layers relate to either communication technologies (layers 1-4) or user applications (layers 5-7). The document also discusses how the OSI model differs from Internet protocols and covers concepts like connection types, reliability, and the relationship between services and protocols.
Packet switching is a technique used in computer networks where messages are divided into packets that contain header information with the destination. Each packet is routed independently through the network based on its header. There are two main approaches for packet switching: datagram packet switching treats each packet independently and routes them without maintaining connection state, while virtual circuit switching establishes a pre-planned route via a call setup before sending packets along a fixed path for the connection's duration.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.
Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
Use PyCharm for remote debugging of WSL on a Windo cf5c162d672e4e58b4dde5d797...shadow0702a
This document serves as a comprehensive step-by-step guide on how to effectively use PyCharm for remote debugging of the Windows Subsystem for Linux (WSL) on a local Windows machine. It meticulously outlines several critical steps in the process, starting with the crucial task of enabling permissions, followed by the installation and configuration of WSL.
The guide then proceeds to explain how to set up the SSH service within the WSL environment, an integral part of the process. Alongside this, it also provides detailed instructions on how to modify the inbound rules of the Windows firewall to facilitate the process, ensuring that there are no connectivity issues that could potentially hinder the debugging process.
The document further emphasizes on the importance of checking the connection between the Windows and WSL environments, providing instructions on how to ensure that the connection is optimal and ready for remote debugging.
It also offers an in-depth guide on how to configure the WSL interpreter and files within the PyCharm environment. This is essential for ensuring that the debugging process is set up correctly and that the program can be run effectively within the WSL terminal.
Additionally, the document provides guidance on how to set up breakpoints for debugging, a fundamental aspect of the debugging process which allows the developer to stop the execution of their code at certain points and inspect their program at those stages.
Finally, the document concludes by providing a link to a reference blog. This blog offers additional information and guidance on configuring the remote Python interpreter in PyCharm, providing the reader with a well-rounded understanding of the process.
The CBC machine is a common diagnostic tool used by doctors to measure a patient's red blood cell count, white blood cell count and platelet count. The machine uses a small sample of the patient's blood, which is then placed into special tubes and analyzed. The results of the analysis are then displayed on a screen for the doctor to review. The CBC machine is an important tool for diagnosing various conditions, such as anemia, infection and leukemia. It can also help to monitor a patient's response to treatment.
2. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
General Description of I/O
Wide variety of peripherals
• Delivering different amounts of data
• At different speeds
• In different formats (bit depth, etc.)
3. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Closing the Gap
• Need I/O modules to act as bridge
between processor/memory bus and the
peripherals
Processor Bus
I/O
Module
External
sensors
and
controls
Device
Interface
Device
Interface
Device
Interface
4. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
External Devices
• External devices are needed as a means of
communication to the outside world (both input and
output – I/O)
• Types
– Human readable – communication with user
(monitor, printer, keyboard, mouse)
– Machine readable – communication with
equipment (hard drive, CDROM, sensors, and
actuators)
– Communication – communication with remote
computers/devices (Can be any of the first two or
a network interface card or modem)
6. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Device Interface Components
• The control logic is the I/O module's interface to the device
• The data channel passes the collected data from or the data
to be output to the device. On the opposite end is the I/O
module, but eventually it is the processor.
• The transducer acts as a converter between the digital data
of the I/O module and the signals of the outside world.
– Keyboard converts motion of key into data representing
key pressed or released
– Temperature sensor converts amount of heat into a digital
value
– Disk drive converts data to electronic signals for controlling
the read/write head
7. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
I/O Module Functions
• Control & Timing
• Processor Communication
• Device Communication
• Data Buffering
• Error Detection
8. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
I/O Module: Control and Timing
• Required because of multiple devices all
communicating on the same channel
• Example
– CPU checks I/O module device status
– I/O module returns status
– If ready, CPU requests data transfer
– I/O module gets data from device
– I/O module transfers data to CPU
– Variations for output, DMA, etc.
9. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
I/O Module: Processor
Communication
• Commands from processor – Examples: READ
SECTOR, WRITE SECTOR, SEEK track
number, and SCAN record ID.
• Data – passed back and forth over the data bus
• Status reporting – Request from the processor
for the I/O Module's status. May be as simple as
BUSY and READY
• Address recognition – I/O device is setup as a
block of one or more addresses unique to itself
10. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Other I/O Module Functions
• Device Communication – specific to each device
• Data Buffering – Due to the differences in speed
(device is usually orders of magnitude slower) the
I/O module needs to buffer data to keep from tying
up the CPU's bus with slow reads or writes
• Error Detection – simply distributing the need for
watching for errors to the module. They may
include:
– Malfunctions by device (paper jam)
– Data errors (parity checking at the device level)
– Internal errors to the I/O module such as buffer overruns
12. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
I/O Module Level of Operation
• How much control will the CPU be required to
handle?
• How much will the CPU be allowed to handle?
• What will the interface look like, e.g., Unix treats
everything like a file
• Support multiple or single device
• Will additional control be needed for multiple
devices on a single port (e.g., serial port versus
USB)
13. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Input/Output Techniques
• Programmed I/O – poll and response
• Interrupt driven – module calls for CPU
when needed
• Direct Memory Access (DMA) – module
has direct access to specified block of
memory
14. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Addressing I/O Devices
“Memory-Mapped I/O”
• Data transfer is the same as a memory
access (chip selects)
• 80x86 example, any assembly language
command accessing memory use memory
read (^MRDC) and write (^MWTC) lines
• Can use ALL memory instructions which is
much greater than I/O instructions
15. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Addressing I/O Devices
“Isolated I/O”
• Data transfer uses the same address lines
but different read/write control lines
• 8086 example, in and out commands use
same bus with different read (^IORC) and
write (^IOWC) lines
• Limited number of instructions to choose
from
16. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Programmed I/O –
CPU has direct control over I/O
• Processor requests operation with commands sent
to I/O module
– Control – telling a peripheral what to do
– Test – used to check condition of I/O module or device
– Read – obtains data from peripheral so processor can read
it from the data bus
– Write – sends data using the data bus to the peripheral
• I/O module performs operation
• When completed, I/O module updates its status
registers
• Sensing status – involves polling the I/O module's
status registers
17. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Programmed I/O (continued)
• I/O module does not inform CPU directly
• CPU may wait or do something and come back
later
• Wastes CPU time because typically processor is
much faster than I/O
– CPU acts as a bridge for moving data between I/O
module and main memory, i.e., every piece of data
goes through CPU
– CPU waits for I/O module to complete operation
18. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Programmed I/O Example
Motorola 68HC11 Serial Communications
• Memory-mapped control registers
– SCCR1(0x102C)
– SCCR2 (0x102D)
• Memory-mapped status register SCSR (0x102E)
TIE TCIE RIE ILIE TE RE RWU
TDRE TC RDRF IDLE OR NF FE 0
R8 T8 0 M WAKE 0 0 0
19. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Programmed I/O Example (continued)
Control:
• Transmit enable (TE) – Set to one in order to
enable serial output
• Receive enable (RE) – Set to one in order to
enable serial input
Status:
• Transmit data register empty (TDRE) – Set to one
to indicate data can be placed in buffer
• Transmit complete (TC) – zero means character is
being sent; one means transmitter idle
• Receive data register full – Set to a one when
received data needs to be read
20. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Programmed I/O Example (continued)
“Transmitting a character”
SCCR2 |=0x08; // Set TE to 1
while !end_of_stream
{
while !(SCSR & 0x80); // Wait until TDRE=1
SCDR = next_byte_to_send;
}
21. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Programmed I/O Example (continued)
“Receiving a character”
SCCR2 |=0x04; // Set RE to 1
while !(SCSR & 0x20); // Wait until RDRF=1
received_byte = SCDR;
22. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Interrupt Driven I/O
• Overcomes CPU waiting
• Requires setup code and interrupt service
routine
• No repeated CPU checking of device
• I/O module interrupts when ready
• Still requires CPU to be go between for
moving data between I/O module and
main memory
23. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Analogy: Exception Handling
• Before exception handling, functions would indicate
an error with a return value
– Calling code would check return code and handle error
accordingly
– Code littered with extra if-statements
– Ex: if(myFunction() == -1) printf("Error occurred.");
• Exception handling creates some sort of error flag.
– Third party code watches for flag, and if it gets set,
executes error handler.
– Allows for single error handler and cleaner code
• Configuration consists of trigger, listener, and handler
24. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Basic Interrupt I/O Operation
• CPU initializes the process
• I/O module gets data from peripheral while
CPU does other work
• I/O module interrupts CPU
• CPU requests data
I/O module transfers data
26. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
CPU Viewpoint (continued)
• Issue read command
Do other work
• Check for interrupt at end of each
instruction cycle (NO CODE IS INVOLVED
IN THIS)
• I/O module issues interrupt request
27. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
CPU Viewpoint (continued)
I/O module issues interrupt request forcing processor to:
• Save context on stack
– Registers (this may have to be done by ISR)
– Pointers including PC/IP, but not SP
– Flags (Program Status Word)
• Send acknowledgement so I/O module can release request
• Process interrupt by loading address of ISR into PC/IP
• Interrupt must save results of ISR because more than likely,
returning from the interrupt will erase all indications that it
happened at all
• Retrieve context including PC/IP
28. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Interrupt I/O Example
(continued from programmed I/O)
Control:
• Transmit interrupt enable (TIE) – set to one
enables interrupt when TDRE is set to one
• Transmit complete interrupt enable (TCIE) –
set to one enables interrupt when TC is set to
one
• Receive interrupt enable (RIE) – set to one
enables interrupt when RDRF is set to one or
when error occurs
29. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Interrupt I/O Example (continued)
Status:
• Overrun error (OR) – set to one when
character received but there was no room in
SCDR
• Noise flag (NF) – set to one when noise is
detected on receive input
• Framing error (FE) – set to one when
received data had error with framing bits
30. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Interrupt I/O Example (continued)
“Transmitting a character”
SCCR2 |=0x88; // Set TIE and TE to 1
setISR(&ser_tx_ISR());
// At this point, processor can do something else
void INTERRUPT ser_tx_ISR()
{
SCDR = next_byte_to_send;
}
31. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Interrupt I/O Example (continued)
“Receiving a character”
SCCR2 |=0x24; // Set RIE and RE to 1
setISR(&ser_rx_ISR());
// At this point, processor can do something else
void INTERRUPT ser_rx_ISR()
{
if ((SCSR & 0x2E) == 0x20)
received_byte = SCDR;
else if ((SCSR & 0xE) != 0) process_error();
}
32. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Design Issues
• Resolution of multiple interrupts – How do
you identify the module issuing the
interrupt?
• Priority – How do you deal with multiple
interrupts at the same time or interrupting
in the middle of an interrupt?
33. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Identifying Interrupting Module
• Different interrupt line for each module
• Limits number of devices
• Even with this method, there are often
multiple interrupts still on a single interrupt
lined
• Priority is set by hardware
34. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Software poll
• Single interrupt line – when interrupt
occurs, CPU then goes out to check who
needs attention
• Slow
• Priority is set by order in which CPU
polls devices
35. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Daisy Chain or Hardware poll
• Interrupt Acknowledge sent down a chain
• Module responsible places unique vector
on bus
• CPU uses vector to identify handler
routine
• Priority is set by order in which
interrupt acknowledge gets to I/O
modules, i.e., order of devices on the
chain
36. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Bus Arbitration
• Allow multiple modules to control bus (See
“Method of Arbitration,” p. 75)
• I/O Module must claim the bus before it can raise
interrupt
• Can do this with:
– Bus controller/arbiter
– Distribute control to devices
• Must be one master, either processor or other
device
• Device that "wins" places vector on bus uniquely
identifying interrupt
• Priority is set by priority in arbitration, i.e.,
whoever is currently in control of the bus
38. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
82C59A (continued)
• 80386 has one interrupt line
• 8259A has 8 interrupt lines
39. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
82C59A Sequence of Events
• 82C59A accepts interrupts
• 82C59A determines priority
– Fully nested IR0 (highest) through IR7 (lowest)
– Rotating – after interrupt is serviced, it goes to bottom
of priority list
– Special mask – allows individual interrupts to be
disabled
• 82C59A signals 8086 (raises INTR line)
• CPU Acknowledges with INTA line
• 82C59A puts correct vector on data bus
• CPU processes interrupt
40. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Direct Memory Access (DMA)
• Impetus behind DMA – Interrupt driven
and programmed I/O require active CPU
intervention (All data must pass through
CPU)
• Transfer rate is limited by processor's
ability to service the device
• CPU is tied up managing I/O transfer
41. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
DMA (continued)
• Additional Module (hardware) on bus
• DMA controller takes over bus from CPU
for I/O
– Waiting for a time when the processor doesn't
need bus
– Cycle stealing – seizing bus from CPU (more
common)
42. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
DMA Operation
• CPU tells DMA controller:
– whether it will be a read or write operation
– the address of device to transfer data from
– the starting address of memory block for the
data transfer
– the amount of data to be transferred
• DMA performs transfer while CPU does
other processes
• DMA sends interrupt when completed
44. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Cycle Stealing
• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt – CPU does not switch
context
• CPU suspended just before it accesses
bus – i.e. before an operand or data fetch
or a data write
• Slows down CPU but not as much as CPU
doing transfer
45. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
In-class discussion
• What effect does caching memory have on
DMA?
• Hint: How much are the system buses
available?
46. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
DMA Configurations
Single Bus, Detached DMA controller
– Each transfer uses bus twice – I/O to DMA
then DMA to memory
– CPU is suspended twice
47. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
DMA Configurations (continued)
Single Bus, DMA controller integrated into I/O module
– Controller may support one or more devices
– Each transfer uses bus once – DMA to memory
– CPU is suspended once
48. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
DMA Configurations (continued)
Separate I/O Bus
– Bus supports all DMA enabled devices with single
DMA controller
– Each transfer uses bus once – DMA to memory
– CPU is suspended once
49. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
Evolutions of I/O Methods
Growth of more sophisticated I/O devices
1.Processor directly controls device
2.Processor uses Programmed I/O
3.Processor uses Interrupts
4.Processor uses DMA
5.Some processing moved to processors in I/O
module that access programs in memory and
execute them on their own without CPU
intervention (I/O Module referred to as an I/O
Channel)
6.Distributed processing where I/O module is a
computer in its own right(I/O Module referred to
as an I/O Processor)
50. Input/Output– Page ‹#› of 51
CSCI 4717 – Computer Architecture
I/O Channels (continued)
• I/O Channel is extension of DMA concept
• CPU instructs the I/O channel to execute a
program in memory
• Following these instructions, the I/O channel
does the transfer of data itself
• Architecture
– Selector – one device transferring block of data at a
time
– Multiplexor – TDM