ok

1. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter 5
Register Transfer Languages

2. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter Outline
• Micro-operations
• RTL
• RTL specifications
• Realizing RTL specifications
• VHDL

3. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Micro-operations
• Specify data transfer
• Do not specify conditions under which
transfers occur
• Do not specify hardware implementation

4. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Example: X  Y
X

5. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Register Transfer Language
• Specify micro-operations and when they
occur
• Format: conditions: micro-operations

6. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Example: α: X  Y
X

7. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Simultaneous Data Transfers
α: X  Y, Y  Z
Q D

8. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Invalid Simultaneous Transfers
α: X  Y, X  Z

9. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Loading Constant Values into
Registers
α: X  0
β: X  1

10. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Making Transfers Mutually
Exclusive

11. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Multi-bit Data Transfers
α: X  Y

12. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Bit and Bit-range Transfers

13. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Arithmetic and Logical Micro-
operations

14. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Shift Micro-operations

15. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Specifying Digital
Components: D Flip-Flop

16. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Specifying Digital Components:
JK Flip-Flop

17. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Specifying Digital Components:
Left Shift Register

18. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Specifying Simple Systems

19. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
System Implementation – Data
Paths

20. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
System Implementation – Data
Paths and Control

21. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
System Implementation Using a
Bus and 3-State Buffers

22. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
System Implementation Using
a Bus and a Multiplexer
n o j

23. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter
• Counts up when U = 1
• Count sequence: 000  001  010 
011  100  101  000 …
• V is 3-bit output = count value
• C is 1-bit output = 1 when V = 000

24. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter State Table
1 1 1
1 1 1

25. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter State Diagram

26. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter RTL
Specification

27. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter System
Implementation

28. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter Another
System Implementation

29. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller
• C = 1 when car is at toll booth
• I[1..0] indicates coin input
• Outputs R, G, A:
– Car in toll booth, toll not fully paid: R = 1
– Toll paid: G = 1
– Car left without paying full toll: R = 1, A = 1

30. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller States

31. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller State Table

32. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller State Diagram

33. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller State
Assignments

34. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Converting State Transitions
to RTL Code

35. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Converting State Transitions to
RTL Code

36. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller RTL
Specification (excluding outputs)

37. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Toll Booth Controller RTL
Specification (outputs)

38. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL – VHSIC Hardware
Description Language
• Formal syntax – portable
• Platform independent
• Design for PLDs, ASICs, or custom
chips
• Simulate designs
• Different levels of abstraction

39. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL Design Structure
• Library section
• Entity section
• Architecture section

40. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL Library Section
library IEEE;
use IEEE.std_logic_1164.all;

41. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL Entity Section

42. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL Architecture Section

43. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL – High Level of
Abstraction
• Modulo 6 counter
• Designed as a state machine

44. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter – Library
and Entity Sections

45. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Modulo 6 Counter – One State

46. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Architecture Section – State
Generation

47. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Architecture Section – State
Generation (continued)

48. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Architecture Section – State
Transition

49. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL – Low Level of Abstraction

50. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
VHDL – Advanced
Capabilities
• Components
• Timing
• Simulation

51. Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Summary
• Micro-operations
• RTL
• RTL specifications
• Realizing RTL specifications
• VHDL