The document discusses integrated circuit (IC) design technology. It covers IC technology types including full-custom, semicustom, and programmable logic devices. It also discusses design technology topics such as automation through synthesis, verification through hardware/software co-simulation, and reuse through intellectual property cores. The document provides details on the IC design process and challenges associated with increasing design complexity.
This document discusses design technologies for improving productivity in embedded systems design. It focuses on automation through synthesis, reuse through intellectual property cores, and verification through hardware/software co-simulation. Synthesis is described as automatically converting a system's behavioral description into a structural implementation to optimize design metrics. Logic synthesis, register-transfer synthesis, and behavioral synthesis are discussed as techniques that operate at different levels of abstraction in the design process.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
VLSI and Embedded System DESIGN – provides an overview of VLSI design and embedded systems. It discusses the challenges in VLSI design including power dissipation and interconnect issues. It then defines embedded systems and describes their characteristics like being single-purposed, tightly constrained, and reactive in real-time. Key technologies for embedded systems design are discussed including processor technology, integrated circuit technology, and design technologies which allow a unified view of hardware and software co-design. Optimization of design metrics like cost, performance, power, and flexibility is a major challenge.
This document provides an overview of embedded system design. It discusses the characteristics of embedded systems and examples of embedded devices. It then covers key aspects of embedded system design including optimization of design metrics like cost, size and power. Processor technologies like general purpose, single purpose and application specific processors are described. The document also discusses integrated circuit technologies like full custom, semi-custom ASICs and programmable logic devices.
This document outlines the course contents for a VLSI Design course. The course covers six units: (1) an introduction to VLSI design including Moore's Law and design challenges, (2) VLSI circuit design processes and technologies, (3) analysis of CMOS logic circuits, (4) advanced CMOS logic circuit techniques, (5) memories, and (6) testing and testability. The goal of the course is to provide students with knowledge of very large scale integration circuits, which are essential components in modern electronic devices.
This document discusses digital VLSI design flows. It begins by acknowledging previous work that informed the presentation. It then discusses considerations in developing an electronic system, including components of the system. It describes integrated circuits based on application, fabrication technology, device, and device count. It discusses using standard or application-specific integrated circuits. It outlines a top-down design approach and terminology used in the design flow.
Performance and Flexibility for Mmultiple-Processor SoC DesignYalagoud Patil
Concepts, limitations of traditional ASIC design
Extensible processors as an alternative to RTL
Toward multiple-processor SoCs
Processors and disruptive technology
Conclusions
This document provides an overview of the ASIC back-end design flow, including timing driven placement. It discusses the inputs to the Astro placement and routing tool, including the gate-level netlist, standard cell library, and timing constraints. It describes key aspects of the placement process, including floorplanning, placement rows, and timing driven placement to optimize critical paths. The goal is to meet all timing constraints by balancing timing, area, power, and signal integrity.
This document discusses design technologies for improving productivity in embedded systems design. It focuses on automation through synthesis, reuse through intellectual property cores, and verification through hardware/software co-simulation. Synthesis is described as automatically converting a system's behavioral description into a structural implementation to optimize design metrics. Logic synthesis, register-transfer synthesis, and behavioral synthesis are discussed as techniques that operate at different levels of abstraction in the design process.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
VLSI and Embedded System DESIGN – provides an overview of VLSI design and embedded systems. It discusses the challenges in VLSI design including power dissipation and interconnect issues. It then defines embedded systems and describes their characteristics like being single-purposed, tightly constrained, and reactive in real-time. Key technologies for embedded systems design are discussed including processor technology, integrated circuit technology, and design technologies which allow a unified view of hardware and software co-design. Optimization of design metrics like cost, performance, power, and flexibility is a major challenge.
This document provides an overview of embedded system design. It discusses the characteristics of embedded systems and examples of embedded devices. It then covers key aspects of embedded system design including optimization of design metrics like cost, size and power. Processor technologies like general purpose, single purpose and application specific processors are described. The document also discusses integrated circuit technologies like full custom, semi-custom ASICs and programmable logic devices.
This document outlines the course contents for a VLSI Design course. The course covers six units: (1) an introduction to VLSI design including Moore's Law and design challenges, (2) VLSI circuit design processes and technologies, (3) analysis of CMOS logic circuits, (4) advanced CMOS logic circuit techniques, (5) memories, and (6) testing and testability. The goal of the course is to provide students with knowledge of very large scale integration circuits, which are essential components in modern electronic devices.
This document discusses digital VLSI design flows. It begins by acknowledging previous work that informed the presentation. It then discusses considerations in developing an electronic system, including components of the system. It describes integrated circuits based on application, fabrication technology, device, and device count. It discusses using standard or application-specific integrated circuits. It outlines a top-down design approach and terminology used in the design flow.
Performance and Flexibility for Mmultiple-Processor SoC DesignYalagoud Patil
Concepts, limitations of traditional ASIC design
Extensible processors as an alternative to RTL
Toward multiple-processor SoCs
Processors and disruptive technology
Conclusions
This document provides an overview of the ASIC back-end design flow, including timing driven placement. It discusses the inputs to the Astro placement and routing tool, including the gate-level netlist, standard cell library, and timing constraints. It describes key aspects of the placement process, including floorplanning, placement rows, and timing driven placement to optimize critical paths. The goal is to meet all timing constraints by balancing timing, area, power, and signal integrity.
System on Chip (SoC) designs integrate multiple components, such as processors, memory, and I/O, onto a single chip. This consolidation provides benefits like reduced cost and power consumption compared to using multiple discrete chips. The SoC design process involves specifying system functionality, defining an architecture to implement it using reusable intellectual property cores, and employing techniques like hardware-software codesign and spiral development models to improve productivity. Key challenges in SoC design include managing complexity, meeting tight schedules, and ensuring high design quality and verification.
The document discusses various programmable chip and board implementation technologies including PLDs, CPLDs, and FPGAs. It describes the basic components and features of these technologies. PLDs contain programmable logic arrays that can implement sum-of-products logic functions. CPLDs are an evolution of PLDs, containing multiple PALs and an interconnect matrix. FPGAs provide even higher densities by placing programmable logic elements in an array with a programmable routing fabric between them. The document discusses the logic elements, interconnect, memory blocks, I/O and other features of example FPGA families from Altera and Actel.
This document provides an introduction to VLSI design. It discusses the evolution of integrated circuits from SSI to VLSI, CMOS transistor structure and logic gates, the VLSI design process involving different levels of abstraction, design styles including full custom, ASIC, programmable logic, and system-on-chip. It also covers trends in transistor size, interconnect delay becoming dominant, and issues like power consumption and noise. The objectives are to understand transistor operation, CMOS logic, power and delay estimation, and layout design rules.
This document provides an overview of digital CMOS logic circuits. It discusses CMOS technology and how it has become the dominant technology for digital circuit implementation due to its low power dissipation and high integration density. The document then covers different logic circuit families including CMOS, bipolar, BiCMOS, and GaAs. It discusses characteristics of logic circuits like noise margins, propagation delay, power dissipation, silicon area, and fan-in/fan-out. Different digital system design styles using off-the-shelf components or custom VLSI chips are presented. The role of design abstraction and computer aids in facilitating large digital system design is also covered. Finally, the document discusses CMOS inverter circuit operation and the voltage transfer
The document provides a list of components and equipment with their specifications that are required for an electronics lab. It includes Xilinx software licenses, logic design software, FPGA development boards, and simulation tools. The listed items cover digital design, analog and mixed-signal circuit design, and FPGA programming. Specifications for Spartan-3 and Spartan-3 DSP FPGA development boards are also provided, describing their programmable logic chips, interfaces, and configuration options.
This document discusses the history of computer development and trends in computer hardware over time. It provides examples of early mainframe computers from 1965 that occupied entire rooms and cost millions, compared to modern laptops from 2008 that are thousands of times more powerful yet small and inexpensive. It outlines Moore's Law and trends related to transistor counts doubling every 1-2 years and processor performance doubling every 18 months. The document also discusses shrinking chip sizes over time and the limits of chip manufacturing.
Digital systems work with discrete-time and discrete-valued signals known as digital signals. Integrated circuits allow for highly compact and powerful digital systems by integrating millions of transistors onto a single silicon chip. Moore's law observed that the number of transistors on a chip doubles approximately every two years, driving continued improvements in speed, capacity, and functionality of digital electronics. Modern digital system design relies heavily on electronic design automation tools to manage increasing design complexity across multiple levels of abstraction.
This document provides an overview of Module 1 of the ECIE 4343 Very Large Scale Integrated Circuits (VLSI) Design course. The module introduces course logistics, content, and design implementation options. It outlines topics that will be covered including VLSI economy, MOSFET characteristics, circuit layout, fabrication, and CAD tools. A course schedule is provided listing weekly topics and assignments. Assessment breakdown consists of a final exam, project, midterm, and assignments/quizzes. Historical trends in transistor size reduction and integrated circuit scaling are reviewed.
The document discusses trends in integration technologies such as VLSI. It describes how VLSI has allowed for more compact, lower power, and higher speed integrated circuits. It classifies integrated circuits based on application, fabrication technique, technology, and device count. It then discusses the history of integrated circuits from the transistor in 1947 to modern chips containing tens of millions of transistors. It outlines drivers for VLSI technology including smaller sizes, lower power, and reduced costs.
This document outlines the typical design flow for VLSI chips, including: 1) design specification, 2) design entry using schematics or HDL, 3) functional simulation to verify logic, 4) planning placement and routing of components, 5) timing simulation accounting for delays, and 6) fabrication of the final chip design either using full custom or semi-custom methods. The goal is to design and test a chip that meets the specified requirements before manufacturing.
This document provides an overview of an ASIC/FPGA technology and design flow course. It discusses the course organization, material, schedule, and recommended literature. The course will cover FPGA and ASIC design flows, including Verilog, synthesis, simulation, and implementation. It will also discuss chip structures, technologies, applications and the semiconductor industry. Students will complete projects to design an FPGA peripheral and an ASIC, with design reviews to mimic industry practice. The goal is to prepare students for careers in chip design and verification.
This document discusses application-to-architecture mapping and hardware-software codesign. It describes traditional bottom-up and top-down design methodologies. It then summarizes hardware-software partitioning techniques including integer linear programming and global criticality/local phase approaches. Platform-based design is emerging as a trend, reusing architectures like Texas Instruments' OMAP platform or processor-centric platforms like Tensilica's Xtensa.
This document discusses digital system verification techniques. It reviews the conventional design and verification flow including simulation at different levels of abstraction. Key verification techniques are discussed including simulation, formal verification, and static timing analysis. An emerging verification paradigm is described that uses cycle-based simulation and formal verification for functional verification and static timing analysis for timing verification.
This document discusses the evolution of computer architecture from CISC to RISC designs. It provides details on major advances like microprogramming, cache memory, and microprocessors that influenced computer designs. Reduced Instruction Set Computers (RISC) aimed to improve performance by using simpler instructions optimized for pipelining. RISC relies on register-based operations while CISC uses more complex instructions mapped to microcode. The tradeoffs between the two approaches are still debated as most modern designs incorporate elements of both.
This document discusses the evolution of computer architecture from CISC to RISC designs. It provides details on major advances like microprogramming, cache memory, and microprocessors that influenced computer design. It then describes the key features of RISC systems like large register files, limited instruction sets, and emphasis on instruction pipelining. The document discusses optimizations for RISC designs like delayed branching and register allocation techniques. It also examines the debate around the performance of RISC versus CISC and notes most modern systems incorporate aspects of both.
This document discusses disruptive technologies, specifically how Moore's Law has impacted the technology industry and networking. It provides three key points:
1. Moore's Law, which predicted the doubling of transistors on integrated circuits every two years, has been the guiding principle for new product development. However, for networking, transistor count has doubled but speed has increased slowly.
2. Networking performance has not kept up with Moore's Law like CPU performance has. Network ASICs have increased 10x over 12 years while CPUs increased 64x.
3. Merchant silicon using full custom chip designs has allowed networking to scale at Moore's Law growth rates, providing higher port density, lower price per port, and lower power consumption
Digital Design Technology and Techniques. The class notes present basic digital logic design abstraction, electronic design process, and CAD tools for digital design.
This document provides an overview of computer aided design (CAD) and circuit simulation. It begins with warnings for the class and then defines CAD as using computers to model physical systems and design variants for manufacturing. It lists several CAD software programs and describes different types of circuit simulations, such as DC analysis and transient analysis. The document outlines the design and simulation process and discusses netlists, elements like sources and passive/active devices, and why simulation is important for verification.
An Experimental mmWave Channel Model for UAV to UAV Communication.pdfSambasiva62
This paper proposes an empirical propagation loss model for UAV-to-UAV communications at 60 GHz based on extensive measurement data collected from aerial experiments using Facebook Terragraph channel sounders mounted on DJI M600 drones. The measurement results validate the empirical path loss model and show that path loss does not have an explicit dependence on UAV height between 6-15 meters. The paper also compares the proposed model to 3GPP channel models and publicly releases the measurement dataset.
This document describes an IOT-based vehicle accident and alcohol detection system using GSM and GPS. The system aims to (1) track the location of an accident using GPS and send messages to emergency services and family, and (2) detect if the driver has consumed alcohol using an alcohol sensor and prevent the vehicle from moving if so, sending an alert to police. It consists of an ARM7 microcontroller interfaced with a GPS module, GSM module, MQ3 alcohol sensor and accelerometer. If an accident occurs, the location is sent via GSM. If alcohol is detected, the vehicle is stopped and police alerted. The system aims to reduce accidents and response time to save lives.
System on Chip (SoC) designs integrate multiple components, such as processors, memory, and I/O, onto a single chip. This consolidation provides benefits like reduced cost and power consumption compared to using multiple discrete chips. The SoC design process involves specifying system functionality, defining an architecture to implement it using reusable intellectual property cores, and employing techniques like hardware-software codesign and spiral development models to improve productivity. Key challenges in SoC design include managing complexity, meeting tight schedules, and ensuring high design quality and verification.
The document discusses various programmable chip and board implementation technologies including PLDs, CPLDs, and FPGAs. It describes the basic components and features of these technologies. PLDs contain programmable logic arrays that can implement sum-of-products logic functions. CPLDs are an evolution of PLDs, containing multiple PALs and an interconnect matrix. FPGAs provide even higher densities by placing programmable logic elements in an array with a programmable routing fabric between them. The document discusses the logic elements, interconnect, memory blocks, I/O and other features of example FPGA families from Altera and Actel.
This document provides an introduction to VLSI design. It discusses the evolution of integrated circuits from SSI to VLSI, CMOS transistor structure and logic gates, the VLSI design process involving different levels of abstraction, design styles including full custom, ASIC, programmable logic, and system-on-chip. It also covers trends in transistor size, interconnect delay becoming dominant, and issues like power consumption and noise. The objectives are to understand transistor operation, CMOS logic, power and delay estimation, and layout design rules.
This document provides an overview of digital CMOS logic circuits. It discusses CMOS technology and how it has become the dominant technology for digital circuit implementation due to its low power dissipation and high integration density. The document then covers different logic circuit families including CMOS, bipolar, BiCMOS, and GaAs. It discusses characteristics of logic circuits like noise margins, propagation delay, power dissipation, silicon area, and fan-in/fan-out. Different digital system design styles using off-the-shelf components or custom VLSI chips are presented. The role of design abstraction and computer aids in facilitating large digital system design is also covered. Finally, the document discusses CMOS inverter circuit operation and the voltage transfer
The document provides a list of components and equipment with their specifications that are required for an electronics lab. It includes Xilinx software licenses, logic design software, FPGA development boards, and simulation tools. The listed items cover digital design, analog and mixed-signal circuit design, and FPGA programming. Specifications for Spartan-3 and Spartan-3 DSP FPGA development boards are also provided, describing their programmable logic chips, interfaces, and configuration options.
This document discusses the history of computer development and trends in computer hardware over time. It provides examples of early mainframe computers from 1965 that occupied entire rooms and cost millions, compared to modern laptops from 2008 that are thousands of times more powerful yet small and inexpensive. It outlines Moore's Law and trends related to transistor counts doubling every 1-2 years and processor performance doubling every 18 months. The document also discusses shrinking chip sizes over time and the limits of chip manufacturing.
Digital systems work with discrete-time and discrete-valued signals known as digital signals. Integrated circuits allow for highly compact and powerful digital systems by integrating millions of transistors onto a single silicon chip. Moore's law observed that the number of transistors on a chip doubles approximately every two years, driving continued improvements in speed, capacity, and functionality of digital electronics. Modern digital system design relies heavily on electronic design automation tools to manage increasing design complexity across multiple levels of abstraction.
This document provides an overview of Module 1 of the ECIE 4343 Very Large Scale Integrated Circuits (VLSI) Design course. The module introduces course logistics, content, and design implementation options. It outlines topics that will be covered including VLSI economy, MOSFET characteristics, circuit layout, fabrication, and CAD tools. A course schedule is provided listing weekly topics and assignments. Assessment breakdown consists of a final exam, project, midterm, and assignments/quizzes. Historical trends in transistor size reduction and integrated circuit scaling are reviewed.
The document discusses trends in integration technologies such as VLSI. It describes how VLSI has allowed for more compact, lower power, and higher speed integrated circuits. It classifies integrated circuits based on application, fabrication technique, technology, and device count. It then discusses the history of integrated circuits from the transistor in 1947 to modern chips containing tens of millions of transistors. It outlines drivers for VLSI technology including smaller sizes, lower power, and reduced costs.
This document outlines the typical design flow for VLSI chips, including: 1) design specification, 2) design entry using schematics or HDL, 3) functional simulation to verify logic, 4) planning placement and routing of components, 5) timing simulation accounting for delays, and 6) fabrication of the final chip design either using full custom or semi-custom methods. The goal is to design and test a chip that meets the specified requirements before manufacturing.
This document provides an overview of an ASIC/FPGA technology and design flow course. It discusses the course organization, material, schedule, and recommended literature. The course will cover FPGA and ASIC design flows, including Verilog, synthesis, simulation, and implementation. It will also discuss chip structures, technologies, applications and the semiconductor industry. Students will complete projects to design an FPGA peripheral and an ASIC, with design reviews to mimic industry practice. The goal is to prepare students for careers in chip design and verification.
This document discusses application-to-architecture mapping and hardware-software codesign. It describes traditional bottom-up and top-down design methodologies. It then summarizes hardware-software partitioning techniques including integer linear programming and global criticality/local phase approaches. Platform-based design is emerging as a trend, reusing architectures like Texas Instruments' OMAP platform or processor-centric platforms like Tensilica's Xtensa.
This document discusses digital system verification techniques. It reviews the conventional design and verification flow including simulation at different levels of abstraction. Key verification techniques are discussed including simulation, formal verification, and static timing analysis. An emerging verification paradigm is described that uses cycle-based simulation and formal verification for functional verification and static timing analysis for timing verification.
This document discusses the evolution of computer architecture from CISC to RISC designs. It provides details on major advances like microprogramming, cache memory, and microprocessors that influenced computer designs. Reduced Instruction Set Computers (RISC) aimed to improve performance by using simpler instructions optimized for pipelining. RISC relies on register-based operations while CISC uses more complex instructions mapped to microcode. The tradeoffs between the two approaches are still debated as most modern designs incorporate elements of both.
This document discusses the evolution of computer architecture from CISC to RISC designs. It provides details on major advances like microprogramming, cache memory, and microprocessors that influenced computer design. It then describes the key features of RISC systems like large register files, limited instruction sets, and emphasis on instruction pipelining. The document discusses optimizations for RISC designs like delayed branching and register allocation techniques. It also examines the debate around the performance of RISC versus CISC and notes most modern systems incorporate aspects of both.
This document discusses disruptive technologies, specifically how Moore's Law has impacted the technology industry and networking. It provides three key points:
1. Moore's Law, which predicted the doubling of transistors on integrated circuits every two years, has been the guiding principle for new product development. However, for networking, transistor count has doubled but speed has increased slowly.
2. Networking performance has not kept up with Moore's Law like CPU performance has. Network ASICs have increased 10x over 12 years while CPUs increased 64x.
3. Merchant silicon using full custom chip designs has allowed networking to scale at Moore's Law growth rates, providing higher port density, lower price per port, and lower power consumption
Digital Design Technology and Techniques. The class notes present basic digital logic design abstraction, electronic design process, and CAD tools for digital design.
This document provides an overview of computer aided design (CAD) and circuit simulation. It begins with warnings for the class and then defines CAD as using computers to model physical systems and design variants for manufacturing. It lists several CAD software programs and describes different types of circuit simulations, such as DC analysis and transient analysis. The document outlines the design and simulation process and discusses netlists, elements like sources and passive/active devices, and why simulation is important for verification.
An Experimental mmWave Channel Model for UAV to UAV Communication.pdfSambasiva62
This paper proposes an empirical propagation loss model for UAV-to-UAV communications at 60 GHz based on extensive measurement data collected from aerial experiments using Facebook Terragraph channel sounders mounted on DJI M600 drones. The measurement results validate the empirical path loss model and show that path loss does not have an explicit dependence on UAV height between 6-15 meters. The paper also compares the proposed model to 3GPP channel models and publicly releases the measurement dataset.
This document describes an IOT-based vehicle accident and alcohol detection system using GSM and GPS. The system aims to (1) track the location of an accident using GPS and send messages to emergency services and family, and (2) detect if the driver has consumed alcohol using an alcohol sensor and prevent the vehicle from moving if so, sending an alert to police. It consists of an ARM7 microcontroller interfaced with a GPS module, GSM module, MQ3 alcohol sensor and accelerometer. If an accident occurs, the location is sent via GSM. If alcohol is detected, the vehicle is stopped and police alerted. The system aims to reduce accidents and response time to save lives.
The document summarizes various communication bands and their uses. The L-band from 1-2 GHz is used for radar, satellite communications, GPS signals, and weather systems. It has a low bandwidth but can penetrate clouds and weather. The S-band from 2-4 GHz is mainly used for radar systems and two-way communications for devices. It provides accurate radar data but can be affected by rain. The C-band from 4-8 GHz is used for satellite communications between ground stations and has less interference from rain than higher frequencies. It supports distribution of TV, mobile services, and disaster recovery.
1. The document discusses co-channel interference which occurs when the same frequency is reused in different cell locations. It describes how directional antennas and increasing the number of sectors can reduce this interference.
2. Methods to calculate the carrier-to-interference ratio in different scenarios are presented, including for omni-directional antennas with different frequency reuse patterns and for directional antenna systems.
3. Determining the co-channel interference area involves measuring signal levels with a mobile receiver and comparing to thresholds for carrier-to-interference and carrier-to-noise ratios.
This document discusses frequency management and channel assignment in cellular networks. It explains that frequency management divides available channels into subsets that can be assigned to each cell, either fixed or dynamically. It describes how channels are divided and grouped in the Advanced Mobile Phone System (AMPS). Channels can be assigned to cell sites on a long-term fixed basis or short-term dynamic basis. The document also discusses set-up channels, voice channels, frequency reuse patterns, and techniques for channel sharing, borrowing, and sectorization to improve spectrum efficiency and traffic capacity.
The document discusses various multiple access techniques used in wireless communication systems to allow multiple users to access a shared radio channel simultaneously. It describes Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Code Division Multiple Access (CDMA), and Space Division Multiple Access (SDMA). FDMA divides the bandwidth into different frequency channels. TDMA divides the time dimension into different time slots. CDMA uses unique codes to identify users within the same frequency band. SDMA enables spatial separation of users within the same frequency and time. The document provides details on the principles, advantages, and disadvantages of each multiple access technique.
The document discusses mobile radio propagation models. It begins by describing the free space propagation model, which predicts received signal strength between a transmitter and receiver with line of sight. It then discusses how distance, transmitted power, antenna gains, wavelength and losses impact received power based on Friis transmission equation. Later it introduces the ground reflection model, knife edge diffraction model and scattering model to account for common propagation mechanisms. It concludes by discussing how path loss models like log-distance and log-normal shadowing can be used for link budget design and outdoor propagation modeling.
A channel model is a mathematical representation of how a communication channel affects wireless signals. There are four categories of channel models: path loss models which represent signal power reduction over distance without filtering; purely stochastic models which address noise and multipath fading without geometry; spatial models which were developed for MIMO systems to account for antenna arrays; and ray tracing models which use location information to explicitly define scatterers. Channel models are essential for predicting link and system performance and reduce the need for costly measurement projects.
This document describes the design of custom single-purpose processors. It discusses converting algorithms to state machines and finite state machines with datapaths. It also covers creating the datapath and controller, including registers, functional units, multiplexors and the controller state table and implementation. The example shown is for a greatest common divisor processor.
This document provides an overview of 5G technology, including its evolution from previous generations of wireless technology. 5G is expected to offer speeds up to 1 Gbps, make wireless networks globally accessible at low cost, and support applications like wearable devices with AI capabilities. The architecture of 5G is designed as an open platform across different layers, including an Open Wireless Architecture for the physical and data link layers and an Open Transport Protocol for the transport and session layers. 5G aims to create a true wireless world with virtually no limitations on access or coverage areas.
This document discusses microprocessor interfacing and communication. It covers topics such as basic communication protocols using address, data and control buses. It describes different interfacing techniques like memory-mapped I/O, port-based I/O, and interrupt-driven I/O. Interrupts allow a peripheral to asynchronously signal the processor to service an event. The processor saves its state and jumps to a fixed or vectored interrupt service routine location to handle the interrupt before returning to the main program.
This document discusses various standard single-purpose processors including timers, counters, watchdog timers, UARTs, LCD controllers, stepper motor controllers, analog-to-digital converters, and real-time clocks. It provides details on the functionality and applications of these common peripherals, as well as examples of their basic configurations and implementations.
This document introduces embedded systems and their design challenges. It defines embedded systems as computing systems embedded within electronic devices that are single-functioned, tightly-constrained, and reactive in real-time. The key design challenge is optimizing numerous metrics like cost, size, performance, and time-to-market simultaneously. It also outlines common processor, integrated circuit, and design technologies used for embedded systems.
The document provides an overview of embedded systems including:
- Embedded systems are computing systems embedded within electronic devices like cameras, cell phones, and appliances.
- Designing embedded systems involves optimizing multiple metrics like cost, power usage, performance, and time to market. Improving one metric may negatively impact others.
- Time to market is an important metric as delays in releasing a product can result in significant lost revenues by missing the peak sales window.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
2. Contents
IC Technology:
• Introduction
• Full-Custom (VLSI) Technology
• Semicustom(ASIC) IC Technology
• Programmable Logic Devices(PLD) IC Technology
Design Technology:
• Automation: Synthesis
• Verification: Hardware Software Co-simulation
• Reuse: Intellectual Property cores
• Design Process Models
3. 3
Introduction
CMOS transistor:
• Source, Drain
– Diffusion area where electrons can flow
– Can be connected to metal contacts (via’s)
• Gate
– Polysilicon area where control voltage is applied
• Oxide
– Si O2 Insulator so the gate voltage can’t leak
4. 4
• Every dimension of the MOSFET has to scale
– (PMOS) Gate oxide has to scale down to
• Increase gate capacitance
• Reduce leakage current from S to D
• Pinch off current from source to drain
– Current gate oxide thickness is about 2.5-3nm
• That’s about 25 atoms!!!
source drain
oxide
gate
IC package IC
channel
Silicon substrate
6. 6
• FinFET has been manufactured to
18nm
– Still acts as a very good transistor
• Simulation shown that it can be scaled
to 10nm
– Quantum effect start to kick in
• Reduce mobility by ~10%
– Ballistic transport become significant
• Increase current by about ~20%
7. 7
NAND
• Metal layers for routing (~10)
• PMOS don’t like 0
• NMOS don’t like 1
• A stick diagram form the basis for mask sets
8. 8
Silicon manufacturing steps
• Tape out
– Send design to manufacturing
• Spin
– One time through the manufacturing process
• Photolithography
– Drawing patterns by using photoresist to form barriers for deposition
9. 9
Full Custom
• Very Large Scale Integration (VLSI)
• Placement
– Place and orient transistors
• Routing
– Connect transistors
• Sizing
– Make fat, fast wires or thin, slow wires
– May also need to size buffer
• Design Rules
– “simple” rules for correct circuit function
• Metal/metal spacing, min poly width…
10. 10
Full Custom
• Best size, power, performance
• Hand design
– Horrible time-to-market/flexibility/NRE cost…
– Reserve for the most important units in a processor
• ALU, Instruction fetch…
• Physical design tools
– Less optimal, but faster…
11. 11
Semi-Custom
• Gate Array
– Array of prefabricated gates
– “place” and route
– Higher density, faster time-to-market
– Does not integrate as well with full-custom
• Standard Cell
– A library of pre-designed cell
– Place and route
– Lower density, higher complexity
– Integrate great with full-custom
12. 12
Semi-Custom
• Most popular design style
• Jack of all trade
– Good
• Power, time-to-market,
performance, NRE cost, per-unit
cost, area…
• Master of none
– Integrate with full custom for
critical regions of design
14. 14
Programmable Logic Device
• Programmable Logic Device
– Programmable Logic Array, Programmable Array Logic, Field Programmable Gate
Array
• All layers already exist
– Designers can purchase an IC
– To implement desired functionality
• Connections on the IC are either created or destroyed to implement
• Benefits
– Very low NRE costs
– Great time to market
• Drawback
– High unit cost, bad for large volume
– Power
• Except special PLA
– slower
1600 usable gate, 7.5 ns
$7 list price
19. 19
• Design task
– Define system functionality
– Convert functionality to physical implementation while
• Satisfying constrained metrics
• Optimizing other design metrics
• Designing embedded systems is hard
– Complex functionality
• Millions of possible environment scenarios
• Competing, tightly constrained metrics
– Productivity gap
• As low as 10 lines of code or 100 transistors produced per day
Introduction
20. 20
Improving productivity
• Design technologies developed to improve productivity
• We focus on technologies advancing hardware/software unified
view
– Automation
• Program replaces manual design
• Synthesis
– Reuse
• Predesigned components
• Cores
• General-purpose and single-purpose processors on single IC
– Verification
• Ensuring correctness/completeness of each design step
• Hardware/software co-simulation
Reuse
Specificat
ion
Implement
ation
Automa
tion
Verificati
on
21. 21
Automation: synthesis
• Early design mostly hardware
• Software complexity increased with advent
of general-purpose processor
• Different techniques for software design
and hardware design
– Caused division of the two fields
• Design tools evolve for higher levels of
abstraction
– Different rate in each field
• Hardware/software design fields rejoining
– Both can start from behavioral description
in sequential program model
– 30 years longer for hardware design to
reach this step in the ladder
• Many more design dimensions
• Optimization critical
Implementation
Assembly instructions
Machine instructions Logic gates
Logic equations / FSM's
Register transfers
Sequential program code (e.g., C, VHDL)
Compilers
(1960s,1970s)
Assemblers, linkers
(1950s, 1960s)
Behavioral synthesis
(1990s)
RT synthesis
(1980s, 1990s)
Logic synthesis
(1970s, 1980s)
Microprocessor plus
program bits
VLSI, ASIC, or PLD
implementation
The codesign ladder
23. 23
Increasing abstraction level
• Higher abstraction level focus of hardware/software design evolution
– Description smaller/easier to capture
• E.g., Line of sequential program code can translate to 1000 gates
– Many more possible implementations available
• (a) Like flashlight, the higher above the ground, the more ground illuminated
– Sequential program designs may differ in performance/transistor count by orders of
magnitude
– Logic-level designs may differ by only power of 2
• (b) Design process proceeds to lower abstraction level, narrowing in on single
implementation
(a) (b)
idea
implemen
tation
back-of-the-envelope
sequential program
register-transfers
logic
modeling
cost
increases
opportunities
decrease
idea
implemen
tation
24. 24
Synthesis
• Automatically converting system’s behavioral description to a structural
implementation
– Complex whole formed by parts
– Structural implementation must optimize design metrics
• More expensive, complex than compilers
– Cost = $100s to $10,000s
– User controls 100s of synthesis options
– Optimization critical
• Otherwise could use software
– Optimizations different for each user
– Run time = hours, days
25. 25
Gajski’s Y-chart
• Each axis represents type of description
– Behavioral
• Defines outputs as function of inputs
• Algorithms but no implementation
– Structural
• Implements behavior by connecting
components with known behavior
– Physical
• Gives size/locations of components and
wires on chip/board
• Synthesis converts behavior at given level
to structure at same level or lower
– E.g.,
• FSM → gates, flip-flops (same level)
• FSM → transistors (lower level)
• FSM X registers, FUs (higher level)
• FSM X processors, memories (higher level)
Behavior
Physical
Structural
Processors,
memories
Registers, FUs, MUXs
Gates, flip-flops
Transistors
Sequential
programs
Register
transfers
Logic
equations/FSM
Transfer
functions
Cell Layout
Modules
Chips
Boards
26. 26
Logic synthesis
• Logic-level behavior to structural implementation
– Logic equations and/or FSM to connected gates
• Combinational logic synthesis
– Two-level minimization (Sum of products/product of sums)
• Best possible performance
– Longest path = 2 gates (AND gate + OR gate/OR gate + AND gate)
• Minimize size
– Minimum cover
– Minimum cover that is prime
– Heuristics
– Multilevel minimization
• Trade performance for size
• Pareto-optimal solution
– Heuristics
• FSM synthesis
– State minimization
– State encoding
27. 27
Two-level minimization
• Represent logic function as sum of
products (or product of sums)
– AND gate for each product
– OR gate for each sum
• Gives best possible performance
– At most 2 gate delay
• Goal: minimize size
– Minimum cover
• Minimum # of AND gates (sum of products)
– Minimum cover that is prime
• Minimum # of inputs to each AND gate (sum of
products)
F = abc'd' + a'b'cd +
a'bcd + ab'cd
Sum of products
4 4-input AND gates and
1 4-input OR gate
→ 40 transistors
a
b
c
d
F
Direct implementation
28. 28
Minimum cover
• Minimum # of AND gates (sum of products)
• Literal: variable or its complement
– a or a’, b or b’, etc.
• Minterm: product of literals
– Each literal appears exactly once
• abc’d’, ab’cd, a’bcd, etc.
• Implicant: product of literals
– Each literal appears no more than once
• abc’d’, a’cd, etc.
– Covers 1 or more minterms
• a’cd covers a’bcd and a’b’cd
• Cover: set of implicants that covers all minterms of function
• Minimum cover: cover with minimum # of implicants
29. 29
Minimum cover: K-map approach
• Karnaugh map (K-map)
– 1 represents minterm
– Circle represents implicant
• Minimum cover
– Covering all 1’s with min # of
circles
– Example: direct vs. min cover
• Less gates
– 4 vs. 5
• Less transistors
– 28 vs. 40
11
1
0 0 0
0 0 1 0
1 0 0 0
0 0 0
ab
cd
00
01
11
10
00 01 10
1
1
0 0 0
0 0 1 0
1 0 0 0
0 0 0
ab
cd
00
01
11
10
00 01 11 10
1
F=abc'd' + a'cd + ab'cd
a
b
c
d
F
2 4-input AND
gate
1 3-input AND
gates
1 4 input OR
gate
→ 28
transistors
K-map: sum of products K-map: minimum cover
Minimum cover
Minimum cover implementation
30. 30
Minimum cover that is prime
• Minimum # of inputs to AND gates
• Prime implicant
– Implicant not covered by any other
implicant
– Max-sized circle in K-map
• Minimum cover that is prime
– Covering with min # of prime implicants
– Min # of max-sized circles
– Example: prime cover vs. min cover
• Same # of gates
– 4 vs. 4
• Less transistors
– 26 vs. 28
1
0 0 0
0 0 1 0
1 0 0 0
0 0 0
ab
cd
00
01
11
10
00 01 11 10
1
K-map: minimum cover that is prime
Minimum cover that is prime
F=abc'd' + a'cd + b'cd
1 4-input AND
gate
2 3-input AND
gates
1 4 input OR
gate
→ 26 transistors
F
a
b
c
d
Implementation
31. 31
Minimum cover: heuristics
• K-maps give optimal solution every time
– Functions with > 6 inputs too complicated
– Use computer-based tabular method
• Finds all prime implicants
• Finds min cover that is prime
• Also optimal solution every time
• Problem: 2n minterms for n inputs
– 32 inputs = 4 billion minterms
– Exponential complexity
• Heuristic
– Solution technique where optimal solution not guaranteed
– Hopefully comes close
32. 32
Heuristics: iterative improvement
• Start with initial solution
– i.e., original logic equation
• Repeatedly make modifications toward better solution
• Common modifications
– Expand
• Replace each nonprime implicant with a prime implicant covering it
• Delete all implicants covered by new prime implicant
– Reduce
• Opposite of expand
– Reshape
• Expands one implicant while reducing another
• Maintains total # of implicants
– Irredundant
• Selects min # of implicants that cover from existing implicants
• Synthesis tools differ in modifications used and the order they are used
33. 33
Multilevel logic minimization
• Trade performance for size
– Increase delay for lower # of gates
– Gray area represents all possible
solutions
– Circle with X represents ideal solution
• Generally not possible
– 2-level gives best performance
• max delay = 2 gates
• Solve for smallest size
– Multilevel gives pareto-optimal
solution
• Minimum delay for a given size
• Minimum size for a given delay
size
delay
2-level
minim.
34. 34
Example
• Minimized 2-level logic function:
– F = adef + bdef + cdef + gh
– Requires 5 gates with 18 total gate inputs
• 4 ANDS and 1 OR
• After algebraic manipulation:
– F = (a + b + c)def + gh
– Requires only 4 gates with 11 total gate inputs
• 2 ANDS and 2 ORs
– Less inputs per gate
– Assume gate inputs = 2 transistors
• Reduced by 14 transistors
– 36 (18 * 2) down to 22 (11 * 2)
– Sacrifices performance for size
• Inputs a, b, and c now have 3-gate delay
• Iterative improvement heuristic commonly
used
F
b
c
e
a
d
f
g
h
2-level minimized
F
b
c
e
a
d
f
g
h
multilevel minimized
35. 35
FSM synthesis
• FSM to gates
• State minimization
– Reduce # of states
• Identify and merge equivalent states
– Outputs, next states same for all possible inputs
– Tabular method gives exact solution
» Table of all possible state pairs
» If n states, n2 table entries
» Thus, heuristics used with large # of states
• State encoding
– Unique bit sequence for each state
– If n states, log2(n) bits
– n! possible encodings
– Thus, heuristics common
36. 36
Technology mapping
• Library of gates available for implementation
– Simple
• only 2-input AND,OR gates
– Complex
• various-input AND,OR,NAND,NOR,etc. gates
• Efficiently implemented meta-gates (i.e., AND-OR-INVERT,MUX)
• Final structure consists of specified library’s components only
• If technology mapping integrated with logic synthesis
– More efficient circuit
– More complex problem
– Heuristics required
37. 37
Complexity impact on user
• As complexity grows, heuristics used
• Heuristics differ tremendously among synthesis tools
– Computationally expensive
• Higher quality results
• Variable optimization effort settings
• Long run times (hours, days)
• Requires huge amounts of memory
• Typically needs to run on servers, workstations
– Fast heuristics
• Lower quality results
• Shorter run times (minutes, hours)
• Smaller amount of memory required
• Could run on PC
• Super-linear-time (i.e. n3) heuristics usually used
– User can partition large systems to reduce run times/size
– 1003 > 503 + 503 (1,000,000 > 250,000)
38. 38
Integrating logic design and physical
design
• Past
– Gate delay much greater than wire delay
– Thus, performance evaluated as # of levels
of gates only
• Today
– Gate delay shrinking as feature size
shrinking
– Wire delay increasing
• Performance evaluation needs wire length
– Transistor placement (needed for wire
length) domain of physical design
– Thus, simultaneous logic synthesis and
physical design required for efficient
circuits
Wire
Transistor
Delay
Reduced feature size
39. 39
Register-transfer synthesis
• Converts FSMD to custom single-purpose processor
– Datapath
• Register units to store variables
– Complex data types
• Functional units
– Arithmetic operations
• Connection units
– Buses, MUXs
– FSM controller
• Controls datapath
– Key sub problems:
• Allocation
– Instantiate storage, functional, connection units
• Binding
– Mapping FSMD operations to specific units
40. 40
Behavioral synthesis
• High-level synthesis
• Converts single sequential program to single-purpose processor
– Does not require the program to schedule states
• Key sub problems
– Allocation
– Binding
– Scheduling
• Assign sequential program’s operations to states
• Conversion template given in Ch. 2
• Optimizations important
– Compiler
• Constant propagation, dead-code elimination, loop unrolling
– Advanced techniques for allocation, binding, scheduling
41. 41
System synthesis
• Convert 1 or more processes into 1 or more processors
(system)
– For complex embedded systems
• Multiple processes may provide better performance/power
• May be better described using concurrent sequential programs
• Tasks
– Transformation
• Can merge 2 exclusive processes into 1 process
• Can break 1 large process into separate processes
• Procedure inlining
• Loop unrolling
– Allocation
• Essentially design of system architecture
– Select processors to implement processes
– Also select memories and busses
42. 42
System synthesis
• Tasks (cont.)
– Partitioning
• Mapping 1 or more processes to 1 or more processors
• Variables among memories
• Communications among buses
– Scheduling
• Multiple processes on a single processor
• Memory accesses
• Bus communications
– Tasks performed in variety of orders
– Iteration among tasks common
43. 43
System synthesis
• Synthesis driven by constraints
– E.g.,
• Meet performance requirements at minimum cost
– Allocate as much behavior as possible to general-purpose processor
» Low-cost/flexible implementation
– Minimum # of SPPs used to meet performance
• System synthesis for GPP only (software)
– Common for decades
• Multiprocessing
• Parallel processing
• Real-time scheduling
• Hardware/software codesign
– Simultaneous consideration of GPPs/SPPs during synthesis
– Made possible by maturation of behavioral synthesis in 1990’s
44. 44
Temporal vs. spatial thinking
• Design thought process changed by evolution of synthesis
• Before synthesis
– Designers worked primarily in structural domain
• Connecting simpler components to build more complex systems
– Connecting logic gates to build controller
– Connecting registers, MUXs, ALUs to build datapath
– “capture and simulate” era
• Capture using CAD tools
• Simulate to verify correctness before fabricating
– Spatial thinking
• Structural diagrams
• Data sheets
45. 45
Temporal vs. spatial thinking
• After synthesis
– “describe-and-synthesize” era
– Designers work primarily in behavioral domain
– “describe and synthesize” era
• Describe FSMDs or sequential programs
• Synthesize into structure
– Temporal thinking
• States or sequential statements have relationship over time
• Strong understanding of hardware structure still important
– Behavioral description must synthesize to efficient structural
implementation
46. 46
Verification
• Ensuring design is correct and complete
– Correct
• Implements specification accurately
– Complete
• Describes appropriate output to all relevant input
• Formal verification
– Hard
– For small designs or verifying certain key properties only
• Simulation
– Most common verification method
47. 47
Formal verification
• Analyze design to prove or disprove certain properties
• Correctness example
– Prove ALU structural implementation equivalent to behavioral
description
• Derive Boolean equations for outputs
• Create truth table for equations
• Compare to truth table from original behavior
• Completeness example
– Formally prove elevator door can never open while elevator is moving
• Derive conditions for door being open
• Show conditions conflict with conditions for elevator moving
48. 48
Simulation
• Create computer model of design
– Provide sample input
– Check for acceptable output
• Correctness example
– ALU
• Provide all possible input combinations
• Check outputs for correct results
• Completeness example
– Elevator door closed when moving
• Provide all possible input sequences
• Check door always closed when elevator moving
49. 49
Increases confidence
• Simulating all possible input sequences impossible for most
systems
– E.g., 32-bit ALU
• 232 * 232 = 264 possible input combinations
• At 1 million combinations/sec
• ½ million years to simulate
• Sequential circuits even worse
• Can only simulate tiny subset of possible inputs
– Typical values
– Known boundary conditions
• E.g., 32-bit ALU
– Both operands all 0’s
– Both operands all 1’s
• Increases confidence of correctness/completeness
• Does not prove
50. 50
Advantages over physical
implementation
• Controllability
– Control time
• Stop/start simulation at any time
– Control data values
• Inputs or internal values
• Observability
– Examine system/environment values at any time
• Debugging
– Can stop simulation at any point and:
• Observe internal values
• Modify system/environment values before restarting
– Can step through small intervals (i.e., 500 nanoseconds)
51. 51
Disadvantages
• Simulation setup time
– Often has complex external environments
– Could spend more time modeling environment than system
• Models likely incomplete
– Some environment behavior undocumented if complex environment
– May not model behavior correctly
• Simulation speed much slower than actual execution
– Sequentializing parallel design
• IC: gates operate in parallel
• Simulation: analyze inputs, generate outputs for each gate 1 at time
– Several programs added between simulated system and real hardware
• 1 simulated operation:
– = 10 to 100 simulator operations
– = 100 to 10,000 operating system operations
– = 1,000 to 100,000 hardware operations
52. 52
Simulation speed
• Relative speeds of different types of
simulation/emulation
– 1 hour actual execution of SOC
• = 1.2 years instruction-set simulation
• = 10,000,000 hours gate-level simulation
10,000,000 gate-level HDL simulation
register-transfer-level HDL simulation
cycle-accurate simulation
instruction-set simulation
throughput model
hardware emulation
FPGA 1 day
1 hour
4 days
1
10
100
1000
10000
100,000
1,000,000
IC
1.4 months
1.2 years
12 years
>1 lifetime
1 millennium
53. 53
Overcoming long simulation time
• Reduce amount of real time simulated
– 1 msec execution instead of 1 hour
• 0.001sec * 10,000,000 = 10,000 sec = 3 hours
– Reduced confidence
• 1 msec of cruise controller operation tells us little
• Faster simulator
– Emulators
• Special hardware for simulations
– Less precise/accurate simulators
• Exchange speed for observability/controllability
54. 54
Reducing precision/accuracy
• Don’t need gate-level analysis for all simulations
– E.g., cruise control
• Don’t care what happens at every input/output of each logic gate
– Simulating RT components ~10x faster
– Cycle-based simulation ~100x faster
• Accurate at clock boundaries only
• No information on signal changes between boundaries
• Faster simulator often combined with reduction in real time
– If willing to simulate for 10 hours
• Use instruction-set simulator
• Real execution time simulated
– 10 hours * 1 / 10,000
– = 0.001 hour
– = 3.6 seconds
55. 55
Hardware/software co-simulation
• Variety of simulation approaches exist
– From very detailed
• E.g., gate-level model
– To very abstract
• E.g., instruction-level model
• Simulation tools evolved separately for hardware/software
– Recall separate design evolution
– Software (GPP)
• Typically with instruction-set simulator (ISS)
– Hardware (SPP)
• Typically with models in HDL environment
• Integration of GPP/SPP on single IC creating need for merging
simulation tools
56. 56
Integrating GPP/SPP simulations
• Simple/naïve way
– HDL model of microprocessor
• Runs system software
• Much slower than ISS
• Less observable/controllable than ISS
– HDL models of SPPs
– Integrate all models
• Hardware-software co-simulator
– ISS for microprocessor
– HDL model for SPPs
– Create communication between simulators
– Simulators run separately except when transferring data
– Faster
– Though, frequent communication between ISS and HDL model slows it down
57. 57
Minimizing communication
• Memory shared between GPP and SPPs
– Where should memory go?
– In ISS
• HDL simulator must stall for memory access
– In HDL?
• ISS must stall when fetching each instruction
• Model memory in both ISS and HDL
– Most accesses by each model unrelated to other’s accesses
• No need to communicate these between models
– Co-simulator ensures consistency of shared data
– Huge speedups (100x or more) reported with this technique
58. 58
Emulators
• General physical device system mapped to
– Microprocessor emulator
• Microprocessor IC with some monitoring, control circuitry
– SPP emulator
• FPGAs (10s to 100s)
– Usually supports debugging tasks
• Created to help solve simulation disadvantages
– Mapped relatively quickly
• Hours, days
– Can be placed in real environment
• No environment setup time
• No incomplete environment
– Typically faster than simulation
• Hardware implementation
59. 59
Disadvantages
• Still not as fast as real implementations
– E.g., emulated cruise-control may not respond fast
enough to keep control of car
• Mapping still time consuming
– E.g., mapping complex SOC to 10 FPGAs
• Just partitioning into 10 parts could take weeks
• Can be very expensive
– Top-of-the-line FPGA-based emulator: $100,000 to
$1mill
– Leads to resource bottleneck
• Can maybe only afford 1 emulator
• Groups wait days, weeks for other group to finish using
60. 60
Reuse: intellectual property cores
• Commercial off-the-shelf (COTS) components
– Predesigned, prepackaged ICs
– Implements GPP or SPP
– Reduces design/debug time
– Have always been available
• System-on-a-chip (SOC)
– All components of system implemented on single chip
– Made possible by increasing IC capacities
– Changing the way COTS components sold
• As intellectual property (IP) rather than actual IC
– Behavioral, structural, or physical descriptions
– Processor-level components known as cores
• SOC built by integrating multiple descriptions
61. 61
Cores
• Soft core
– Synthesizable behavioral
description
– Typically written in HDL
(VHDL/Verilog)
• Firm core
– Structural description
– Typically provided in HDL
• Hard core
– Physical description
– Provided in variety of physical
layout file formats
Behavior
Physical
Structural
Processors,
memories
Registers, FUs,
MUXs
Gates, flip-flops
Transistors
Sequential
programs
Register
transfers
Logic
equations/FSM
Transfer
functions
Cell Layout
Modules
Chips
Boards
Gajski’s Y-chart
62. 62
Advantages/disadvantages of hard
core
• Ease of use
– Developer already designed and tested core
• Can use right away
• Can expect to work correctly
• Predictability
– Size, power, performance predicted accurately
• Not easily mapped (retargeted) to different
process
– E.g., core available for vendor X’s 0.25 micrometer
CMOS process
• Can’t use with vendor X’s 0.18 micrometer process
• Can’t use with vendor Y
63. 63
Advantages/disadvantages of soft/firm
cores
• Soft cores
– Can be synthesized to nearly any technology
– Can optimize for particular use
• E.g., delete unused portion of core
– Lower power, smaller designs
– Requires more design effort
– May not work in technology not tested for
– Not as optimized as hard core for same processor
• Firm cores
– Compromise between hard and soft cores
• Some retargetability
• Limited optimization
• Better predictability/ease of use
64. 64
New challenges to processor providers
• Cores have dramatically changed business model
– Pricing models
• Past
– Vendors sold product as IC to designers
– Designers must buy any additional copies
» Could not (economically) copy from original
• Today
– Vendors can sell as IP
– Designers can make as many copies as needed
• Vendor can use different pricing models
– Royalty-based model
» Similar to old IC model
» Designer pays for each additional model
– Fixed price model
» One price for IP and as many copies as needed
– Many other models used
65. 65
IP protection
• Past
– Illegally copying IC very difficult
• Reverse engineering required tremendous, deliberate effort
• “Accidental” copying not possible
• Today
– Cores sold in electronic format
• Deliberate/accidental unauthorized copying easier
• Safeguards greatly increased
• Contracts to ensure no copying/distributing
• Encryption techniques
– limit actual exposure to IP
• Watermarking
– determines if particular instance of processor was copied
– whether copy authorized
66. 66
New challenges to processor users
• Licensing arrangements
– Not as easy as purchasing IC
– More contracts enforcing pricing model and IP protection
• Possibly requiring legal assistance
• Extra design effort
– Especially for soft cores
• Must still be synthesized and tested
• Minor differences in synthesis tools can cause problems
• Verification requirements more difficult
– Extensive testing for synthesized soft cores and soft/firm cores mapped to particular
technology
• Ensure correct synthesis
• Timing and power vary between implementations
– Early verification critical
• Cores buried within IC
• Cannot simply replace bad core
67. 67
Design process model
• Describes order that design steps are
processed
– Behavior description step
– Behavior to structure conversion step
– Mapping structure to physical implementation
step
• Waterfall model
– Proceed to next step only after current step
completed
• Spiral model
– Proceed through 3 steps in order but with less
detail
– Repeat 3 steps gradually increasing detail
– Keep repeating until desired system obtained
– Becoming extremely popular (hardware &
software development)
Behavioral
Structural
Physical
Waterfall design model
Behavioral
Structural
Physical
Spiral design model
68. 68
Waterfall method
• Not very realistic
– Bugs often found in later steps that must be fixed in
earlier step
• E.g., forgot to handle certain input condition
– Prototype often needed to know complete desired
behavior
• E.g, customer adds features after product demo
– System specifications commonly change
• E.g., to remain competitive by reducing power, size
– Certain features dropped
• Unexpected iterations back through 3 steps
cause missed deadlines
– Lost revenues
– May never make it to market
Behavioral
Structural
Physical
Waterfall design model
69. 69
Spiral method
• First iteration of 3 steps incomplete
• Much faster, though
– End up with prototype
• Use to test basic functions
• Get idea of functions to add/remove
– Original iteration experience helps in following
iterations of 3 steps
• Must come up with ways to obtain structure and
physical implementations quickly
– E.g., FPGAs for prototype
• silicon for final product
– May have to use more tools
• Extra effort/cost
• Could require more time than waterfall method
– If correct implementation first time with waterfall
Behavioral
Structural
Physical
Spiral design model
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General-purpose processor design
models
• Previous slides focused on SPPs
• Can apply equally to GPPs
– Waterfall model
• Structure developed by particular company
• Acquired by embedded system designer
• Designer develops software (behavior)
• Designer maps application to architecture
– Compilation
– Manual design
– Spiral-like model
• Beginning to be applied by embedded system designers
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Spiral-like model
• Designer develops or acquires architecture
• Develops application(s)
• Maps application to architecture
• Analyzes design metrics
• Now makes choice
– Modify mapping
– Modify application(s) to better suit architecture
– Modify architecture to better suit application(s)
• Not as difficult now
– Maturation of synthesis/compilers
– IPs can be tuned
• Continue refining to lower abstraction level until
particular implementation chosen
Architecture Application(s)
Mapping
Analysis
Y-chart
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Summary
• Design technology seeks to reduce gap between
IC capacity growth and designer productivity
growth
• Synthesis has changed digital design
• Increased IC capacity means sw/hw components
coexist on one chip
• Design paradigm shift to core-based design
• Simulation essential but hard
• Spiral design process is popular