IMEC is an independent research organization established in 1984 by the Flemish government. It has over 1,000 employees across multiple sites worldwide and collaborates with over 600 companies and 208 universities. IMEC conducts world-leading research in nano-electronics, with a focus on scientific knowledge and innovative partnerships to develop industry-relevant technology solutions. Its research programs span areas like healthcare, energy, wireless communications, and more.
The document describes a joint consortium between IMEC, LETI, and IHP called ePIXfab that aims to provide expertise and services for multi-project wafer runs and packaging integration. IMEC in particular has world-leading research in nano-electronics with clean rooms and facilities for CMOS scaling down to 65nm, MEMS, silicon photonics, and more. The consortium offers MPW runs on their 200mm CMOS process as well as packaging and integration services through the EU-funded ESSenTIAL support action.
ALD/CVD applications, equipment and precursors in high volume manufacturingJonas Sundqvist
This document discusses trends in atomic layer deposition (ALD) and chemical vapor deposition (CVD) applications, equipment, and precursors for high-volume manufacturing. It notes that ALD equipment sales have grown to $1.8-1.9 billion annually, with 300mm spatial ALD and multi-wafer tools gaining market share. Advanced logic and memory nodes like 10nm and 7nm are driving increased use of ALD for applications like high-k dielectrics. Key precursor suppliers are also discussed.
Driven by application diversification, IPDs (integrated passive devices) continue their promising
growth.
Today, miniaturization and integration are key drivers in electronic devices. This is even more critical in several consumer applications, where thinner devices mean higher integration levels, necessitating low-profile components.
More information on that report at http://www.i-micronews.com/reports.html
Etching
In order to form a functional MEMS structure on a substrate, it is necessary to etch the thin films previously deposited and/or the substrate itself. In general, there are two classes of etching processes:
Wet etching where the material is dissolved when immersed in a chemical solution
Dry etching where the material is sputtered or dissolved using reactive ions or a vapour phase etchant
On-chip ESD protection for Silicon PhotonicsSofics
In the past, Fiber-optic communication was used only for long distance communication (50 km and beyond). Only a limited number of these high-end interface products were required worldwide. More recently, companies running large data centers (Facebook, Google, Amazon,...) like to replace the traditional cabling between server racks. The copper-based approach is considered a bottleneck for further improvements in data transfer capacity. Optical fiber can dramatically increase the bandwidth between servers and reduce complexity.
Thus, the optical interconnect suppliers now need to produce a large number of their products. To reduce the cost, they separate the optical parts (laser diodes, photo detectors) from the digital controller circuits. That allows to rely on advanced, standard CMOS technology for those controller circuits, enabling a cost-effective high-volume production. Both elements are combined within a single IC package using advanced packing techniques.
The 25-56Gbps interfaces consist of SerDes-type circuits and are integrated into advanced CMOS technology like 28nm CMOS. To create such high-speed differential I/O circuits, designers utilize the thin oxide transistors. However, those transistors are very sensitive and can be easily damaged during transient events like electrostatic discharge (ESD).
Despite the fact that the sensitive pads are not connected outside of the package, they could still receive ESD stress during assembly. Therefore, adequate protection clamps need to be inserted at the bond pads. On the other hand, for signal integrity, it is important to limit the capacitance between the interface pads and the supply lines.
Sofics has worked with several companies developing these optical interconnect interfaces. Sofics developed ESD protection with parasitic capacitance below 15fF, ten times lower than the typical low-cap ESD protection devices in TSMC 28nm CMOS.
SPICE Compatible Models for Circuit Simulation of ESD EventsTsuyoshi Horigome
This document discusses SPICE compatible models for circuit simulation of ESD events. It motivates the need for ESD simulation by discussing how it allows prediction of robustness prior to manufacture. The document outlines the modeling objectives of accuracy, simplicity, integration and comprehensiveness. It describes developing models for the SiGe bipolar process that capture junction breakdown, avalanche current and failure metrics. An example of simulating a full-chip ESD event that identifies a failure is presented along with the solution of adding a resistor.
The document describes a joint consortium between IMEC, LETI, and IHP called ePIXfab that aims to provide expertise and services for multi-project wafer runs and packaging integration. IMEC in particular has world-leading research in nano-electronics with clean rooms and facilities for CMOS scaling down to 65nm, MEMS, silicon photonics, and more. The consortium offers MPW runs on their 200mm CMOS process as well as packaging and integration services through the EU-funded ESSenTIAL support action.
ALD/CVD applications, equipment and precursors in high volume manufacturingJonas Sundqvist
This document discusses trends in atomic layer deposition (ALD) and chemical vapor deposition (CVD) applications, equipment, and precursors for high-volume manufacturing. It notes that ALD equipment sales have grown to $1.8-1.9 billion annually, with 300mm spatial ALD and multi-wafer tools gaining market share. Advanced logic and memory nodes like 10nm and 7nm are driving increased use of ALD for applications like high-k dielectrics. Key precursor suppliers are also discussed.
Driven by application diversification, IPDs (integrated passive devices) continue their promising
growth.
Today, miniaturization and integration are key drivers in electronic devices. This is even more critical in several consumer applications, where thinner devices mean higher integration levels, necessitating low-profile components.
More information on that report at http://www.i-micronews.com/reports.html
Etching
In order to form a functional MEMS structure on a substrate, it is necessary to etch the thin films previously deposited and/or the substrate itself. In general, there are two classes of etching processes:
Wet etching where the material is dissolved when immersed in a chemical solution
Dry etching where the material is sputtered or dissolved using reactive ions or a vapour phase etchant
On-chip ESD protection for Silicon PhotonicsSofics
In the past, Fiber-optic communication was used only for long distance communication (50 km and beyond). Only a limited number of these high-end interface products were required worldwide. More recently, companies running large data centers (Facebook, Google, Amazon,...) like to replace the traditional cabling between server racks. The copper-based approach is considered a bottleneck for further improvements in data transfer capacity. Optical fiber can dramatically increase the bandwidth between servers and reduce complexity.
Thus, the optical interconnect suppliers now need to produce a large number of their products. To reduce the cost, they separate the optical parts (laser diodes, photo detectors) from the digital controller circuits. That allows to rely on advanced, standard CMOS technology for those controller circuits, enabling a cost-effective high-volume production. Both elements are combined within a single IC package using advanced packing techniques.
The 25-56Gbps interfaces consist of SerDes-type circuits and are integrated into advanced CMOS technology like 28nm CMOS. To create such high-speed differential I/O circuits, designers utilize the thin oxide transistors. However, those transistors are very sensitive and can be easily damaged during transient events like electrostatic discharge (ESD).
Despite the fact that the sensitive pads are not connected outside of the package, they could still receive ESD stress during assembly. Therefore, adequate protection clamps need to be inserted at the bond pads. On the other hand, for signal integrity, it is important to limit the capacitance between the interface pads and the supply lines.
Sofics has worked with several companies developing these optical interconnect interfaces. Sofics developed ESD protection with parasitic capacitance below 15fF, ten times lower than the typical low-cap ESD protection devices in TSMC 28nm CMOS.
SPICE Compatible Models for Circuit Simulation of ESD EventsTsuyoshi Horigome
This document discusses SPICE compatible models for circuit simulation of ESD events. It motivates the need for ESD simulation by discussing how it allows prediction of robustness prior to manufacture. The document outlines the modeling objectives of accuracy, simplicity, integration and comprehensiveness. It describes developing models for the SiGe bipolar process that capture junction breakdown, avalanche current and failure metrics. An example of simulating a full-chip ESD event that identifies a failure is presented along with the solution of adding a resistor.
Direct Bond Interconnect (DBI) Technology as an Alternative to Thermal Compre...Invensas
DBI® is a low temperature hybrid direct bonding technology that allows wafers or die to be bonded with exceptionally fine pitch 3D electrical interconnect.
The document provides an overview of the history and evolution of semiconductors and integrated circuits from 1947 to present. It discusses key inventions and milestones such as the transistor in 1947, the integrated circuit in 1961, and Moore's Law predicting transistor doubling every two years. It also covers different chip design approaches including full custom, standard cell, gate arrays, and FPGAs, along with their relative costs, performance, and design complexities.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and Fin...Sofics
Sofics presentation (B2.2) at the 1st International EOS/ESD Symposium on Design and System (IEDS). IEDS is dedicated to the fundamental understanding of issues related to electrostatic discharge on design and system and the application of this knowledge to the solution of problems.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
1) 3D IC designs stack multiple silicon dies on top of each other using through-silicon vias (TSVs) to connect the dies. This overcomes limitations of conventional 2D designs like Moore's law.
2) Key advantages of 3D IC include higher density, performance and lower power consumption from shorter interconnects. It also enables heterogeneous integration and improves reliability.
3) Challenges include developing 3D transistor architectures, managing variability and thermal issues across stacked dies, and ensuring design and manufacturing tools are ready to support 3D IC. Major applications are seen in memory, imaging sensors and processors.
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
This document summarizes research on high-k dielectric devices fabricated using atomic layer deposition (ALD) for semiconductor applications presented by researchers from the Fraunhofer Institute for Photonic Microsystems. It discusses the history of ALD deposition of high-k materials like TiO2 and laminates of Ta2O5 and HfO2 for capacitor applications in the 1990s. It also summarizes the development of TiN/ZrO2-based capacitors and research on ALD HfO2 for emerging ferroelectric memory devices. Finally, it discusses the fabrication of 3D capacitor structures using ALD with densities over 250 nF/mm2 and possibilities for 3D integration of ferroelectric HfO2
1. The document describes the key steps in the manufacturing process for computer chips, including transforming silicon ingots into wafers and fabricating transistors on the wafers through photolithography, etching, ion implantation, and other processes.
2. It provides illustrations at the scale of an entire 300mm wafer and also zoomed in to the individual transistor level to show how features are patterned down to 50-200nm in size.
3. The process involves hundreds of precise steps to create layered structures through techniques like thermal oxidation, deposition of materials like silicon dioxide and polysilicon, and selective removal of portions by etching.
Predicting Reliability of Zero Level Through Silicon Vias (TSV)Greg Caswell
Through-silicon vias (TSVs) offer advantages like thinner packages and greater integration, but reliability challenges remain. The three primary failure mechanisms are cracking of copper plating within the TSV, cracking of silicon due to stress from thermal expansion mismatches, and delamination at interfaces between TSV walls and silicon. Interfacial delamination is considered the most likely failure mode due to complex stresses and difficult-to-measure material properties at interfaces. While predicting TSV reliability is challenging with limited test data, lessons from fiber-reinforced composites can provide relevant insights on improving interfacial reliability.
This document discusses electrostatic discharge (ESD) protection in integrated circuits. It introduces ESD, outlines common ESD models like the human body model and machine model, and describes key ESD protection mechanisms such as avalanche breakdown and thermal breakdown in nMOS transistors. These protection mechanisms allow ESD protection devices to safely discharge static electricity through controlled conduction paths before thermal damage occurs.
This standard defines methods for calculating the early life failure rate of a product, using accelerated
testing, whose failure rate is constant or decreasing over time. For technologies where there is adequate
field failure data, alternative methods may be used to establish the early life failure rate.
The purpose of this standard is to define a procedure for performing measurement and calculation of early
life failure rates. Projections can be used to compare reliability performance with objectives, provide line
feedback, support service cost estimates, and set product test and screen strategies to ensure that the
Early life Failure Rate meets customers' requirements.
1.2V core power clamp for TSMC 65nm technologySofics
Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 5nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 4500 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.
The ESD clamp described in this document protects 1.2V core domains in TSMC 65nm CMOS technology.
Este documento describe un amplificador estéreo de 200W (100W por canal) ideal para videorockolas. Incluye una lista de materiales, diagramas esquemáticos, circuito impreso y posición de componentes para construir el amplificador, el cual puede funcionar con una carga de 4 u 8 ohmios utilizando un ventilador adicional en este último caso.
What is the IPC-JSTD-001 Certification ProgramBob Wettermann
This slide set is a high level overview of the IPC J-STD-001 certification and training program. It is designed to give you a high level overview of this soldering and PCB assembly specification certification training program.
SiP technology can provide small form factors, low costs, and multi-function integration solutions. Some key technologies need to be developed to realize these benefits, including EMI shielding partitioning, antenna integration on PCBs, die placement on passive components, and integrating intellectual property cores directly into PCBs. Fan-out wafer level packaging and fan-out package-on-package technologies allow for thinner packages and high I/O routing densities at fine line/space pitches. Challenges include lithography control at sub-2 micron resolutions, high-density bump cleaning, and thin wafer warpage control.
Wafer dicing is the process of separating microelectronic devices on a wafer after processing. It involves scribing or cutting the wafer into individual chips using sawing, breaking, laser cutting, or plasma dicing. The chips are then packaged for use in electronic devices. Wafers are very pure slices of semiconductor material, such as silicon, that serve as substrates for microelectronic circuits. During wafer processing, silicon crystals are grown into cylinders and sliced into thin disks called wafers which undergo polishing, testing, and various processing steps to produce complete electrical circuits.
This document discusses trends in the IC packaging industry and technology. It provides an overview of the market growth in IC packaging units and revenues. Key challenges for the industry are declining ASPs and increasing materials costs. Emerging technologies discussed include wafer-level packaging, 2.5D/3D IC with TSV, and integrated passives. The document outlines SPIL's packaging portfolio and roadmaps for 3D IC and TSV development over the next few years. It also summarizes SPIL's testing and certification capabilities.
Pad design and process for voiding control at QFN assemblynclee715
The document summarizes a study on pad design and process parameters to minimize voiding during QFN assembly. Key findings include: (1) Dividing large thermal pads into sub-units significantly reduces the largest voids while modestly increasing discontinuity; (2) Placing thermal vias peripherally or plugging vias is important when via number is high to control voiding; (3) Increased venting accessibility via sub-pad shape/number reduces voiding but compromises joint continuity.
The document discusses value investing in India. It notes that India offers strong macroeconomic resilience and earnings growth potential across sectors like infrastructure, IT, auto and pharma. Value investing involves buying stocks at a discount to their intrinsic value with a long-term hold strategy. The strategy aims to benefit from compound returns by investing in high-quality businesses trading at attractive valuations. It uses a bottom-up approach focusing on companies with strong returns on capital and trading at a margin of safety. The strategy constructs a concentrated portfolio of 15-20 stocks following strict buy price discipline.
How An Advertiser and Agency
See The Future of Advertising in Print and Online
Fabrice Dekerf,
Managing Director,
Germaine, Belgium
INMA, Krakau,
September 30th 2010
Direct Bond Interconnect (DBI) Technology as an Alternative to Thermal Compre...Invensas
DBI® is a low temperature hybrid direct bonding technology that allows wafers or die to be bonded with exceptionally fine pitch 3D electrical interconnect.
The document provides an overview of the history and evolution of semiconductors and integrated circuits from 1947 to present. It discusses key inventions and milestones such as the transistor in 1947, the integrated circuit in 1961, and Moore's Law predicting transistor doubling every two years. It also covers different chip design approaches including full custom, standard cell, gate arrays, and FPGAs, along with their relative costs, performance, and design complexities.
Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and Fin...Sofics
Sofics presentation (B2.2) at the 1st International EOS/ESD Symposium on Design and System (IEDS). IEDS is dedicated to the fundamental understanding of issues related to electrostatic discharge on design and system and the application of this knowledge to the solution of problems.
Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
1) 3D IC designs stack multiple silicon dies on top of each other using through-silicon vias (TSVs) to connect the dies. This overcomes limitations of conventional 2D designs like Moore's law.
2) Key advantages of 3D IC include higher density, performance and lower power consumption from shorter interconnects. It also enables heterogeneous integration and improves reliability.
3) Challenges include developing 3D transistor architectures, managing variability and thermal issues across stacked dies, and ensuring design and manufacturing tools are ready to support 3D IC. Major applications are seen in memory, imaging sensors and processors.
HIGH-K DEVICES BY ALD FOR SEMICONDUCTOR APPLICATIONSJonas Sundqvist
This document summarizes research on high-k dielectric devices fabricated using atomic layer deposition (ALD) for semiconductor applications presented by researchers from the Fraunhofer Institute for Photonic Microsystems. It discusses the history of ALD deposition of high-k materials like TiO2 and laminates of Ta2O5 and HfO2 for capacitor applications in the 1990s. It also summarizes the development of TiN/ZrO2-based capacitors and research on ALD HfO2 for emerging ferroelectric memory devices. Finally, it discusses the fabrication of 3D capacitor structures using ALD with densities over 250 nF/mm2 and possibilities for 3D integration of ferroelectric HfO2
1. The document describes the key steps in the manufacturing process for computer chips, including transforming silicon ingots into wafers and fabricating transistors on the wafers through photolithography, etching, ion implantation, and other processes.
2. It provides illustrations at the scale of an entire 300mm wafer and also zoomed in to the individual transistor level to show how features are patterned down to 50-200nm in size.
3. The process involves hundreds of precise steps to create layered structures through techniques like thermal oxidation, deposition of materials like silicon dioxide and polysilicon, and selective removal of portions by etching.
Predicting Reliability of Zero Level Through Silicon Vias (TSV)Greg Caswell
Through-silicon vias (TSVs) offer advantages like thinner packages and greater integration, but reliability challenges remain. The three primary failure mechanisms are cracking of copper plating within the TSV, cracking of silicon due to stress from thermal expansion mismatches, and delamination at interfaces between TSV walls and silicon. Interfacial delamination is considered the most likely failure mode due to complex stresses and difficult-to-measure material properties at interfaces. While predicting TSV reliability is challenging with limited test data, lessons from fiber-reinforced composites can provide relevant insights on improving interfacial reliability.
This document discusses electrostatic discharge (ESD) protection in integrated circuits. It introduces ESD, outlines common ESD models like the human body model and machine model, and describes key ESD protection mechanisms such as avalanche breakdown and thermal breakdown in nMOS transistors. These protection mechanisms allow ESD protection devices to safely discharge static electricity through controlled conduction paths before thermal damage occurs.
This standard defines methods for calculating the early life failure rate of a product, using accelerated
testing, whose failure rate is constant or decreasing over time. For technologies where there is adequate
field failure data, alternative methods may be used to establish the early life failure rate.
The purpose of this standard is to define a procedure for performing measurement and calculation of early
life failure rates. Projections can be used to compare reliability performance with objectives, provide line
feedback, support service cost estimates, and set product test and screen strategies to ensure that the
Early life Failure Rate meets customers' requirements.
1.2V core power clamp for TSMC 65nm technologySofics
Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 5nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 4500 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.
The ESD clamp described in this document protects 1.2V core domains in TSMC 65nm CMOS technology.
Este documento describe un amplificador estéreo de 200W (100W por canal) ideal para videorockolas. Incluye una lista de materiales, diagramas esquemáticos, circuito impreso y posición de componentes para construir el amplificador, el cual puede funcionar con una carga de 4 u 8 ohmios utilizando un ventilador adicional en este último caso.
What is the IPC-JSTD-001 Certification ProgramBob Wettermann
This slide set is a high level overview of the IPC J-STD-001 certification and training program. It is designed to give you a high level overview of this soldering and PCB assembly specification certification training program.
SiP technology can provide small form factors, low costs, and multi-function integration solutions. Some key technologies need to be developed to realize these benefits, including EMI shielding partitioning, antenna integration on PCBs, die placement on passive components, and integrating intellectual property cores directly into PCBs. Fan-out wafer level packaging and fan-out package-on-package technologies allow for thinner packages and high I/O routing densities at fine line/space pitches. Challenges include lithography control at sub-2 micron resolutions, high-density bump cleaning, and thin wafer warpage control.
Wafer dicing is the process of separating microelectronic devices on a wafer after processing. It involves scribing or cutting the wafer into individual chips using sawing, breaking, laser cutting, or plasma dicing. The chips are then packaged for use in electronic devices. Wafers are very pure slices of semiconductor material, such as silicon, that serve as substrates for microelectronic circuits. During wafer processing, silicon crystals are grown into cylinders and sliced into thin disks called wafers which undergo polishing, testing, and various processing steps to produce complete electrical circuits.
This document discusses trends in the IC packaging industry and technology. It provides an overview of the market growth in IC packaging units and revenues. Key challenges for the industry are declining ASPs and increasing materials costs. Emerging technologies discussed include wafer-level packaging, 2.5D/3D IC with TSV, and integrated passives. The document outlines SPIL's packaging portfolio and roadmaps for 3D IC and TSV development over the next few years. It also summarizes SPIL's testing and certification capabilities.
Pad design and process for voiding control at QFN assemblynclee715
The document summarizes a study on pad design and process parameters to minimize voiding during QFN assembly. Key findings include: (1) Dividing large thermal pads into sub-units significantly reduces the largest voids while modestly increasing discontinuity; (2) Placing thermal vias peripherally or plugging vias is important when via number is high to control voiding; (3) Increased venting accessibility via sub-pad shape/number reduces voiding but compromises joint continuity.
The document discusses value investing in India. It notes that India offers strong macroeconomic resilience and earnings growth potential across sectors like infrastructure, IT, auto and pharma. Value investing involves buying stocks at a discount to their intrinsic value with a long-term hold strategy. The strategy aims to benefit from compound returns by investing in high-quality businesses trading at attractive valuations. It uses a bottom-up approach focusing on companies with strong returns on capital and trading at a margin of safety. The strategy constructs a concentrated portfolio of 15-20 stocks following strict buy price discipline.
How An Advertiser and Agency
See The Future of Advertising in Print and Online
Fabrice Dekerf,
Managing Director,
Germaine, Belgium
INMA, Krakau,
September 30th 2010
Passive mobile measurement: The next big thing in market research? - TNSMerlien Institute
Presented by James Fergusson, Managing Director, Global Technology Sector - TNS
& Remy Bleijendaa, Digital Consultant, TNS
at Market Research in the Mobile World Asia-Pacific
30-31 January 2013, Kuala Lumpur, Malaysia
This event is proudly organised by Merlien Institute
Check out our upcoming events by visiting http://www.mrmw.net
Assessing color reproduction tolerances in commercial print workflowGiordano Beretta
The document summarizes research on assessing color reproduction tolerances in commercial print workflows. It discusses challenges with ICC profiles, the need for more useful print quality metrics than average ΔE values, preserving color integrity rather than strict color fidelity, and exploring the potential use of the Farnsworth-Munsell 100-hue test to assess color reproduction systems in the same way it is used to test human color discrimination. The research aims to better understand print quality and develop simplified methods for evaluating color reproduction accuracy in commercial print workflows.
1) iPhone users are more likely to download paid smartphone applications compared to other smartphone users. Android and iPhone users show strong brand loyalty, with over 90% likely to repurchase their brand.
2) Android and iPhone users primarily use their smartphones for both personal and business purposes, while over 75% of Blackberry users use their device for both purposes.
3) Around half of Blackberry and other smartphone users would recommend the iPhone to friends and family, while about a third would recommend Android. Android and iPhone users are much more likely to recommend their own brands.
Smaato is a mobile advertising platform that matches ads from over 80 ad networks to mobile app and website inventory from over 55,000 publishers. It aims to provide the highest eCPMs and fill rates for publishers through its optimization technology. The company has seen strong growth, raising $20M in funding and increasing its staff and revenue significantly since being founded in 2005. It now processes billions of ad requests per month globally.
The document discusses LinkedIn's Q2 2012 results and provides forward-looking statements and risks. It reports key metrics such as member and revenue growth. The CEO and CFO then discuss the results and metrics. The document also provides a safe harbor statement, noting the forward-looking statements involve risks and uncertainties that could impact the company's actual results.
Nepal is transitioning from a rural to urban economy and has a literacy rate of 68.2%. Agriculture accounts for about 40% of GDP and 80% of the population derives their livelihood from it. Technology is viewed as a means to increase productivity by combining resources. Nepal's industrial sector relies on imported and low grade technologies with little focus on R&D. Exports are mainly raw materials and skill development lags requirements. Technology transfer occurs through foreign investment but the scale of projects is generally small. Information technology is increasing access to education and tourism information but remains limited outside urban areas.
Outsourcing AP can reduce costs, but can it improve your service delivery too?sharedserviceslink.com
AstraZeneca outsourced their accounts payable process to reduce costs and improve service delivery. They transitioned from local processing units to a shared services model with Genpact over 2.5 years. This centralized the complex AP operating model and improved key metrics like cost per invoice processed, payment on time rates, and customer service ratings. While the initial focus was on cost savings and stability, AstraZeneca aims to further transform the process through standardization, technology exploitation, and continuous improvement culture.
eCMO 2010 Digital lifestyles and media consumption habits of four generations...HKAIM
This document provides an overview of media consumption habits across four generations in Hong Kong based on survey data. Younger generations, especially those born post-1990, are highly engaged with digital media like the internet and smartphones. They use social media frequently and see the web as an important source of entertainment and information. Older generations still rely more on traditional media like television and newspapers. The data suggests media usage varies significantly between age groups and generations in Hong Kong.
The document summarizes the global financial crisis and its impacts. It discusses how the subprime mortgage crisis in the US triggered a global crisis through interconnected financial markets and declining trade. The crisis led to a sharp decline in global GDP growth. It discusses policy responses by countries through fiscal stimulus and efforts to stabilize financial systems. It emphasizes the need for coordinated global action on financial regulation, trade, and addressing poverty and environmental impacts. Lessons from past financial crises are outlined around the importance of rapid and sizable responses, social protection policies, and balancing national and global goals.
This is a presentation based on 5 years activities of a Business Angel Club founded by alumni of the Swiss Federal Insitute of Technology, EPFL. Presented at a panel with INSEAD alumni sharing experiences with successful entrepreneurs Kelly Richdale IDQ, Martin Velasco Anecova , Pedro Bados Nexthink, Marco Boella - Lemotpics with assistance of Colin Turner Greentek ventures
GlobalLogic Java Community Webinar #18 “How to Improve Web Application Perfor...GlobalLogic Ukraine
Під час доповіді відповімо на питання, навіщо потрібно підвищувати продуктивність аплікації і які є найефективніші способи для цього. А також поговоримо про те, що таке кеш, які його види бувають та, основне — як знайти performance bottleneck?
Відео та деталі заходу: https://bit.ly/45tILxj
[OReilly Superstream] Occupy the Space: A grassroots guide to engineering (an...Jason Yip
The typical problem in product engineering is not bad strategy, so much as “no strategy”. This leads to confusion, lack of motivation, and incoherent action. The next time you look for a strategy and find an empty space, instead of waiting for it to be filled, I will show you how to fill it in yourself. If you’re wrong, it forces a correction. If you’re right, it helps create focus. I’ll share how I’ve approached this in the past, both what works and lessons for what didn’t work so well.
"NATO Hackathon Winner: AI-Powered Drug Search", Taras KlobaFwdays
This is a session that details how PostgreSQL's features and Azure AI Services can be effectively used to significantly enhance the search functionality in any application.
In this session, we'll share insights on how we used PostgreSQL to facilitate precise searches across multiple fields in our mobile application. The techniques include using LIKE and ILIKE operators and integrating a trigram-based search to handle potential misspellings, thereby increasing the search accuracy.
We'll also discuss how the azure_ai extension on PostgreSQL databases in Azure and Azure AI Services were utilized to create vectors from user input, a feature beneficial when users wish to find specific items based on text prompts. While our application's case study involves a drug search, the techniques and principles shared in this session can be adapted to improve search functionality in a wide range of applications. Join us to learn how PostgreSQL and Azure AI can be harnessed to enhance your application's search capability.
Getting the Most Out of ScyllaDB Monitoring: ShareChat's TipsScyllaDB
ScyllaDB monitoring provides a lot of useful information. But sometimes it’s not easy to find the root of the problem if something is wrong or even estimate the remaining capacity by the load on the cluster. This talk shares our team's practical tips on: 1) How to find the root of the problem by metrics if ScyllaDB is slow 2) How to interpret the load and plan capacity for the future 3) Compaction strategies and how to choose the right one 4) Important metrics which aren’t available in the default monitoring setup.
QA or the Highway - Component Testing: Bridging the gap between frontend appl...zjhamm304
These are the slides for the presentation, "Component Testing: Bridging the gap between frontend applications" that was presented at QA or the Highway 2024 in Columbus, OH by Zachary Hamm.
Conversational agents, or chatbots, are increasingly used to access all sorts of services using natural language. While open-domain chatbots - like ChatGPT - can converse on any topic, task-oriented chatbots - the focus of this paper - are designed for specific tasks, like booking a flight, obtaining customer support, or setting an appointment. Like any other software, task-oriented chatbots need to be properly tested, usually by defining and executing test scenarios (i.e., sequences of user-chatbot interactions). However, there is currently a lack of methods to quantify the completeness and strength of such test scenarios, which can lead to low-quality tests, and hence to buggy chatbots.
To fill this gap, we propose adapting mutation testing (MuT) for task-oriented chatbots. To this end, we introduce a set of mutation operators that emulate faults in chatbot designs, an architecture that enables MuT on chatbots built using heterogeneous technologies, and a practical realisation as an Eclipse plugin. Moreover, we evaluate the applicability, effectiveness and efficiency of our approach on open-source chatbots, with promising results.
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Keywords: AI, Containeres, Kubernetes, Cloud Native
Event Link: https://meine.doag.org/events/cloudland/2024/agenda/#agendaId.4211
Must Know Postgres Extension for DBA and Developer during MigrationMydbops
Mydbops Opensource Database Meetup 16
Topic: Must-Know PostgreSQL Extensions for Developers and DBAs During Migration
Speaker: Deepak Mahto, Founder of DataCloudGaze Consulting
Date & Time: 8th June | 10 AM - 1 PM IST
Venue: Bangalore International Centre, Bangalore
Abstract: Discover how PostgreSQL extensions can be your secret weapon! This talk explores how key extensions enhance database capabilities and streamline the migration process for users moving from other relational databases like Oracle.
Key Takeaways:
* Learn about crucial extensions like oracle_fdw, pgtt, and pg_audit that ease migration complexities.
* Gain valuable strategies for implementing these extensions in PostgreSQL to achieve license freedom.
* Discover how these key extensions can empower both developers and DBAs during the migration process.
* Don't miss this chance to gain practical knowledge from an industry expert and stay updated on the latest open-source database trends.
Mydbops Managed Services specializes in taking the pain out of database management while optimizing performance. Since 2015, we have been providing top-notch support and assistance for the top three open-source databases: MySQL, MongoDB, and PostgreSQL.
Our team offers a wide range of services, including assistance, support, consulting, 24/7 operations, and expertise in all relevant technologies. We help organizations improve their database's performance, scalability, efficiency, and availability.
Contact us: info@mydbops.com
Visit: https://www.mydbops.com/
Follow us on LinkedIn: https://in.linkedin.com/company/mydbops
For more details and updates, please follow up the below links.
Meetup Page : https://www.meetup.com/mydbops-databa...
Twitter: https://twitter.com/mydbopsofficial
Blogs: https://www.mydbops.com/blog/
Facebook(Meta): https://www.facebook.com/mydbops/
In our second session, we shall learn all about the main features and fundamentals of UiPath Studio that enable us to use the building blocks for any automation project.
📕 Detailed agenda:
Variables and Datatypes
Workflow Layouts
Arguments
Control Flows and Loops
Conditional Statements
💻 Extra training through UiPath Academy:
Variables, Constants, and Arguments in Studio
Control Flow in Studio
The Department of Veteran Affairs (VA) invited Taylor Paschal, Knowledge & Information Management Consultant at Enterprise Knowledge, to speak at a Knowledge Management Lunch and Learn hosted on June 12, 2024. All Office of Administration staff were invited to attend and received professional development credit for participating in the voluntary event.
The objectives of the Lunch and Learn presentation were to:
- Review what KM ‘is’ and ‘isn’t’
- Understand the value of KM and the benefits of engaging
- Define and reflect on your “what’s in it for me?”
- Share actionable ways you can participate in Knowledge - - Capture & Transfer
"What does it really mean for your system to be available, or how to define w...Fwdays
We will talk about system monitoring from a few different angles. We will start by covering the basics, then discuss SLOs, how to define them, and why understanding the business well is crucial for success in this exercise.
"Choosing proper type of scaling", Olena SyrotaFwdays
Imagine an IoT processing system that is already quite mature and production-ready and for which client coverage is growing and scaling and performance aspects are life and death questions. The system has Redis, MongoDB, and stream processing based on ksqldb. In this talk, firstly, we will analyze scaling approaches and then select the proper ones for our system.
MySQL InnoDB Storage Engine: Deep Dive - MydbopsMydbops
This presentation, titled "MySQL - InnoDB" and delivered by Mayank Prasad at the Mydbops Open Source Database Meetup 16 on June 8th, 2024, covers dynamic configuration of REDO logs and instant ADD/DROP columns in InnoDB.
This presentation dives deep into the world of InnoDB, exploring two ground-breaking features introduced in MySQL 8.0:
• Dynamic Configuration of REDO Logs: Enhance your database's performance and flexibility with on-the-fly adjustments to REDO log capacity. Unleash the power of the snake metaphor to visualize how InnoDB manages REDO log files.
• Instant ADD/DROP Columns: Say goodbye to costly table rebuilds! This presentation unveils how InnoDB now enables seamless addition and removal of columns without compromising data integrity or incurring downtime.
Key Learnings:
• Grasp the concept of REDO logs and their significance in InnoDB's transaction management.
• Discover the advantages of dynamic REDO log configuration and how to leverage it for optimal performance.
• Understand the inner workings of instant ADD/DROP columns and their impact on database operations.
• Gain valuable insights into the row versioning mechanism that empowers instant column modifications.
Essentials of Automations: Exploring Attributes & Automation ParametersSafe Software
Building automations in FME Flow can save time, money, and help businesses scale by eliminating data silos and providing data to stakeholders in real-time. One essential component to orchestrating complex automations is the use of attributes & automation parameters (both formerly known as “keys”). In fact, it’s unlikely you’ll ever build an Automation without using these components, but what exactly are they?
Attributes & automation parameters enable the automation author to pass data values from one automation component to the next. During this webinar, our FME Flow Specialists will cover leveraging the three types of these output attributes & parameters in FME Flow: Event, Custom, and Automation. As a bonus, they’ll also be making use of the Split-Merge Block functionality.
You’ll leave this webinar with a better understanding of how to maximize the potential of automations by making use of attributes & automation parameters, with the ultimate goal of setting your enterprise integration workflows up on autopilot.
inQuba Webinar Mastering Customer Journey Management with Dr Graham HillLizaNolte
HERE IS YOUR WEBINAR CONTENT! 'Mastering Customer Journey Management with Dr. Graham Hill'. We hope you find the webinar recording both insightful and enjoyable.
In this webinar, we explored essential aspects of Customer Journey Management and personalization. Here’s a summary of the key insights and topics discussed:
Key Takeaways:
Understanding the Customer Journey: Dr. Hill emphasized the importance of mapping and understanding the complete customer journey to identify touchpoints and opportunities for improvement.
Personalization Strategies: We discussed how to leverage data and insights to create personalized experiences that resonate with customers.
Technology Integration: Insights were shared on how inQuba’s advanced technology can streamline customer interactions and drive operational efficiency.
"Scaling RAG Applications to serve millions of users", Kevin GoedeckeFwdays
How we managed to grow and scale a RAG application from zero to thousands of users in 7 months. Lessons from technical challenges around managing high load for LLMs, RAGs and Vector databases.
8. IMEC IN THE WORLD
The Netherlands
Belgium
China
office US office Japan
Taiwan
India
9. Organic
Silicon solar cell
200mm line NERF
solar cell lab
pilot line
line
Nano 300mm
biolabs pilot line
450mm
ready
STATE-OF-THE-ART
RESEARCH FACILITIES
10. 300mm PILOT LINE
IMEC TOWER
‣ Expansion of 14,208 m2
14 208
‣ 16 floors – capacity of 450 people & lab space
11. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
29. GLOBAL NETWORK
SYSTEM COMPANIES
MEMORY IDM LOGIC IDM FOUNDRIES FABLITE FABLESS
EQUIPMENT MATERIAL SOFTWARE
SUPPLIERS SUPPLIERS SUPPLIERS
30. GLOBAL NETWORK
Memory IDM Logic IDM Foundries Fablite Fabless
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31. CORE CMOS PARTNERS
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Lam
RESEARCH
32. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
51. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
58. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
66. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
72. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
90. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
96. RESEARCH PROGRAMS FOR FULL ECO SYSTEM
Human++ Green Radio Imaging Sensor Energy
BAN Low power Image sensors systems Photovoltaics
Life Sciences wireless & vision systems for industrial Power devices
communication applications LEDs
Core CMOS CMORE Organic
Lithography Devices Interconnects MEMS, Sensor electronics
Photonics
104. RESEARCH PROGRAMS
FOR FULL INDUSTRY ECO SYSTEM
Memory IDM Logic IDM Foundries Fablite Fabless
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and then insert it again.
110. LEVERAGE TO FLANDERS
With a dedicated team
stimulating, initiating &
coordinating cooperation
with Flemish companies &
innovation actors
Exploration, transfer &
consolidation in Flanders
Worldwide industrial network
of top companies
Build-up
Build up of technology portfolio in generic R&D Programs
111. COOPERATION WITH
LOCAL COMPANIES / ACTORS
Timely insight Participation in
and inputs for LT/MT/ST
LT research researchh
1 few
Sharing Focussed added value Application of
pp
technological
research results
know-how
Cooperation with Support for
Informing about
development of
technological local new products
d
opportunities companies/actors and processes
1 many 1 1
Low threshold High threshold
Generic added value Specific added value
112. EXPANSION MODEL:
MICROELECTRONICS FOR BENEFIT OF OTHER SECTORS
Textile Automotive
Biomedic Food
al
Electronic Design Construction Health & Wellness
113. IMEC’S IMPACT ON THE LOCAL INDUSTRY
EVOLUTION COLLABORATION LOCAL COMPANIES
600
1984 2001:
500
142 local companies 486
464
2002 2011: 447
344 extra local companies, 411
400 >60% SME’s! 381
350
306
300
261
222
200 166
142
127
102 110
86
100 74
57
45
26 32
0
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
116. COOPERATION IN DIFFERENT SECTORS 2011
WITH LOCAL COMPANIES
22%
34% Microelectronics
Non-ICT
Textile
Automotive
Medical
Food
Graphics
Wellness 26%
Health
H lth
Chemical 18%
Electronic prod.
Construction ICT (others)
Domotics