Wide Band Frequency Synthesizer has become essential components in wireless communication
systems. They are used as frequency synthesizers with precise and convenient digital control in both traditional
electronics, such as televisions and AM/FM radios, and modern consumer products among which cellular
mobile phone is a striking example.
IC fabrication technology advances have made monolithic integration possible. More and more
electronic devices can be put on the same chip to reduce the number of external components and then the costs.
Therefore, on a single chip we can accomplish many functions for which we might need to make several chips
work together a few years ago. A monolithic wide-band PLL is of great interests to wireless communication
applications due to both its low cost and convenience to switch between different communication standards.
The focus of this work is to implement a wide-band Frequency Synthesizer using as few as possible building
blocks and also as simple as possible structure.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Implementation of Algorithms For Multi-Channel Digital Monitoring ReceiverIOSR Journals
Abstract: Monitoring Receivers form an important constituent of the Electronic support. In Monitoring
Receiver we can monitor, demodulate or scan the multiple channels.
In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The
implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital
Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to
Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs.
Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to
the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the
implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf)
development board. Xilinx System Generator will be used for the implementation of the algorithms.
Keywords: DDC, ADC, Digital Base band demodulation, IF, Monitoring Receiver.
A novel fast time jamming analysis transmission selection technique for radar...IJECEIAES
The jamming analysis transmission selection (JATS) sub-system is used in radar systems to detect and avoid the jammed frequencies in the available operating bandwidth during signal transmission and reception. The available time to measure the desired frequency spectrum and select the non-jammed frequency for transmission is very limited. A novel fast time (FAT) technique that measures the channel spectrum, detects the jamming sub-band and selects the non-jammed frequency for radar system transmission in real time is proposed. A JATS sub-system has been designed, simulated, fabricated and implemented based on FAT technique to verify the idea. The novel FAT technique utilizes time-domain analysis instead of the wellknown fast Fourier transform (FFT) used in conventional JATS sub-systems. Therefore, the proposed fast time jamming analysis transmission selection (FAT-JATS) sub-system outperforms other reported JATS sub-systems as it uses less FPGA resources, avoids time-delay occurred due to complex FFT calculations and enhances the real time operation. This makes the proposed technique an excellent candidate for JATS sub-systems.
FPGA Based Power Efficient Chanalizer For Software Defined RadioIJMER
Multiple communication channel support in RF transmission, such as that in a Software Defined Radio (SDR) warrants the use of channelizers to extract required channels from the received RF frequency band and to perform follow-on baseband processing. This paper describes the process of channelization as it applies to low power and high-efficiency applications in wireless and Satellite Communications (SATCOM) domains. Smaller bandwidths and changing requirements of bandwidth calls for a programmable channel selection mechanism whereby channels and the resulting bandwidth can be selected based on target application, which is the primary principle in the Software Defined Radio based systems.
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
Software Defined Radio Engineering course samplerJim Jenkins
This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.
A Simulation of Wideband CDMA System on Digital Up/Down ConvertersEditor IJMTER
In this paper, I present FPGA implementation of a digital down converter (DDC) and
digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in
nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx
System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the
circuits are verified on the Spartan - 3 FPGA
Matlab Based Decimeter Design Analysis Wimax Appliacationiosrjce
A Digital down Converter (DDC), which is basically used to convert an intermediate frequency (IF)
signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC
constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, We can
comparison of two window and see the costs of all Window filters
Wavelet Based Analysis of Online Monitoring of Electrical Power by Mobile Tec...IJMER
Electrical automation is an important option for obtaining optimal solution while monitoring the electrical power consumption. While using the conventional methods the errors in continuous monitoring of power consumption is more. But the system requires not only the monitoring of the energy but also requires the analysis of the monitored energy. In this paper wavelet analysis is used for the analysis of the monitored energy/power which is monitored by GPRS technology. By using the GPRS mobile technology the energy consumption is monitored continuously and the observed data is interfaced to the computer by RS 232 port. By using MATLAB the monitored data is processed to obtain in depth analysis of the monitored power. The proposed method not only monitors the data but also provides efficient means to analyze the observed data by Wavelet Transform
A Study on Mathematical Statistics to Evaluate Relationship between AttributesIJMER
The goodness of fit of a statistical model describes how well it fits a set of observations. Measures of
goodness of fit typically summarize the discrepancy between observed values and the values expected under the
model in question. Such measures can be used in statistical hypothesis testing, e.g. to test for normality of
residuals, to test whether two samples are drawn from identical distributions (see Kolmogorov–Smirnov test), or
whether outcome frequencies follow a specified distribution (see Pearson's chi-squared test).
In this paper, we give several new fixed point theorems to extend results [3]-[4] ,and we apply
the effective modification of He’s variation iteration method to solve some nonlinear and linear equations are
proceed to examine some a class of integral-differential equations and some partial differential equation, to
illustrate the effectiveness and convenience of this method(see[7]). Finally we have also discussed Berge type
equation with exact solution
A novel fast time jamming analysis transmission selection technique for radar...IJECEIAES
The jamming analysis transmission selection (JATS) sub-system is used in radar systems to detect and avoid the jammed frequencies in the available operating bandwidth during signal transmission and reception. The available time to measure the desired frequency spectrum and select the non-jammed frequency for transmission is very limited. A novel fast time (FAT) technique that measures the channel spectrum, detects the jamming sub-band and selects the non-jammed frequency for radar system transmission in real time is proposed. A JATS sub-system has been designed, simulated, fabricated and implemented based on FAT technique to verify the idea. The novel FAT technique utilizes time-domain analysis instead of the wellknown fast Fourier transform (FFT) used in conventional JATS sub-systems. Therefore, the proposed fast time jamming analysis transmission selection (FAT-JATS) sub-system outperforms other reported JATS sub-systems as it uses less FPGA resources, avoids time-delay occurred due to complex FFT calculations and enhances the real time operation. This makes the proposed technique an excellent candidate for JATS sub-systems.
FPGA Based Power Efficient Chanalizer For Software Defined RadioIJMER
Multiple communication channel support in RF transmission, such as that in a Software Defined Radio (SDR) warrants the use of channelizers to extract required channels from the received RF frequency band and to perform follow-on baseband processing. This paper describes the process of channelization as it applies to low power and high-efficiency applications in wireless and Satellite Communications (SATCOM) domains. Smaller bandwidths and changing requirements of bandwidth calls for a programmable channel selection mechanism whereby channels and the resulting bandwidth can be selected based on target application, which is the primary principle in the Software Defined Radio based systems.
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
Software Defined Radio Engineering course samplerJim Jenkins
This 3-day course is designed for digital signal processing engineers, RF system engineers, and managers who wish to enhance their understanding of this rapidly emerging technology. Most topics include carefully described design analysis, alternative approaches, performance analysis, and references to published research results. Many topics are illustrated by Matlab simulation demos. An extensive bibliography is included.
A Simulation of Wideband CDMA System on Digital Up/Down ConvertersEditor IJMTER
In this paper, I present FPGA implementation of a digital down converter (DDC) and
digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in
nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx
System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the
circuits are verified on the Spartan - 3 FPGA
Matlab Based Decimeter Design Analysis Wimax Appliacationiosrjce
A Digital down Converter (DDC), which is basically used to convert an intermediate frequency (IF)
signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC
constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, We can
comparison of two window and see the costs of all Window filters
Wavelet Based Analysis of Online Monitoring of Electrical Power by Mobile Tec...IJMER
Electrical automation is an important option for obtaining optimal solution while monitoring the electrical power consumption. While using the conventional methods the errors in continuous monitoring of power consumption is more. But the system requires not only the monitoring of the energy but also requires the analysis of the monitored energy. In this paper wavelet analysis is used for the analysis of the monitored energy/power which is monitored by GPRS technology. By using the GPRS mobile technology the energy consumption is monitored continuously and the observed data is interfaced to the computer by RS 232 port. By using MATLAB the monitored data is processed to obtain in depth analysis of the monitored power. The proposed method not only monitors the data but also provides efficient means to analyze the observed data by Wavelet Transform
A Study on Mathematical Statistics to Evaluate Relationship between AttributesIJMER
The goodness of fit of a statistical model describes how well it fits a set of observations. Measures of
goodness of fit typically summarize the discrepancy between observed values and the values expected under the
model in question. Such measures can be used in statistical hypothesis testing, e.g. to test for normality of
residuals, to test whether two samples are drawn from identical distributions (see Kolmogorov–Smirnov test), or
whether outcome frequencies follow a specified distribution (see Pearson's chi-squared test).
In this paper, we give several new fixed point theorems to extend results [3]-[4] ,and we apply
the effective modification of He’s variation iteration method to solve some nonlinear and linear equations are
proceed to examine some a class of integral-differential equations and some partial differential equation, to
illustrate the effectiveness and convenience of this method(see[7]). Finally we have also discussed Berge type
equation with exact solution
Network Forensic Investigation of HTTPS ProtocolIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
: The main objective of this paper is the systematic description of the current research and
development of small or miniature unmanned aerial vehicles and micro aerial vehicles, with a focus on
rotary wing vehicles. In recent times, unmanned/Micro aerial vehicles have been operated across the
world; they have also been the subject of considerable research. In particular, UAVs/MAVs with rotary
wings have been expected to perform various tasks such as monitoring at fixed points and surveillance
from the sky since they can perform not only perform static flights by hovering but also achieve vertical
takeoffs and landing. Helicopters have been used for personnel transport, carrying goods, spreading
information, and performing monitoring duties for long periods. A manned helicopter has to be used for
all these duties. On the other hand, unmanned helicopters that can be operated by radio control have
been developed as a hobby. Since unmanned helicopters are often superior to manned helicopters in
terms of cost and safety, in recent years, accomplishing tasks using unmanned helicopters has become
popular. Considerable expertise is required to operate unmanned helicopters by radio control, and
hence, vast labor resources are employed to train operators. Moreover, it is impossible to operate
unmanned helicopters outside visual areas because of lack of radio control, and the working area is
hence limited remarkably. For solving the above problems, it is necessary to realize autonomous
control of unmanned helicopters. However, no general method for designing the small unmanned
helicopters has been developed yet – today, various design techniques by different study groups using
different helicopters exist. In this paper the conceptual design process is explained.
Multistage interconnection networks (MIN) are among the most efficient switching architectures for the number of switching Element (SE). Optical crosstalk in optical multistage interconnection network on the omega network topology Switches are arranged in multiple stages. These switches also referred to as switching element (SEs) have two input and two output ports, interconnected to the neighboring stages in a shuffle exchange connected pattern message routing in such a network is determined by the interstate connection pattern.
Optical Multistage interconnection networks (OMIN) are advanced version of MINs. The main Problem with OMIN is crosstalk. The main purpose of this paper is to Present crosstalk free modified omega network, which is based on time domain approach. This paper presents the source and destination based Algorithm (SDBA) .SDBA does the scheduling for source and their respective destination addresses for the message routing. SDBA is compared with the crosstalk modified omega network (CFMON).CFMON also Minimizes the crosstalk. This paper is the modified form of the omega network.
Stability of Simply Supported Square Plate with Concentric CutoutIJMER
The finite element method is used to obtain the elastic buckling loads for simply supported isotropic square plate containing circular, square and rectangular cutouts. ANSYS finite element software had been used in the study. The applied inplane loads considered are uniaxial and biaxial compressions. In all the cases the load is distributed uniformly along the plate outer edges. The effects of the size and shape of concentric cutouts with different plate thickness ratios and having all-round simply supported boundary condition on the plate buckling strength have been considered in the analysis. It is found that cutouts have considerable influence on the buckling load factor k and the effect is larger when cutout ratios greater than 0.3 and for thickness ratio greater than 0.15.
Reduction of Topology Control Using Cooperative Communications in ManetsIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Architecture of direct_digital_synthesizanjunarayanan
A frequency synthesizer is an electronic device which generates a range of frequency mostly sine wave from a fixed clock provided. These frequency synthesizers are commonly found in radio receivers, mobile telephones radio telephones, wacky talkies, as local oscillators, satellite receivers, GPS system. Direct digital synthesizer is a frequency synthesizer which digitally creates arbitrary wave forms of different frequencies from the fixed frequency provided as clock input.DDS generates digital wave forms and these digital waveforms are converted to analog signals by the digital to analog converter connected at the output of DDS. The DDS designed here is a ROM based DDS. DDS has many advantages over PLL and other similar approaches such as fast settling time, sub-Hertz frequency resolution, continuous phase switching response and low phase noise. This system has many applications such as the confidential message transfer, speedy frequency switching.
Index terms –DDS-Direct Digital Synthesizer
Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system
The numerically controlled oscillator (NCO) is one of the digital oscillator
signal generators. It can generate the clocked, synchronous, discrete
waveform, and generally sinusoidal. Often NCOs care utilized in the
combinations of digital to analog converter (DAC) at the outputs for creating
direct digital synthesizer (DDS). The network on chips (NOCs) are utilized
in various communication systems that are fully digital or mixed signals
such as synthesis of arbitrary wave, precise control for sonar systems or
phased array radar, digital down/up converters, all the digital phase locked
loops (PLLs) for cellular and personal communication system (PCS) base
stations and drivers for acoustic or optical transmissions and multilevel
phase shift keying/frequency shift keying (PSK/FSK) modulators or
demodulators (modem). The basic architecture of NCO will be enhanced
and improved with less hardware for facilitating complete system level
support to various sorts of modulation with minimum FPGA resources. In
this paper design and memory optimization of hybrid gate diffusion input
(GDI) numerically controlled oscillator based on field programmable gate
array (FPGA) is implemented. compared with NCO based 8-bit microchip,
memory optimization of hybrid GDI numerically controlled oscillator based
on FPGA gives effective outcome in terms of delay, metal-oxidesemiconductor field-effect transistors (MOSFET’s) and nodes.
HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPSVLSICS Design
With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆) converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both
continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Digital Implementation of Costas Loop with Carrier RecoveryIJERD Editor
Demodulator circuit is a basic building block of wireless communication. Digital implementation of
demodulator is attracting more attention for the significant advantages of digital systems than analog systems.
The carrier signal extraction is the main problem in synchronous demodulation in design of demodulator based
on Software Defined Radio. When transmitter or receiver in motion, it is difficult for demodulator to generate
carrier signal same in frequency and phase as transmitter carrier signal due to Doppler shift and Doppler rate.
Here the digital implementation of Costas loop for QPSK demodulation in continuous mode is discussed with
carrier recovery using phase locked loop.
DSM Based low oversampling using SDR transmitterIJTET Journal
The oversampling recruitment is a limiting factor in high frequency application such as software defined radio. This project is a high frequency processing and low oversampling ratio. A single bit semi parallel processing is proposed in this paper. Using this single bit PDSM Architecture, high speed, high complexity computations are executed in parallel. The single bit DSM is to build an RF transmitter that includes a one bit quantifier with two level switching power amplifier for high linearity and high efficiency. Performance analysis by using the MATLAB simulations by reducing the oversampling ratio by same signal to noise ratio. The DSM implemented on field programmable gate array and using a signal code division multiple access signal. This project will give bandwidth of the low oversampled signal increased four times without increasing frequency. Finally they can be achieved signal to noise ratio is very low and also oversampling ratio is small.
Similar to Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer) Controller Using VHDL (20)
A Study on Translucent Concrete Product and Its Properties by Using Optical F...IJMER
- Translucent concrete is a concrete based material with light-transferring properties,
obtained due to embedded light optical elements like Optical fibers used in concrete. Light is conducted
through the concrete from one end to the other. This results into a certain light pattern on the other
surface, depending on the fiber structure. Optical fibers transmit light so effectively that there is
virtually no loss of light conducted through the fibers. This paper deals with the modeling of such
translucent or transparent concrete blocks and panel and their usage and also the advantages it brings
in the field. The main purpose is to use sunlight as a light source to reduce the power consumption of
illumination and to use the optical fiber to sense the stress of structures and also use this concrete as an
architectural purpose of the building
Developing Cost Effective Automation for Cotton Seed DelintingIJMER
A low cost automation system for removal of lint from cottonseed is to be designed and
developed. The setup consists of stainless steel drum with stirrer in which cottonseeds having lint is mixed
with concentrated sulphuric acid. So lint will get burn. This lint free cottonseed treated with lime water to
neutralize acidic nature. After water washing this cottonseeds are used for agriculter purpose
Study & Testing Of Bio-Composite Material Based On Munja FibreIJMER
The incorporation of natural fibres such as munja fiber composites has gained
increasing applications both in many areas of Engineering and Technology. The aim of this study is to
evaluate mechanical properties such as flexural and tensile properties of reinforced epoxy composites.
This is mainly due to their applicable benefits as they are light weight and offer low cost compared to
synthetic fibre composites. Munja fibres recently have been a substitute material in many weight-critical
applications in areas such as aerospace, automotive and other high demanding industrial sectors. In
this study, natural munja fibre composites and munja/fibreglass hybrid composites were fabricated by a
combination of hand lay-up and cold-press methods. A new variety in munja fibre is the present work
the main aim of the work is to extract the neat fibre and is characterized for its flexural characteristics.
The composites are fabricated by reinforcing untreated and treated fibre and are tested for their
mechanical, properties strictly as per ASTM procedures.
Hybrid Engine (Stirling Engine + IC Engine + Electric Motor)IJMER
Hybrid engine is a combination of Stirling engine, IC engine and Electric motor. All these 3 are
connected together to a single shaft. The power source of the Stirling engine will be a Solar Panel. The aim of
this is to run the automobile using a Hybrid engine
Fabrication & Characterization of Bio Composite Materials Based On Sunnhemp F...IJMER
The present day technology demands eco-friendly developments. In this era the
composite material are playing a vital roal in different field of Engineering .The composite materials
are using as a principle materials. Nowaday the composite materials are utilizing as a important
component of engineering field .Where as the importance of the applications of composites is well
known, but thrust on the use of natural fibres in it for reinforcement has been given priority for some
times. But changing from synthetic fibres to natural fibres provides only half green-composites. A
partial green composite will be achieved if the matrix component is also eco-friendly. Keeping this in
view, a detailed literature surveyed has been carried out through various issues of the Journals
related to this field. The material systems used are sunnhemp fibres. Some epoxy and hardener has
been also added for stability and drying of the bio-composites. Various graphs and bar-charts are
super-imposed on each other for comparison among themselves and Graphs is plotted on MAT LAB
and ORIGIN 6.0 software. To determining tensile strengths, Various properties for different biocomposites
have been compared among themselves. Comparison of the behaviour of bio-composites of
this work has been also compare with other works. The bio-composites developed in this work are
likely to get applications in fall ceilings, partitions, bio-degradable packagings, automotive interiors,
sports things (e.g. rackets, nets, etc.), toys etc.
Geochemistry and Genesis of Kammatturu Iron Ores of Devagiri Formation, Sandu...IJMER
The Greenstone belts of Karnataka are enriched in BIFs in Dharwar craton, where Iron
formations are confined to the basin shelf, clearly separated from the deeper-water iron formation that
accumulated at the basin margin and flanking the marine basin. Geochemical data procured in terms of
major, trace and REE are plotted in various diagrams to interpret the genesis of BIFs. Al2O3, Fe2O3 (T),
TiO2, CaO, and SiO2 abundances and ratios show a wide variation. Ni, Co, Zr, Sc, V, Rb, Sr, U, Th,
ΣREE, La, Ce and Eu anomalies and their binary relationships indicate that wherever the terrigenous
component has increased, the concentration of elements of felsic such as Zr and Hf has gone up. Elevated
concentrations of Ni, Co and Sc are contributed by chlorite and other components characteristic of basic
volcanic debris. The data suggest that these formations were generated by chemical and clastic
sedimentary processes on a shallow shelf. During transgression, chemical precipitation took place at the
sediment-water interface, whereas at the time of regression. Iron ore formed with sedimentary structures
and textures in Kammatturu area, in a setting where the water column was oxygenated.
Experimental Investigation on Characteristic Study of the Carbon Steel C45 in...IJMER
In this paper, the mechanical characteristics of C45 medium carbon steel are investigated
under various working conditions. The main characteristic to be studied on this paper is impact toughness
of the material with different configurations and the experiment were carried out on charpy impact testing
equipment. This study reveals the ability of the material to absorb energy up to failure for various
specimen configurations under different heat treated conditions and the corresponding results were
compared with the analysis outcome
Non linear analysis of Robot Gun Support Structure using Equivalent Dynamic A...IJMER
Robot guns are being increasingly employed in automotive manufacturing to replace
risky jobs and also to increase productivity. Using a single robot for a single operation proves to be
expensive. Hence for cost optimization, multiple guns are mounted on a single robot and multiple
operations are performed. Robot Gun structure is an efficient way in which multiple welds can be done
simultaneously. However mounting several weld guns on a single structure induces a variety of
dynamic loads, especially during movement of the robot arm as it maneuvers to reach the weld
locations. The primary idea employed in this paper, is to model those dynamic loads as equivalent G
force loads in FEA. This approach will be on the conservative side, and will be saving time and
subsequently cost efficient. The approach of the paper is towards creating a standard operating
procedure when it comes to analysis of such structures, with emphasis on deploying various technical
aspects of FEA such as Non Linear Geometry, Multipoint Constraint Contact Algorithm, Multizone
meshing .
Static Analysis of Go-Kart Chassis by Analytical and Solid Works SimulationIJMER
This paper aims to do modelling, simulation and performing the static analysis of a go
kart chassis consisting of Circular beams. Modelling, simulations and analysis are performed using 3-D
modelling software i.e. Solid Works and ANSYS according to the rulebook provided by Indian Society of
New Era Engineers (ISNEE) for National Go Kart Championship (NGKC-14).The maximum deflection is
determined by performing static analysis. Computed results are then compared to analytical calculation,
where it is found that the location of maximum deflection agrees well with theoretical approximation but
varies on magnitude aspect.
In récent year various vehicle introduced in market but due to limitation in
carbon émission and BS Séries limitd speed availability vehicle in the market and causing of
environnent pollution over few year There is need to decrease dependancy on fuel vehicle.
bicycle is to be modified for optional in the future To implement new technique using change in
pedal assembly and variable speed gearbox such as planetary gear optimise speed of vehicle
with variable speed ratio.To increase the efficiency of bicycle for confortable drive and to
reduce torque appli éd on bicycle. we introduced epicyclic gear box in which transmission done
throgh Chain Drive (i.e. Sprocket )to rear wheel with help of Epicyclical gear Box to give
number of différent Speed during driving.To reduce torque requirent in the cycle with change in
the pedal mechanism
Integration of Struts & Spring & Hibernate for Enterprise ApplicationsIJMER
The proposal of this paper is to present Spring Framework which is widely used in
developing enterprise applications. Considering the current state where applications are developed using
the EJB model, Spring Framework assert that ordinary java beans(POJO) can be utilize with minimal
modifications. This modular framework can be used to develop the application faster and can reduce
complexity. This paper will highlight the design overview of Spring Framework along with its features that
have made the framework useful. The integration of multiple frameworks for an E-commerce system has
also been addressed in this paper. This paper also proposes structure for a website based on integration of
Spring, Hibernate and Struts Framework.
Microcontroller Based Automatic Sprinkler Irrigation SystemIJMER
Microcontroller based Automatic Sprinkler System is a new concept of using
intelligence power of embedded technology in the sprinkler irrigation work. Designed system replaces
the conventional manual work involved in sprinkler irrigation to automatic process. Using this system a
farmer is protected against adverse inhuman weather conditions, tedious work of changing over of
sprinkler water pipe lines & risk of accident due to high pressure in the water pipe line. Overall
sprinkler irrigation work is transformed in to a comfortableautomatic work. This system provides
flexibility & accuracy in respect of time set for the operation of a sprinkler water pipe lines. In present
work the author has designed and developed an automatic sprinkler irrigation system which is
controlled and monitored by a microcontroller interfaced with solenoid valves.
On some locally closed sets and spaces in Ideal Topological SpacesIJMER
In this paper we introduce and characterize some new generalized locally closed sets
known as
δ
ˆ
s-locally closed sets and spaces are known as
δ
ˆ
s-normal space and
δ
ˆ
s-connected space and
discussed some of their properties
Intrusion Detection and Forensics based on decision tree and Association rule...IJMER
This paper present an approach based on the combination of, two techniques using
decision tree and Association rule mining for Probe attack detection. This approach proves to be
better than the traditional approach of generating rules for fuzzy expert system by clustering methods.
Association rule mining for selecting the best attributes together and decision tree for identifying the
best parameters together to create the rules for fuzzy expert system. After that rules for fuzzy expert
system are generated using association rule mining and decision trees. Decision trees is generated for
dataset and to find the basic parameters for creating the membership functions of fuzzy inference
system. Membership functions are generated for the probe attack. Based on these rules we have
created the fuzzy inference system that is used as an input to neuro-fuzzy system. Fuzzy inference
system is loaded to neuro-fuzzy toolbox as an input and the final ANFIS structure is generated for
outcome of neuro-fuzzy approach. The experiments and evaluations of the proposed method were
done with NSL-KDD intrusion detection dataset. As the experimental results, the proposed approach
based on the combination of, two techniques using decision tree and Association rule mining
efficiently detected probe attacks. Experimental results shows better results for detecting intrusions as
compared to others existing methods
Natural Language Ambiguity and its Effect on Machine LearningIJMER
"Natural language processing" here refers to the use and ability of systems to process
sentences in a natural language such as English, rather than in a specialized artificial computer
language such as C++. The systems of real interest here are digital computers of the type we think of as
personal computers and mainframes. Of course humans can process natural languages, but for us the
question is whether digital computers can or ever will process natural languages. We have tried to
explore in depth and break down the types of ambiguities persistent throughout the natural languages
and provide an answer to the question “How it affects the machine translation process and thereby
machine learning as whole?” .
Today in era of software industry there is no perfect software framework available for
analysis and software development. Currently there are enormous number of software development
process exists which can be implemented to stabilize the process of developing a software system. But no
perfect system is recognized till yet which can help software developers for opting of best software
development process. This paper present the framework of skillful system combined with Likert scale. With
the help of Likert scale we define a rule based model and delegate some mass score to every process and
develop one tool name as MuxSet which will help the software developers to select an appropriate
development process that may enhance the probability of system success.
Material Parameter and Effect of Thermal Load on Functionally Graded CylindersIJMER
The present study investigates the creep in a thick-walled composite cylinders made
up of aluminum/aluminum alloy matrix and reinforced with silicon carbide particles. The distribution
of SiCp is assumed to be either uniform or decreasing linearly from the inner to the outer radius of
the cylinder. The creep behavior of the cylinder has been described by threshold stress based creep
law with a stress exponent of 5. The composite cylinders are subjected to internal pressure which is
applied gradually and steady state condition of stress is assumed. The creep parameters required to
be used in creep law, are extracted by conducting regression analysis on the available experimental
results. The mathematical models have been developed to describe steady state creep in the composite
cylinder by using von-Mises criterion. Regression analysis is used to obtain the creep parameters
required in the study. The basic equilibrium equation of the cylinder and other constitutive equations
have been solved to obtain creep stresses in the cylinder. The effect of varying particle size, particle
content and temperature on the stresses in the composite cylinder has been analyzed. The study
revealed that the stress distributions in the cylinder do not vary significantly for various combinations
of particle size, particle content and operating temperature except for slight variation observed for
varying particle content. Functionally Graded Materials (FGMs) emerged and led to the development
of superior heat resistant materials.
Energy Audit is the systematic process for finding out the energy conservation
opportunities in industrial processes. The project carried out studies on various energy conservation
measures application in areas like lighting, motors, compressors, transformer, ventilation system etc.
In this investigation, studied the technical aspects of the various measures along with its cost benefit
analysis.
Investigation found that major areas of energy conservation are-
1. Energy efficient lighting schemes.
2. Use of electronic ballast instead of copper ballast.
3. Use of wind ventilators for ventilation.
4. Use of VFD for compressor.
5. Transparent roofing sheets to reduce energy consumption.
So Energy Audit is the only perfect & analyzed way of meeting the Industrial Energy Conservation.
An Implementation of I2C Slave Interface using Verilog HDLIJMER
The focus of this paper is on implementation of Inter Integrated Circuit (I2C) protocol
following slave module for no data loss. In this paper, the principle and the operation of I2C bus protocol
will be introduced. It follows the I2C specification to provide device addressing, read/write operation and
an acknowledgement. The programmable nature of device provide users with the flexibility of configuring
the I2C slave device to any legal slave address to avoid the slave address collision on an I2C bus with
multiple slave devices. This paper demonstrates how I2C Master controller transmits and receives data to
and from the Slave with proper synchronization.
The module is designed in Verilog and simulated in ModelSim. The design is also synthesized in Xilinx
XST 14.1. This module acts as a slave for the microprocessor which can be customized for no data loss.
Discrete Model of Two Predators competing for One PreyIJMER
This paper investigates the dynamical behavior of a discrete model of one prey two
predator systems. The equilibrium points and their stability are analyzed. Time series plots are obtained
for different sets of parameter values. Also bifurcation diagrams are plotted to show dynamical behavior
of the system in selected range of growth parameter
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
block diagram and signal flow graph representation
Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer) Controller Using VHDL
1. International
OPEN ACCESS Journal
Of Modern Engineering Research (IJMER)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 9 |
Implementation of Wide Band Frequency Synthesizer Base on
DFS (Digital Frequency Synthesizer) Controller Using VHDL
Md. Aamir Rauf Khan1
, Archana Yadav2
1, 2
(Department of ECE, Integral University, India)
I. INTRODUCTION
Wide Band Frequency Synthesizer has become essential components in wireless communication
systems. They are used as frequency synthesizers with precise and convenient digital control in both traditional
electronics, such as televisions and AM/FM radios, and modern consumer products among which cellular
mobile phone is a striking example.
IC fabrication technology advances have made monolithic integration possible. More and more
electronic devices can be put on the same chip to reduce the number of external components and then the costs.
Therefore, on a single chip we can accomplish many functions for which we might need to make several chips
work together a few years ago. A monolithic wide-band PLL is of great interests to wireless communication
applications due to both its low cost and convenience to switch between different communication standards.
The focus of this work is to implement a wide-band Frequency Synthesizer using as few as possible building
blocks and also as simple as possible structure.
Many of the concepts of DDS are illustrated by the way in which a sine wave is generated. The figure
below shows a block diagram of a simple DDS function generator. The sine function is stored in a RAM table.
The RAM's digital sine output is converted to an analog sine wave by a DAC. The steps seen at the DAC
output are filtered by a low pass filter to provide a clean sine wave output.
The frequency of the sine wave depends on the rate at which addresses to the RAM table are changed.
Addresses are generated by adding a constant, stored in the phase increment register (PIR), to the phase
accumulator. Usually, the rate of additions is constant, and the frequency is changed by changing the number
in the PIR.
Our intuition might suggest that a large number of samples are required for each cycle of the sine
wave to achieve good spectral purity of the output. A sketch of a sine which is approximated by a small number
of samples per cycle hardly looks like a sine wave. Remarkably, only about three samples are required during
each cycle. In fact, if we could make an arbitrarily sharp, low-pass filter, we would need only two samples per
cycle
Abstract: A frequency synthesizer is an electronic system for generating any of a range of frequencies
from a single fixed time base or oscillator. They are found in many modern devices, including radio
receivers, mobile telephones, radiotelephones, walkie-talkies, CB radios, satellite receivers, GPS
systems, etc. Direct Digital Synthesis (DDS) is a kind of frequency synthesizer that use electronic
methods for digitally creating arbitrary waveforms and frequencies from a single, fixed source
frequency. Direct Digital Frequency Synthesis (DDFS) is a mixed signal part i.e. it has both digital and
analog parts. DDFS’s digital part is also known as Numerically Controlled Oscillator (NCO), which
consists of a Phase Register, a Phase Accumulator (PA) and a ROM. The analog part has Digital-to-
Analog Converter and a filter. NCO is a digital computing block which renders digital word sequences
in time at a given reference clock frequency, which thereafter are converted into analog signals to serve
as a synthesizer. The phase accumulator (PA) clocked with, generates the phase value sequence.
Application of the DDFS ranges from instrumentation to modern communication systems, which employs
spread-spectrum and phase shift-keying modulation techniques.
The focus of this paper is on design, analysis and simulation of DDFS, using tools like Xilinx and
Cadence. Traditional designs of high bandwidth frequency synthesizers employ the use of a phase
locked- loop (PLL). DDFS provides many significant advantages over the PLL approaches, such as fast
settling time, sub-Hertz frequency resolution, continuous-phase switching response and low phase noise.
Keywords: DFS, Modelsim 10.2a, VHDL, Wide Band Frequency Synthesizer, Xilinx ISE 14.2.
2. Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 10 |
II. RELATED WORK
The Fast frequency switching is crucially important in modern wireless communication systems such
as TDMA/CDMA digital cellular systems and spectrum-spread wireless LANs. For example, the TDMA
system may require that the carrier frequency have to be switched during a signal slot, that is, the change must
be accomplished within 100us. Linear phase shifting is also crucial in any system that uses phase shift keying
modulation techniques. Such system includes IS-95, IS-94, GSM, DCS-1800, CDPD and several others.
Direct Digital Frequency Synthesizer (DDFS) can achieve fast frequency switching in small frequency steps,
over a wide band. Also it provides linear phase and frequency shifting with good spectral purity. So, DDFS is
best suited to use in the above communication systems. A further requirement for DDFS is low power
consumption budget, especially for portable wireless terminals.
Woogeun Rhee et al (2013), worked on overview of fractional- N phase-locked loops (PLLs) with
practical design perspectives focusing on a 0Σ modulation technique and a finite-impulse response (FIR)
filtering method. Spur generation and nonlinearity issues in the 0Σ fractional-N PLLs are discussed with
simulation and hardware results. High-order 0Σ modulation with FIR-embedded filtering is considered for low
noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for
alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the
finite-modulo fractional-N PLL design [2].
Govind S. Patel et al (2013), worked on an optimized Direct Digital Frequency Synthesizer (DDFS)
utilizing Piecewise Linear Approximation is introduced. The proposed technique allows successive read access
to memory cells per one clock cycle using time sharing. The output values will be temporarily stored and read
at a later time. The output of this system is a reconstructed signal that is a good approximation of the desired
waveform. As a result, the DDFS only needs to store fewer coefficients and the hardware complexity is
significantly reduced. The proposed DDFS has been analyzed using MATLAB. The SFDR of synthesized
achieved is 84.2 dBc. To prove the better performance of proposed DDS architecture it is compared favorably
with several existing DDS architectures. In future it can also be used to improve the performance of Hybrid
DDS-PLL Synthesizers [3].
M. NourEldin M. et al (2013), proposed a algorithm for a low-power high-resolution ROM-less
Direct Digital frequency synthesizer architecture based on FPGA Design is proposed. This work is equipped to
generate a sinusoidal waveform with a new simple design method, which is endowed with high speed, low
power and high spurious free dynamic range (SFDR) features. The proposed low power methodology is
achieved by two methods: first, in a phase accumulator design by selecting a pipelined phase accumulator with
8-bit components that has lowest number of four input LUTs and number of occupied Slices. Second, in the
circuit of TSC by proposing the circuit without an external power source. The output frequency of proposed
design is 195.35 kHz using built in clock frequency of 50MHz. However, the maximum operating frequency is
190.93MHz. In addition, the design has frequency resolution of 0.012Hz, which is promising to get very high
tuning frequency with SFDR of 42 dBc or 70 dBFS [4].
Eli Bloch wt al, (2013), worked on an integrated circuit (IC) for heterodyne optical phase locking in a
1–20-GHz offset range is hereby reported. The IC, implemented in a 500-nm InP HBT process, contains an
emitter coupled logic digital single-sideband mixer to provide phase locking at a 20-GHz offset frequency, and
a wideband phase-frequency detector designed to provide loop acquisition up to 40-GHz initial frequency
offset. The all-digital IC design has phase-frequency detection gain independent of IC process parameters or
optical signal levels, and provides a wide offset locking range. A 100-ps delay decreases the overall loop delay,
making wideband loop filter design possible. In addition, a medium-scale high-frequency logic design
methodology is presented and fully discussed [5].
Jochen Rust et al, (2012) said that nowadays Direct Digital Frequency Synthesizers (DDFS) are used
in a vast area of applications, the demand for simple and efficient hardware design and implementation
methods is a highly important aspect. In this work a new approach is introduced considering Automatic
Nonuniform Piecewise linear function Approximation (ANPA). Automatic function generation is performed
that enables quick HDL design by parameter specification in advance. For evaluation, several different
configurations are simulated regarding approximation accuracy and complexity. In addition, logical and
physical IC synthesis is performed for selected designs and their results are compared with actual references
with respect to the common hardware constraints power, area and time [6].
3. Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 11 |
III. METHODOLOGY
The concept of this technique is the same with that used in above quadrant compression technique [3].
Figure 1 shows the block diagram of the proposed DDFS architecture. The MSB2 is used to select the
quadrants of the sine wave, while the MSB1 is used to control the format converter. The remaining W-2 bits
are fed into Complement or whose output is split into two parts, the MSB part, with A bits long, represents the
S segments and the LSB part with B bits long, represents an angle x in the interval [0,π/ (2S)]. A multiplexer
and its coefficients are the equivalent of a ROM which provide the segment initial amplitudes Qi, represented
with D bits. The proposed architecture also incorporates pulse forming circuit which controls the fetching and
loading process of successive Qi coefficients. This circuit along with the three storage registers and one
Subtract or is essential to perform the task of the slope derivation during the segment interval. Besides the sine
symmetry property, the linear approximation method has been used to approximate the first quadrant of sine
function by S straight lines; each line is defined by two coefficients, Pi and Qi. The coefficient Mi, which
represents the slope of ith element. The first quadrant of sine function approximation segment can be
calculated from the sine function as follows.
Pi = {sin [iΔx] –sin [(i-1) Δx]}/ Δx 1≤ i ≤ S (1)
where, Δx = the length of segment. Above Eq. (1) can be realized easily by subtracting the Sin [i.Δx] at
successive phase angles and then dividing the result by Δx.
As Δx unsigned constant coefficient, the division can simply be realized by binary operation. The coefficients
Qi, is equal to [sin (i-1) Δx] points, As examples for segment number1, (Q1= 0), yields K1 = P1x and for
segment number 2, (Q2 = sin Δx), in general, Qi = sin [(i-1) Δx] for the ith segment and it can be realized by
delaying the pervious sin (iΔx) by one clock period, hence the realization of the whole Ki (x) function is
accomplished. It is clear that it must get two consecutive sine points at the same time to conduct the process of
subtraction and extraction of the slope later.
These two sine points can be got only when the corresponding phase angles point simultaneously to
their addresses in the sine LUT and that is an inconsequent assumption. As mentioned earlier, the accessing of
the memory is valid only once at a specific clock cycle. In this study, we introduce architecture of pulse
forming circuit which is performing the task of time sharing and propose the procedure enumerated below to
get around this problem. The value of phase register at any clock period represents the phase of the sine
function. As not all of the samples of the sinusoid are stored, only the first A bits of the W-2 phase accumulator
output are used to select segment initial amplitudes Qi. , i.e., it represents the MUX address inputs. The
remaining B LSB's bits (B = W-2-A) represent an angle x in the interval Δx and are used to calculate the value
of the interpolated sine point. It has three simple blocks: digital comparator, pulse narrowing circuit and
tapped delay.
At each clock cycle, the digital comparator examines the MUX Address inputs for detecting the
changes in data select inputs i.e., transitions between the segments
The detected signal will be applied to the Pulse Narrowing Circuit to produce a Δt pulse width signal
i.e., trigger1 (tg1), which is usually a fraction of 1/fclk
This signal, tg1 gives an order to advance the Data Select Inputs of MUX by 1, hence the output of the
MUX during this time slot is Sin [(i+2)Δx]
At the same time, the tg1 is used to load this value in register1 (R1)
After Δt, the data select inputs get back to the previous address value, so the output of MUX will be Sin
[(i+1)Δx]
Trigger2 (tg2) enables register 2 (R2) to load this value
The content of R2 will be subtracted from the content of R1 and the result will be loaded in register3
(R3), after a specific time which is precisely sufficient to give a chance for signals to be propagated
through all gates and settle. Hence, the slope is simply derived and kept unchanged during the segment
interval.
4. Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 12 |
Fig 1: Block diagram of a direct digital frequency synthesizer
As shown in Figure 1, the main components of a DDFS are a phase accumulator, phase-to-amplitude converter
(a sine look-up table), a Digital-to-Analog Converter and filter. A DDFS produces a sine wave at a given
frequency. The frequency depends on three variables; the reference-clock frequency and the binary number
programmed into the phase register (frequency control word,clkfM), length of n-bit accumulator. The binary
number in the phase register provides the main input to the phase accumulator.
If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table,
which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The
DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-
frequency sine wave, a constant value (the phase increment—that is determined by the binary numberM) is
added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator
will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase
increment is small, the phase accumulator will take many more steps, accordingly generating a slower
waveform.
Building Blocks of DDFS:
A DDFS is a mixed signal device i.e. it has both analog and digital blocks. These blocks are the Phase
Register, Phase Accumulator, Phase-to-Amplitude Converter (ROM/LUT), Digital-to-Analog Converter, and
Reconstruction Filter. The functionality of each of these blocks is discussed in the following section.
Phase Accumulator:
Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 360 degrees. The
digital implementation is no different. The counter‘s carry function allows the phase accumulator to act as a
phase wheel in the DDFS implementation.
Phase-to-Amplitude Converter (ROM/ LUT):
The DDFS‘s ROM is a sine Look up Table; it converts digital phase input from the accumulator to
output amplitude. The accumulator output represents the phase of the wave as well as an address to a word,
which is the corresponding amplitude of the phase in the LUT. This phase amplitude from the ROM LUT
drives the DAC to provide an analog output. It is also called a digital Phase-to-Amplitude Converter (PAC)
Digital-to-Analog Converter and Filter:
The phase accumulator computes a phase (angle) address for the look-up table, which outputs the
digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC, in turn,
converts that number to a corresponding value of analog voltage or current.
5. Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 13 |
IV. SIMULATION RESULTS
We are generating the sine wave of 1 Hz frequency with different phases in below results. We are
taking frequency 1 Hz converting it into decimal 2147483 then we converting this into hexadecimal we are
getting 0020c49B. In the same way we are converting phase into angle to radian and then converting it into
decimal and hexadecimal as well. In this case we are generating the sine wave of above said frequency with 0o
phase (simple sine wave) shown in fig 2. In this case we are working on positive edge of clock and reset will be
‗0‘.
Fig 2: Simulation Results for 0o
Phase.
In this case we are generating the sine wave of above said frequency with 90o
phase shown in fig 3. In this case
we are working on positive edge of clock and reset will be ‗0‘.
Fig 3: Simulation Results for 90o
Phase Shift.
6. Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 14 |
In this case we are generating the sine wave of above said frequency with 45o
phase shift. In this case we are
working on positive edge of clock and reset will be ‗0‘ shown in fig 4.
Fig 4: Simulation Results for 45o
Phase Shift.
In this case we are generating the sine wave of above said frequency with -12o
phase shift. In this case we are
working on positive edge of clock and reset will be ‗0‘ shown in fig 5.
Fig 5: Simulation Results for -12o
Phase Shift.
7. Implementation of Wide Band Frequency Synthesizer Base on DFS (Digital Frequency Synthesizer)
| IJMER | ISSN: 2249–6645 | www.ijmer.com | Vol. 4 | Iss. 5| May. 2014 | 15 |
V. CONCLUSION
The DDS IP core (dds_synthesizer) is a implementation of a direct digital frequency synthesizer
(DDS) (also called number controlled oscillator, NCO) which produces a sine wave at the output with a
specified frequency and phase (adjustable at runtime). The resolution of the frequency tuning word (FTW), the
phase and the amplitude are defined seperately. While the FTW resolution can be set by the generic ftw_width,
phase and amplitude resolution are defined as constants phase_width and ampl_width in the seperate package
sine_lut_pkg. We have Simulated the Direct Frequency Synthesizer for Sine wave generation from 1Hz to 100
MHz with Amplitude -1V to 1V. The output frequency range / Amplitude range can be change by
manipulating the Bit width of Ampl_o or FTW.
We can further enhance our design to generate Triangular/ Square by using the presented design with some
more logical gate inserting into it. For implementing on hardware side we must include a DAC.DAC is
required to generate the analog pulses as most of the devices supports only analog input.
REFERENCES
[1] C.S. Vaucher, Architectures for RF Frequency Synthesizers. Boston: Kluwer Academic Publishers, 2002.
[2] Woogeun Rhee et al, ―Fractional-N Frequency Synthesis: Overview and Practical Aspects with FIR-Embedded
Design‖ Journal Of Semiconductor Technology And Science, Vol.13, No.2, April, 2013.
[3] Govind S. Patel et al , ― The Optimization of Direct Digital Frequency Synthesizer Performance by New
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Generation‖ 20th European Signal Processing Conference (EUSIPCO 2012) Bucharest, Romania, August 27 - 31,
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