Tom Palkert of Luxtera and MoSys and the OIF PLL Vice Chair Electrical spoke at the Fiber Optics Expo in Japan on 56G CEI - Electrical Interfaces, port density requirements, applications, PAM-4 vs NRZ results and arguments
DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112GLeah Wilkinson
DesignCon 2019
112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity
A 64Gb/s PAM-4 Transmitter with 4-Tap FFE and 2.26pJ/b Energy Efficiency in 2...aiclab
University of Pavia and STMicroelectronics present a PAM-4 transmitter with 4-tap FFE in 28nm FDSOI CMOS. The proposed TX leverages a new serializer architecture and output stage to demonstrate 1.2Vppd output swing and the highest reported speed of 64Gb/s. Further, it shows state-of-the-art 2.26pJ/bit energy efficiency while meeting CEI-56G-PAM-4 requirements.
DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112GLeah Wilkinson
DesignCon 2019
112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity
A 64Gb/s PAM-4 Transmitter with 4-Tap FFE and 2.26pJ/b Energy Efficiency in 2...aiclab
University of Pavia and STMicroelectronics present a PAM-4 transmitter with 4-tap FFE in 28nm FDSOI CMOS. The proposed TX leverages a new serializer architecture and output stage to demonstrate 1.2Vppd output swing and the highest reported speed of 64Gb/s. Further, it shows state-of-the-art 2.26pJ/bit energy efficiency while meeting CEI-56G-PAM-4 requirements.
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that we describe below are based on best practices and proven methodologies in ASIC chip designs. This blog attempts to explain different steps in the ASIC design flow, starting from ASIC design concept and moving from specifications to benefits.
To ensure successful ASIC design, engineers must follow a proven ASIC design flow which is based on a good understanding of ASIC specifications, requirements, low power design and performance, with a focus on meeting the goal of right time to market. Every stage of ASIC design cycle has EDA tools that can help to implement ASIC design with ease.
Co-Packaged Optics: The OIF’s Work to Standardize Higher Integration Levels f...Leah Wilkinson
OIF Presents:
Co-Packaged Optics: The OIF’s Work to Standardize Higher Integration Levels for Next-Generation Data Center Systems
ECOC Market Focus
New Technologies & Systems/New Markets/New Packaging Platforms
Wed, 15 September 2021
Jeff Hutchins / Ranovus
OIF PLL Working Group Co-Packaging Vice Chair
Electrical interfaces at 112 Gbps are a critical enabler of faster, more efficient and cost effective networks and data centers. A panel of OIF contributors will discuss the ongoing CEI-112G electrical interface development projects, and the new architectures they will enable including chiplet packaging, co-packaged optics and internal cable based solutions. The panel will provide an update on the multiple interfaces being defined by the OIF including CEI-112G MCM, XSR, VSR, MR and LR for 112 Gbps applications of die-to-die, chip-to-module, chip-to-chip and long reach over backplane and cables. Listen to thought leaders in the electrical interface industry debate the issues surrounding the CEI-112G projects and the architectures they will enable.
CEI-112G is the next wave of electrical interfaces. OIF members presented to the 2017 Design Con community on where the technology for electrical interfaces is headed.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
5 Clock Tree Design Techniques to Optimize SerDes Performance for Networking ...Silicon Labs
As new designs adopt FPGAs, SoCs, ASICs, and CPUs with higher speed SerDes, it’s becoming increasingly important to understand the impact of reference timing on overall system performance. This deck provides practical guidance on overcoming common timing design challenges by reviewing timing requirements for 10G/25G/40G/56G-based designs, explaining when to use clocks versus oscillators, highlighting system-level factors that degrade signal integrity and reviewing how to budget jitter and/or phase noise margin in order to select an optimal timing solution. This deck also explains how to use common bench equipment and software-based tools to simplify the design-in process.
Watch the complete webinar here: http://bit.ly/2zkBIHb
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that we describe below are based on best practices and proven methodologies in ASIC chip designs. This blog attempts to explain different steps in the ASIC design flow, starting from ASIC design concept and moving from specifications to benefits.
To ensure successful ASIC design, engineers must follow a proven ASIC design flow which is based on a good understanding of ASIC specifications, requirements, low power design and performance, with a focus on meeting the goal of right time to market. Every stage of ASIC design cycle has EDA tools that can help to implement ASIC design with ease.
Co-Packaged Optics: The OIF’s Work to Standardize Higher Integration Levels f...Leah Wilkinson
OIF Presents:
Co-Packaged Optics: The OIF’s Work to Standardize Higher Integration Levels for Next-Generation Data Center Systems
ECOC Market Focus
New Technologies & Systems/New Markets/New Packaging Platforms
Wed, 15 September 2021
Jeff Hutchins / Ranovus
OIF PLL Working Group Co-Packaging Vice Chair
Electrical interfaces at 112 Gbps are a critical enabler of faster, more efficient and cost effective networks and data centers. A panel of OIF contributors will discuss the ongoing CEI-112G electrical interface development projects, and the new architectures they will enable including chiplet packaging, co-packaged optics and internal cable based solutions. The panel will provide an update on the multiple interfaces being defined by the OIF including CEI-112G MCM, XSR, VSR, MR and LR for 112 Gbps applications of die-to-die, chip-to-module, chip-to-chip and long reach over backplane and cables. Listen to thought leaders in the electrical interface industry debate the issues surrounding the CEI-112G projects and the architectures they will enable.
CEI-112G is the next wave of electrical interfaces. OIF members presented to the 2017 Design Con community on where the technology for electrical interfaces is headed.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
5 Clock Tree Design Techniques to Optimize SerDes Performance for Networking ...Silicon Labs
As new designs adopt FPGAs, SoCs, ASICs, and CPUs with higher speed SerDes, it’s becoming increasingly important to understand the impact of reference timing on overall system performance. This deck provides practical guidance on overcoming common timing design challenges by reviewing timing requirements for 10G/25G/40G/56G-based designs, explaining when to use clocks versus oscillators, highlighting system-level factors that degrade signal integrity and reviewing how to budget jitter and/or phase noise margin in order to select an optimal timing solution. This deck also explains how to use common bench equipment and software-based tools to simplify the design-in process.
Watch the complete webinar here: http://bit.ly/2zkBIHb
System Architectures Using OIF CEI-56G Interfaces by
Nathan Tracy, Technologist, TE Connectivity and Technical Committee Chair, OIF. Presentation at Fiber Optics Expo 2015 in Tokyo, Japan, April 9, 2015
Optics and Photonics Core Market Analysis from SPIESteve Anderson
A novel approach to assessing the photonics industry involves an in-depth look at more than 3000 companies. It has yielded a unique ranking of the firms that serve the optics and photonics marketplace and their impact on the global economy.
In this slidecast, Brian Welch from Luxtera presents: Silicon Photonics for HPC Interconnects. Luxtera is the first company to overcome the complex technical obstacles involved with integrating high performance optics directly with silicon electronics on a mainstream CMOS chip, bringing direct “fiber to the chip” connectivity to market.
Implications of super channels on CDC ROADM architecturesAnuj Malik
OFC 2014 Presentation
This study proposes CDC ROADM architecture compatible with emerging DWDM super-channel technology. A real world network model is used to quantify that this architecture requires fewer network components leading to less capital and operational costs.
In this deck from the 2019 OpenFabrics Workshop in Austin, Ariel Almog from Mellanox presents: To HDR and Beyond.
"Recently, deployment of 50 Gbps per lane (HDR) speed started and 100 Gbps per lane (EDR) which is a future technology is around the corner. These technologies exposing various new physical interfaces for copper and optical interfaces and type of transceiver like SFP-DD. Supporting these speeds also toughen the task to get low BER (Bit Error Rate) through FEC (Forward Error Correction) algorithm. The high bandwidth might cause the NIC PCIe interface to become a bottle neck as PCIe gen3 can handle up to single 100 Gbps interface over 16 lanes and PCIe gen4 can handle up to single 200 Gbps interface over 16 lanes. In addition, since the host might have dual CPU sockets, Socket direct technology, provides direct PCIe access to dual CPU sockets, eliminates the need for network traffic to go over the inter-process bus and allows better utilization of PCIe, thus optimizing overall system performance."
Watch the video: https://wp.me/p3RLHQ-k0B
Learn more: http://mellanox.com
and
https://www.openfabrics.org/2019-workshop-agenda-and-abstracts/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
The Next Generation Multimode Fiber: Wide Bandwidth MMFLizGoldsmith
Learn about Wide Band Multimode Fiber (WBMMF) -- the application drivers, multiplexing technology, parallel fiber transmission, and Short Wavelength Wave Division Multiplexing. This presentation will also review the cabling evolution roadmap and the WBMMF specification framework.
A 45Gb/s PAM-4 Transmitter Delivering 1.3Vppd Output Swing with 1V supply in ...aiclab
Pushed by the ever-increasing demand of high-speed connectivity, next generation 400Gb/s electrical links are targeting PAM-4 modulation to limit channel loss and preserve link budget. Compared to NRZ, a higher amplitude is desirable to counteract the 1/3 reduction of PAM-4 vertical eye opening. However, linearity is also key, and PAM-4 levels must be precisely spaced to preserve the horizontal eye opening advantage it has over NRZ. This paper presents a 45Gb/s PAM-4 transmitter able to deliver a very large output swing with enhanced linearity and state-of-the-art efficiency. Built around a hybrid combination of current-mode and voltage-mode topologies, the driver is embedded into a 4-taps 5-bits FFE, and allows tuning the output impedance to ensure good source termination. Implemented in 28nm CMOS FDSOI process, the full transmitter includes a half-rate serializer, duty-cycle correction circuit, >>2kV HBM ESD diodes, and delivers a full swing of 1.3Vppd at 45Gb/s, while drawing 120mA only from 1V supply. The power efficiency is ~2 times better than previously reported PAM-4 transmitters.
Duotech's F-16 Briefing During the 2015 F-16 TCG WWRLee Cloer
Brett Rogers, Vice President of Duotech Services, provides a presentation during the morning F-16 Briefings held at the 2015 F-16 TCG Worldwide Review. This briefing was held on the morning of September 14, 2015. If you missed this presentation, we recorded it and have included the full video at the link here > http://duotechservices.com/duotechs-briefing-f-16-tcg-wwr
PAM4 Analysis and Measurement Considerations WebinarHilary Lustig
This webinar explores the acquisition and analysis of PAM4 waveforms. We will show PAM4 Test Configurations, Compliance Measurements and Debug Techniques.
PAM4 Analysis and Measurement Webinar Slidedeckteledynelecroy
In this Teledyne LeCroy webinar we explore the acquisition and analysis of PAM4 waveforms. We will cover PAM4 test configurations, compliance measurements and debug techniques.
High-performance 32G Fibre Channel Module on MDS 9700 Directors:Tony Antony
To better serve the new application requirements, Cisco is introducing a New high-performance Analytics ready 32G Fibre Channel Module on MDS 9700 Directors and a new 32G Host Bus Adapter for UCS C-series. The end to end 32G FC support across Cisco DC platforms set new standards for Storage Networking providing customers with choice. Along with this announcement, Cisco is also announcing NVMe over Fabric support on MDS 9000 Series enabling customers to take advantage of the performance and low latency benefits offered by the new technology to scale efficiently in the post-flash environments.
Sometimes we all need to go back to basics and remind ourselves the essential details on Wi-Fi technology. Join us in this session to learn more about 802.11n/11ac standards, rate vs range, legacy and 11n/11ac co-existence and more.
To learn more, visit us at http://www.arubanetworks.com/wlan. Join the discussion at https://community.arubanetworks.com
In this deck from the Argonne Training Program on Extreme-Scale Computing 2019, Scott Parker from Argonne presents: Theta and the Future of Accelerator Programming.
Designed in collaboration with Intel and Cray, Theta is a 6.92-petaflops (Linpack) system based on the second-generation Intel Xeon Phi processor and Cray’s high-performance computing software stack. Capable of nearly 10 quadrillion calculations per second, Theta will enable researchers to break new ground in scientific investigations that range from modeling the inner workings of the brain to developing new materials for renewable energy applications.
Theta’s unique architectural features represent a new and exciting era in simulation science capabilities,” said ALCF Director of Science Katherine Riley. “These same capabilities will also support data-driven and machine-learning problems, which are increasingly becoming significant drivers of large-scale scientific computing.”
Watch the video: https://wp.me/p3RLHQ-lkl
Learn more: https://www.alcf.anl.gov/news/argonnes-theta-supercomputer-goes-online
and
https://extremecomputingtraining.anl.gov/archive/atpesc-2019/agenda-2019/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
MAT 510 – Homework AssignmentHomework Assignment 6 Due.docxjessiehampson
MAT 510 – Homework Assignment
Homework Assignment 6
Due in Week 9 and worth 30 points
Suppose the number of equipment sales and service contracts that a store sold during the last six (6) months for treadmills and exercise bikes was as follows:
Equipment Sales and Service Contracts Sold
Treadmill
Exercise Bike
Total Sold
185
123
Service Contracts
67
55
The store can only sell a service contract on a new piece of equipment. Of the 185 treadmills sold, 67 included a service contract and 118 did not.
Complete the following questions in the space provided below:
1. Construct a 95 percent confidence interval for the difference between the proportions of service contracts sold on treadmills versus exercise bikes.
2. Is there a major difference between the two pieces of equipment? Why or why not?
Type your answers below and submit this file in Week 9 of the online course shell:
802.11 THROUGHPUT
comp40660 Assignment 1, February 2020
This assignment is worth 18% of the overall grade
Motivation
• Build a simple model of 802.11 frame exchange for TCP
and UDP, using OFDM of 802.11a and 802.11g
• The model will approximate the actual throughput of the
network
• RTS/CTS mechanism is enabled
• No contention
• Demonstration of the calculation for 802.11a – UDP case;
work on TCP case in lab.
• Assignment will be to modify for the .11g/n/ac/ax case for
both TCP and UDP.
802.11 Model
• Basic transactional model – 2 different transaction types, namely
UDP and TCP.
• Any 802.11 transmission of data (from higher layer) requires an
acknowledgement (ACK) by the .11 MAC.
• Each TCP / UDP packet is encapsulated in a single 802.11 frame.
Transport
Network
Data Link
Physical
Transport
Network
Data Link
PhysicalBits
Frame
Packet
Segment
802.11 Frame Exchange
UDP Case
• No guarantee of delivery
• Suitable for real-time applications such as VoIP, VoD
• UDP data encapsulated into 802.11 frame and
transmitted. Receiving station transmits 802.11 ACK.
Server Client
UDP
802.11 Frame Exchange
TCP Case
• Reliable delivery service guaranteeing that all bytes are
received and in correct order through TCP ACKs
• How is this different from the UDP case?
TCP
ACK
Server Client
Data Transmission
• 802.11 uses different inter-frame spaces:
• SIFS (Short Interframe Space)
• High-priority transmissions can begin once SIFS has elapsed
• ACK, RTS, CTS
• DIFS (DCF Interframe Space)
• Minimum idle time for contention-based services
• Stations can have access to the medium if it has been free for
a period longer than DIFS
Packet Headers
• 1500 bytes packet (TCP/UDP) is encapsulated:
• MAC header = 34 bytes
• SNAP LLC header = 8 bytes
• 3 bytes LLC (logical link control) header
• 5 bytes SNAP (sub-network access protocol) header
=> Total size = 1542 bytes
802.11a
• Amendment to the IEEE 802.11 specification
• 1999
• 5Ghz band
• Maximum data rate: 54 Mbps
• OFDM (Orthogonal Frequency Division.
Cisco DWDM Chromatic Dispertion Calculation in CTP\XLSValery Kayukov
Cisco DWDM Chromatic Dispertion Calculation in CTP\XLS:
- Princiopals of CD
- Measurement of CD
- Manual calculation in XLS
- Automatic Calculation in CTP
"OIF Interop – the Key to Unlocking the Benefits of SDN" at OptiNet China 2017Deborah Porchivina
T-API interop demo recap and review of OIF’s current projects presented to more than 500 attendees at OptiNet China in Beijing by Li Junjie, Board Member of Optical Internetworking Forum (OIF), Director, Optical Communications Research Center, Beijing Research Institute, China Telecom
Transport API is a solution that enables SDN for Carriers Networks with an evolutionary approach. It automates and simplifies the operation of transport domains for L0, L1 and L2 services. Learn how the OIF's interoperability demo is helping to bring T-API to market.
SDN Transport API Interoperability Demo with OIF and ONFDeborah Porchivina
OIF Interoperability Demonstration show that Transport SDN is becoming real. ONF T-API Specification is published, implemented and tested. Next is T-API 2.0
Christophe Alter of Orange Telecom presented to attendees of MPLS+SDN+NFV World in Paris in March 2017. He discussed the OIF's new certification program.
Nathan Tracy, OIF Technical Committee Chair and TE Connectivity was invited to speak at ECOC's Market Focus on OIF Interoperability – The Key to Unlocking the Benefits of SDN
OIF presentation at 21st European Conference on Networks and Optical Communications (NOC). Service Providers want programmable network control, Lower costs, New Services, Differentiation. SDN APIs in a Component Architecture
enable programmability. Components may be added in parallel, upgraded. Rich APIs required - Connection Management, Path Computation, Topology.
OIF's Carrier Working Group Chair, Vishnu Shukla, Verizon shares network virtualization and SDN controls to enable transport network as a service to OFC2016 attendees.
The Optical Internetworking Forum (OIF) will host a public workshop addressing the latest developments in 100G Serial, immediately following OFC 2016 in Anaheim, California. The event, OIF Workshop – 100G Serial Electrical Links and Beyond, is open to the public and scheduled for Thursday, March 24, 2016, from 12:30 pm to 6:15 pm at the Anaheim Marriott Hotel.
Vishnu Shukla of Verizon USA and the OIF Carrier Working Group Chair spoke at Globecom 2015 about the Verizon perspective towards SDN and how the OIF was working to support carrier needs to improve transport control through SDN.
Lyndon Ong, of Ciena and the OIF Marketing Committee Co-Chair spoke at Globecom 2015. Focus on work in OIF Transport SDN Framework and joint work between OIF and ONF on Transport APIs
Jonathan Sadler, of Coriant and Vice Chair OIF Technical Committee spoke at
Globecom 2015 on the OIF's 2014 Global Transport SDN Demonstration results.
Clearing a Path to Wide-Scale Transport SDN DeploymentDeborah Porchivina
OIF vice president of marketing, Dave Brown of Alcatel Lucent, moderated a panel at Globcom 2015 discussing Transport SDN technical work in taking place in the OIF.
In this session, OIF panelists will review findings from its Global Transport SDN Prototype Demo and outline components of a tool kit aimed at clearing a path to wide-scale transport SDN deployment.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024
OIF CEI 56-G-FOE-April2015
1. OIF CEI-56G Common Electrical
Interfaces
Tom Palkert
Luxtera/MoSys
OIF PLL Vice Chair Electrical
Tom Palkert
Luxtera/MoSys
OIF PLL Vice Chair Electrical
2. Outline
Port Density Requirements
OIF CEI-56G applications
• USR (die to die in an MCM)
• XSR (Chip to optical engine/memory)
• VSR (Chip to Pluggable module)
• MR (Chip to Chip)
• LR (Backplane)
NRZ and PAM4 test and simulation results
NRZ vs PAM4 arguments
Conclusion
2 FOE 2015
Port Density Requirements
OIF CEI-56G applications
• USR (die to die in an MCM)
• XSR (Chip to optical engine/memory)
• VSR (Chip to Pluggable module)
• MR (Chip to Chip)
• LR (Backplane)
NRZ and PAM4 test and simulation results
NRZ vs PAM4 arguments
Conclusion
3. Port density requirements for Data Centers
de
RJ-45 – 48 Channels
10GBaseT = 480 Gbps
SFP+ – 48 Channels
50G = 2.7 Tbps
Channels/Bandwidth
3 FOE 2015
iPass – 160 Channels
QSFP 144 Channels
50G = 7.2 Tbps
CXP – 320 Channels
50G = 16 Tbps
4. OIF CEI Interfaces for 56G
LR
MR
Switch card
XSR
USR
4 FOE 2015
VSR
MR
XSR
USR
5. CEI-56G-USR
Key specifications
for USR
• 10mm trace length
• DC coupled
• Common clock
• Low voltage swing
HOST LSI
PCB
LSI_PKG
HOST LSI
LSI_PKG
Memory IC
MCM with memory IC
5 FOE 2015
Key specifications
for USR
• 10mm trace length
• DC coupled
• Common clock
• Low voltage swing
Optical I/O core
HOST LSI Driver
IC
Mod
Optical
I/O
LSI_PKG
Si-photonics chip
PCB
MCM with OPTICAL ENGINE
6. CEI-56G-XSR
Key specifications for XSR
• 50-100mm trace length
• DC coupled
• Common clock
• Low voltage swing
6 FOE 2015
XSR interop points
ASIC
Optical Engine or Memory device
Optical Fiber
Key specifications for XSR
• 50-100mm trace length
• DC coupled
• Common clock
• Low voltage swing
15. CEI-56G-MR
TX RX
Key specifications for MR
• 500mm trace length
• Zero or One connector
• Compliance uses COM code
15 FOE 2015
Chip to Chip interop points
AC coupling
capacitor
MR
22. LR PAM4 Measured Results
Design Con 2015 demos
22 FOE 2015
Parthasarathy_3bs_01_0315
23. Why NRZ over PAM4?
PAM4 has a 9dB SNR penalty
• 3 PAM4 eyes in the same voltage swing
as 1 NRZ eye
• VSR channel shows an 8-9dB difference
NRZ has more equalization techniques that can be used
before we move to PAM4
• Higher gain CTLE
• DFE
• TX equalization
Low cost/Low loss Printed circuit board materials are
available
23 FOE 2015
PAM4 has a 9dB SNR penalty
• 3 PAM4 eyes in the same voltage swing
as 1 NRZ eye
• VSR channel shows an 8-9dB difference
NRZ has more equalization techniques that can be used
before we move to PAM4
• Higher gain CTLE
• DFE
• TX equalization
Low cost/Low loss Printed circuit board materials are
available
24. Why PAM4 over NRZ?
As process nodes get smaller density is increasing
but not speed
• PAM designs can use lower cost semiconductor
processes
PAM operates over legacy channels
• Same baud rate as 28G NRZ
Lower loss channels may not require as much
equalization as NRZ
24 FOE 2015
As process nodes get smaller density is increasing
but not speed
• PAM designs can use lower cost semiconductor
processes
PAM operates over legacy channels
• Same baud rate as 28G NRZ
Lower loss channels may not require as much
equalization as NRZ
25. Conclusions
1) The OIF is defining solutions for the next generation
electrical interfaces
2) Both NRZ and PAM4 specifications are being
developed for CEI-56G solutions
25 FOE 2015