This document summarizes an academic paper about implementing a floating point arithmetic unit using an FPGA that follows the IEEE 754-2008 standard for decimal64 numbers. It discusses the paper's abstract, introduction on digital arithmetic and floating point formats. It also provides background on the IEEE 754 standard, describing the basic single and double precision binary formats. The summary highlights that the implemented unit can perform addition, subtraction, multiplication and division on 64-bit operands and operates at 130MHz on a Cyclone-III FPGA with 8 cycle latency.
FPGA Based Decimal Matrix Code for Passive RFID TagIJERA Editor
In this paper, Decimal Matrix Code is developed for RFID passive tag. The proposed DMC uses the decimal algorithm to obtain the maximum error detection and correction capability. The Encoder-Reuse Technique is used to minimize the area overhead of extra circuits without disturbing the complete encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The Simulation results reveals that the Decimal Matrix Code is effective than existing Matrix and Hamming odes in terms of Error Correction Capability. Xilinx ISE 14.7 Software is used for the simulation outputs. The complete design is verified and tested on Spartan-6 FPGA board. The performance of system is measured in terms of power, area and delay. The Synthesis result shows that, the power required for complete design of Decimal Matrix Code is 0.1mW with a delay of 3.109ns.
DOUBLE PRECISION FLOATING POINT CORE IN VERILOGIJCI JOURNAL
A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry
out operations on floating point numbers. The term floating point refers to the fact that the radix point can
"float"; that is, it can placed anywhere with respect to the significant digits of the number. Double
precision floating point, also known as double, is a commonly used format on PCs due to its wider range
over single precision in spite of its performance and bandwidth cost. This paper aims at developing the
verilog version of the double precision floating point core designed to meet the IEEE 754 standard .This
standard defines a double as sign bit, exponent and mantissa. The aim is to build an efficient FPU that
performs basic functions with reduced complexity of the logic used and also reduces the memory
requirement as far as possible.
FPGA Based Decimal Matrix Code for Passive RFID TagIJERA Editor
In this paper, Decimal Matrix Code is developed for RFID passive tag. The proposed DMC uses the decimal algorithm to obtain the maximum error detection and correction capability. The Encoder-Reuse Technique is used to minimize the area overhead of extra circuits without disturbing the complete encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The Simulation results reveals that the Decimal Matrix Code is effective than existing Matrix and Hamming odes in terms of Error Correction Capability. Xilinx ISE 14.7 Software is used for the simulation outputs. The complete design is verified and tested on Spartan-6 FPGA board. The performance of system is measured in terms of power, area and delay. The Synthesis result shows that, the power required for complete design of Decimal Matrix Code is 0.1mW with a delay of 3.109ns.
DOUBLE PRECISION FLOATING POINT CORE IN VERILOGIJCI JOURNAL
A floating-point unit (FPU) is a math coprocessor, a part of a computer system specially designed to carry
out operations on floating point numbers. The term floating point refers to the fact that the radix point can
"float"; that is, it can placed anywhere with respect to the significant digits of the number. Double
precision floating point, also known as double, is a commonly used format on PCs due to its wider range
over single precision in spite of its performance and bandwidth cost. This paper aims at developing the
verilog version of the double precision floating point core designed to meet the IEEE 754 standard .This
standard defines a double as sign bit, exponent and mantissa. The aim is to build an efficient FPU that
performs basic functions with reduced complexity of the logic used and also reduces the memory
requirement as far as possible.
RTL Verification and FPGA Implementation of 4x4 Vedic MultiplierMohd Esa
The objective of this paper is to study 4x4 Vedic multiplier.
Multiplication is an important fundamental function in arithmetic operations.
Vedic multiplier using Urdhva-Tiryagbyam sutra is predominant in
performance evaluation of parameters such as power, area & delay. This paper
presents design, verification and FPGA implementation of Vedic multiplier.
Verification is carried out in Questa Sim 10.4e using System Verilog HVL and
design is carried out in Xilinx ISE Design Suite 14.7 using Verilog HDL
environment
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
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ASSIGNMENT BRIEF
Qualification BTEC Level 5 HND Computing and Systems Development Unit number and
title Unit 51: Computer Systems Architecture Assignment issued Assignment due Assessor name Assignment title Computer Systems
RTL Verification and FPGA Implementation of 4x4 Vedic MultiplierMohd Esa
The objective of this paper is to study 4x4 Vedic multiplier.
Multiplication is an important fundamental function in arithmetic operations.
Vedic multiplier using Urdhva-Tiryagbyam sutra is predominant in
performance evaluation of parameters such as power, area & delay. This paper
presents design, verification and FPGA implementation of Vedic multiplier.
Verification is carried out in Questa Sim 10.4e using System Verilog HVL and
design is carried out in Xilinx ISE Design Suite 14.7 using Verilog HDL
environment
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Computer systems architecture assignment/tutorialoutletPittock
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ASSIGNMENT BRIEF
Qualification BTEC Level 5 HND Computing and Systems Development Unit number and
title Unit 51: Computer Systems Architecture Assignment issued Assignment due Assessor name Assignment title Computer Systems
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...jmicro
This paper presents floating point multiplier capable of supporting wide range of application domains like scientific computing and multimedia applications and also describes an
implementation of a floating point multiplier that supports the IEEE 754-2008 binary interchange format with methodology for estimating the power and speed has been developed. This Pipelined vectorized floating point multiplier supporting FP16, FP32, FP64 input data and reduces the area, power, latency and increases throughput. Precision can be implemented by taking the 128 bit input operands.The floating point units consumeless power and small part of total area. Graphic Processor Units (GPUS) are specially tuned for
performing a set of operations on large sets of data. This paper also presents the design of a Double precision floating point multiplication algorithm with vector support. The single precision floating point multiplier is having a path delay of 72ns and also having the operating frequency of 13.58MHz.Finally this implementation is done in Verilog HDL using Xilinx ISE-14.2.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An Area Efficient Vedic-Wallace based Variable Precision Hardware Multiplier ...IDES Editor
The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design and Analysis of High Performance Floating Point Arithmetic Unitijtsrd
A floating point arithmetic unit designed to perform operations on floating point numbers as well as fixed point numbers. Floating point numbers can support a much wider range of values in comparison to fixed point representation. Floating Point units are mainly used in high speed objects recognition system, high performance computer systems, embedded systems and mobile applications. To represent very small values or very large values, large range is required as the integer representation is no longer appropriate to represent these numbers so these values can be represented by using floating point representation that is based on the IEEE 754 standard. The proposed floating point arithmetic unit is designed using single stage implementation. Due to single stage implementation the complex logic operations which consist of various multiple numbers of stages are converted into single stage implementation. So by using single stage implementation the time requires to reach data from input to output becomes less. The proposed unit is designed in VHDL, simulated in Questa Sim simulator and implemented on vertex 7 FPGA. Naresh Kumar | Onkar Singh | Harjit Singh "Design and Analysis of High Performance Floating Point Arithmetic Unit" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-1 , December 2020, URL: https://www.ijtsrd.com/papers/ijtsrd38049.pdf Paper URL : https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/38049/design-and-analysis-of-high-performance-floating-point-arithmetic-unit/naresh-kumar
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
1. Raja Gopal Surineedi, G.S.Siva Kumar, P.Sunitha / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1221-1225
Arithmetic Unit Implementation Using A FPGA IEEE-754-2008
Decimal64 Floating-Point
Raja Gopal Surineedi, G.S.Siva Kumar, P.Sunitha
M.Tech student, Associate professor, Associate professor,
Pragati engineering college, surampalem,
Abstract:
This paper describes the FPGA on floating point numbers. Each operation can be
implementation of a Decimal Floating Point selected by a particular operation code. Synthesis of
(DFP) ALU (Arithmetic logic unit). The design the unit for the FPGA board has been done using
performs addition, subtraction, multiplication QUARTUS-II.
and division on 64-bit operands that use the Implemented arithmetic unit is a part of a
IEEE 754-2008 decimal encoding of DFP computer system specially designed to carry out
numbers and is based on a fully pipelined circuit. operations on floating point numbers. Some systems
The design presents a novel hardware for pre- (particularly older, microcode-based architectures)
signal generation stage and an enhanced version can also perform various transcendental functions
of previously published leading zero stage. The such as exponential or trigonometric calculations,
design can operate at a frequency of 130 MHZ on though in most modern processors these are done
a CYCLONE-III with a latency of 8 cycles. The with software library routines.
presented DFP adder/subtractor supports
operations on the decimal64 format and it is II. Floating Point Formats
easily extendable for the decimal128 format. To Several different representations of real
our knowledge, this is the first hardware FPGA numbers have been proposed, but by far the most
design for Floating point arithmetic unit based on widely used is the floating-point representation.
IEEE 754-2008 using decimal64 encoding. Floating-point representations have a base b (which
is always assumed to be even) and a precision p. If b
Keywords - About five key words in alphabetical = 10 and p = 3 then the number 0.1 is represented as
order, separated by comma 1.00 × 10-1
If b = 2 and p = 22, then the decimal
I. INTRODUCTION number 0.1 cannot be represented exactly but is
Digital arithmetic operations are very approximately 1.100110011001100110011×2-4. In
important in the design of digital processors and general, a floating point number will be represented
application-specific systems. Arithmetic circuits as ± d.dd… d × be, where d.dd… d is called the
form an important class of circuits in digital systems. Significand and has p digits. More precisely ± d0 d1
With the remarkable progress in the very large scale d2 ... dp-1 × be represents the number. The term
integration (VLSI) circuit technology, many floating-point number will be used to mean a real
complex circuits, unthinkable yesterday have number that can be exactly represented in the format
become easily realizable today. Algorithms that under discussion. Two other parameters associated
seemed impossible to implement now have attractive with floating-point representations are the largest
implementation possibilities for the future. This and smallest allowable exponents, emax and emin.
means that not only the conventional computer Since there are be possible significands, and emax -
arithmetic methods, but also the unconventional emin + 1 possible exponents, afloating-point number
ones are worth investigation in new designs. The can be encoded in bits, where the final +1 is for the
notion of real numbers in mathematics is convenient sign bit. The most common situation is illustrated by
for hand computations and formula manipulations. the decimal number 0.1. Although it has a finite
However, real numbers are not well-suited for decimal representation, in binary it has an infinite
general purpose computation, because their numeric repeating representation. Thus when b = 2, the
representation as a string of digits expressed in, say, number 0.1 lies strictly between two floating-point
base 10 can be very long or even infinitely long. numbers and is exactly representable by neither of
Examples include π, e, and 1/3. In this thesis an them. A less common situation is that a real number
arithmetic unit based on IEEE standard for floating is out of range, that is, its absolute value is larger
point numbers has been implemented on ALTERA than b ×bemax or smaller than 1.0 × bemin
cyclone -III FPGA Board. The arithmetic unit
implmented has a 64-bit processing unit which
allows various arithmetic operations such as,
Addition, Subtraction, Multiplication, Division and,
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2. Raja Gopal Surineedi, G.S.Siva Kumar, P.Sunitha / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1221-1225
III. IEEE 754 Standard for Binary C. Double Precision
Floating-Point Arithmetic: The double precision format helps
The IEEE 754 Standard for Floating-Point overcome the problems of single precision floating
Arithmetic is the most widely-used standard for point. Using twice the space, the double precision
floating-point computation, and is followed by many format has an 11-bit excess-1023 Precision exponent
hardware (CPU and FPU) and software and a 53 bit mantissa (with an implied H.O. bit of
implementations. one) plus a sign bit. This provides a dynamic range
The standard specifies: of about 10±308 and 14-1/2 digits of precision,
Basic and extended floating-point number sufficient for most applications. Double precision
formats floating point values take the form shown in
Add, subtract, multiply, divide, square Figure2.2.[3]
root, remainder, and compare operations
Conversions between integer and floating-
point formats
Conversions between different floating-
point formats
When it comes to their precision and width
in bits, the standard defines two groups:
basic and extended format. [3,4,8]
A. Formats
The standard defines five basic formats,
named using their base and the number of bits used
to encode them. There are three binary floating-point
formats (which can be encoded using 32, 64, or 128
bits) and two decimal floating-point formats (which
can be encoded using 64 or 128 bits). The first two
binary formats are the „Single Precision‟ and
„DoublePrecision‟ formats of IEEE 754-1985, and
the third is often called 'quad'; the decimal formats Table 2.2 Representation of Single Precision floating
are similarly often called 'double' and 'quad'. point numbers
In order to help ensure accuracy during
long chains of computations involving double
precision floating point numbers, Intel designed the
extended precision format. The extended precision
format uses 80 bits. Twelve of the additional 16 bits
are appended to the mantissa; four of the additional
bits are appended to the end of the exponent. Unlike
the single and double precision values, the extended
precision format does not have an implied H.O. bit
which is always one. Therefore, the extended
precision format provides a 64 bit mantissa, a 15 bit
excess-16383 exponent, and a one bit sign. The
format for the extended precision floating point
value is shown in Figure 2.3.[3,4,8]
D. Exceptions
The IEEE standard defines five types of
B. Single Precision exceptions that should be signalled through a one bit
The most significant bit starts from the left. status flag when encountered. Some arithmetic
The three basic components are the sign,exponent, operations are invalid, such as a division by zero or
and mantissa square root of a negative number. The result of an
invalid operation shall be a NaN (Not a number).
There are two types of NaN, quiet NaN (QNaN) and
signaling NaN (SNaN). They have the following
format, where s is the sign bit:
QNaN = s 11111111 10000000000000000000000
SNaN = s 11111111 00000000000000000000001
The result of every invalid operation shall be a NaN
Fig 1.Floating representation of single precision
string with a QNaN or SNaN exception. The SNaN
string can never be the result of any operation, only
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3. Raja Gopal Surineedi, G.S.Siva Kumar, P.Sunitha / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1221-1225
the SNaN exception can be signaled and this IV. DESIGN OF ARITHMETIC UNIT
happens whenever one of the input operand is a Decimal arithmetic plays a key role in
SNaN string otherwise the QNaN exception will be many commercial and financial applications, which
signaled. The SNaN exception can for example be process decimal values and perform decimal
used to signal operations with uninitialized rounding. However, current software
operands, if we set the uninitialized operands to implementations are prohibitively slow [1],
SNaN. prompting hardware manufacturers such as IBM to
E. Range of Floating Point Numbers add decimal floating point (DFP) arithmetic support
By allowing the radix point to be to their microprocessors [2]. Furthermore, the IEEE
adjustable, floating-point notation allows has developed the newly IEEE 754-2008 [3]
calculations over a wide range of magnitudes, using standard for Floating-Point Arithmetic adding the
a fixed number of digits, while maintaining good decimal representation to the IEEE 754-1985
precision. For example, in a decimal floating-point standard. There are several works focused on fixed-
system with three digits, the multiplication that point addition [4, 5]. For example, in [4, 5], Busaba,
human would write as and Haller propose combined decimal and binary
0.12 × 0.12 = 0.0144 Would be expressed as adders using pre-sum and pre-selection logic. Only a
(1.2 × 10^−1) × (1.2 × 10^−1) = (1.44 × 10^2) few previous recent papers focused on decimal
In a fixed-point system with the decimal floating-point addition [6-8]. The proposed adder by
point at the left, it would be 0.120 × 0.120 = 0.014 A Cohen et al. [8] and Bohlender et al. [6] have long
digit of the result was lost because of the inability of latencies and produces one result digit each cycle. In
the digits and decimal point to 'float' relative to each [7] presents the first IEEE 754 decimal floating point
other within the digit string. The range of floating- adder. Nevertheless, recently appears the first
point numbers depends on the number of bits or publications in decimal arithmetic applications on
digits used for representation of the significand (the FPGA [9]. Several hardware designs were
significant digits of the number) and for the synthesized using other platforms than FPGA [10],
exponent. On a typical computer system, a 'double this is why it is believed that it can be one of the first
precision' (64-bit) binary floating point number has a implementation on FPGA for addition/subtraction
coefficient of 53 bits (one of which is implied), an using decimal64 encoding. A recent work [9]
exponent of 11 bits, and one sign bit. Positive presents a DFP adder for FPGA but using Binary
floating-point numbers in this format have an Integer Decimal (BID) encoding, whose results will
approximate range of 10^−308 to 10^308 (because be used in our comparisons. Because of the BID
308 is approximately 1023 × log10 (2), since the adder occupies less area [9] than our proposed
range of the exponent is [−1022, 1023]). The design, it may be argued that the BID format is well
complete range of the format is from about −10^308 suited for hardware implementation but considering
through +10^308.. the latency-area tradeoff.
The number of normalized floating point numbers in
a system F(B, P, L, U) (where B is the base of the 1) A .Floating Point Number System
system, P is the precision of the system to P Every real number can be approximated by
numbers, L is the smallest exponent representable in a floating point number in the IEEE 754 standard
the system, and U is the largest exponent used in the [ANSI 85] as long as that number is within specific
system) is: range. The floating point number format is based on
2 * (B - 1) * B^(P-1) * (U - L + 1) + 1. The one is scientific notation with limited size for each field.
added because the number could be zero. There is a For a normalized floating point number in the IEEE
smallest positive normalized floating-point number, 754 single precision standard where the integer part
Underflow level = UFL = B^L which has a 1 as the is always equals to 1, the sign bit is 1 bit in size. The
leading digit and 0 for the remaining digits of the integer part is omitted as it is always equals to 1. The
mantissa, and the smallest possible value for the size of fraction part is 23 bit and the size of exponent
exponent. There is a largest floating point number, is 8 bit. The base is always equal to 2 and the total
Overflow level = OFL = B^ (U + 1) * (1 - B^ (-P)) size of a single precision floating point number is 32
which has B - 1 as the value for each digit of the bits. In general, an IEEE 754 floating point number
mantissa and the largest possible value for the F can be expressed as follows: where s stands for the
exponent. Any number larger than OFL cannot be sign bit, f stands for the fraction and e stands for the
represented in the given floating-point system and biased exponent. In order to express a negative
no number smaller than the UFL can be represented exponent, there is an exponent bias b associated with
in the floating point system. the exponent field. The actual exponent is the value
The IEEE standard goes further than just of the exponent field minus the bias. The value of
requiring the use of a guard digit. It gives an bias depends on the size of exponent e size as in
algorithm for addition, subtraction, multiplication, equation 2.2. The term significand represents 1.f in
division and square root, and requires which integer field and fraction field are packed
together.
1223 | P a g e
4. Raja Gopal Surineedi, G.S.Siva Kumar, P.Sunitha / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1221-1225
Fig 4.Basic modules of arithmetic operation
V.CONCLUSION
Several different representations of real
numbers have been proposed, but by far the most
widely used is the floating-point representation.
Fig 2.Area utilization report.
Floating-point representations have a base b (which
is always assumed to be even) and a precision p.
2) Arithmetic operations
Finally we implement all basic arithmetic operations
The outline of the paper is as follows. In the
involved in any DSP applications in Floating point
next Section, it is described the background
.With the help of this FPU core we can do any kind
information on decimal floating-point. It describes
of DSP applications. Here we achieve high speed of
the challenge of adding decimal64 encoded
130MHz by various pipelining stages.
numbers, and presents the technique and theory for
addition and subtraction. Section 4 presents
synthesis results for our proposed adder and
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5. Raja Gopal Surineedi, G.S.Siva Kumar, P.Sunitha / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1221-1225
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