Wirebond technology is discussed, along with its pros and cons. Wirebonding allows interconnections between integrated circuits and their packaging during device fabrication using gold, aluminum, silver or copper wires. While it can be used at high frequencies and reduces manufacturing costs, it requires a larger chip footprint and longer interconnect lengths. Market trends show increasing reliability and a shift to ball bonding as devices shrink. Direct chip attachment and chip scale packaging technologies are also described, along with their pros, cons, and trends towards higher density and performance packaging solutions. Flip chip packaging is explained, noting advantages like size reduction but challenges like lack of easy replacement and need for flat mounting surfaces. An iPhone bill of materials lists component costs, and discusses the A9 chip

1. Name: Rachit Patel
Fundamentals of electronic
packaging ME 5352
ID no: 1001103811

2. QuesDon 1
What is Wirebond technology?
Please discuss the pros and cons of the
technology.
Also discuss the technology market trends in the
last 20 years of wirebonding.

3. Wirebond technology
• Wire bonding is the method of making
interconnecDons between an integrated
circuit (IC) or other semiconductor device
and its packaging during semiconductor
device fabricaDon.
• It can be used to connect an IC to other
electronics or to connect from one printed
circuit board to another.
• Gold, Aluminium, Silver and Copper are
the materials used in wire bonding.

4. Pros of wirebond
• Wirebond can be used at frequencies above
100GHz if properly designed.
• It is used to assemble vast majority of
semiconductor packages.
• Simple handling of complex circuits.
• ReducDon in manufacturing costs.
• Flexibility in terms of chip, housing and substrate
geometry.
• Saves space.
• Various applicaDons such as sensor,
measurement, industrial and medical technology.

5. Cons of wirebond
• Larger footprint required for chip to package
interconnecDon
• Slower interconnecDon rates due to point to
point processing of each wirebond
• Long chip to package interconnecDon lengths,
degrading electrical performance

6. Market trends
• In the past, a large proporDon of all
semiconductor device field failures were
caused by wire bonds and the number of
known failure mechanism were limited.
• Through the improvement of bonding
technology, the reliability of wire bonds is
increasing, as is our understanding of failure
modes.

7. ConDnued
• There is two kinds of wire bonds
– Wedge bonds
– Ball bonds
In recent study, it shows that 90% of all electronic
packages and assemblies are produced using ball
bonds and 10% are produced with wedge bonds.
Increase in uDlizaDon of ball bonding is expected as
semiconductor devices increase in funcDonality and
decrease in size causing smaller bond pads and
closer bond pad spacing.

8. QuesDon 2
What is Direct Chip A_achment(DCA)
technology?
Please discuss the pros and cons of the
technology.
Also discuss the technology market trends in the
last 10 years of DCA.

9. Direct chip a_achment
• It refers to flip chip a_ach of a bare die to a
laminate substrate.
• It is disDnguished from chip on board by the
use of flip chip bonding rather than
wirebonding.

10. Pros of DCA
• High component density
• Less free-place in the circuit
• Less cost
• Fast subsDtuDon of the component
• More reliability because of be_er dissipaDon
heat
• Less welds
• Faster Dme to market
• Be_er protecDon against the reserve engineering

11. Cons of DCA
• EncapsulaDon is not consistent

12. Market trends
• Speed: Market pressures are driving package costs down and, as a result,
equipment suppliers are expected to provide improved performance machines, as
die bond speed has a direct correlaDon to the cost of a package. The faster the
machine, the lower the capital equipment depreciaDon cost is a_ributed to the
package.
• Improved accuracy: As package sizes shrink, the bond pad becomes smaller in
proporDon to the chip to save space on the board. Die a_ach accuracy is
important and it can be complex to achieve. Also, as wire bond pitch becomes
smaller, accurate die placement is required to enable an accurate and ultra fine
pitch (50 µm or be_er) wire placement
• Stacked die and mulDchip modules (MCMs): Rather than having mulDple
integrated circuits (ICs) with various funcDons on a board, MCMs are created when
mulDple die with different funcDons are placed on the same module; this creates a
sophisDcated package with excellent performance capabiliDes. MCMs are typically
made by placing the die on top of each other or right next to each other on the
same module using epoxy and soe solder processes. The modules are used in a
mulDtude of different applicaDons varying from communicaDons devices to power
devices.

13. conDnued
• Wider bond range: To save on material costs and cut
out unnecessary cycle Dme, many package designers
specify substrates in array form (Figure 6). The result is
a need for wider bond areas. This includes die bonding
and other downstream process steps.
• 300 mm: At some point, front-end semiconductor
manufacturers` use of 300 mm wafers will require
packaging to accommodate the large wafer size. This
poses a quesDon of how to handle large wafers, while
minimizing the footprint of the machine. Wafers this
size will be very delicate, and handling them without
causing damage will be an issue for die bonder
equipment designers.

14. QuesDon 3
What is Chip Scale Packaging(CSP) technology?
Please discuss the pros and cons of the
technology.
Also discuss the technology market trends in the
last 10 years of DCA.

15. Chip scale packaging
• It is a type of integrated circuit package.
• Originally, it was the acronym for chip-size
packaging.
• It has 5 types:
– Customized leadframe based CSP
– Flexible substrate based CSP
– Flip chip CSP
– Rigid substrate based CSP
– Wafer level redistribuDon CSP

16. Pros of CSP
• Lighter weight
• Thinner package profile
• Economical
• No under fill required
• Shortened manufacture cycle Dme
• Ease of package filling

17. Cons of CSP
• High input/output which requires very small
solder balls on a very Dght pitch
• Requires high density PCB to interconnect
• Expensive
• Thermal management is difficult
• Change in infrastructure
• Moisture sensiDvity

18. Market trends
• Chip products are designed for high performance
networking applicaDons. These kind of chips are
manufactured by companies such as Cisco,Altera, Huawei
and IBM. These chips are 2.5D chip products which were
iniDally viewed as short term bridge to full 3D integrated
circuits. Now, it is believed that 2.5D and 3D will coexist.
2.5D is suited for Xilinx’s virtex 7 devices that are used in
network applicaDons. For large amount of memory
requirement, 3D IC technology is implemented. SoluDons
combining 2.D and 3D technologies where logic chip might
be mounted next to stack of tsv-interconnected memory
chips, possibly even with supporDng analog and passive
components, on a silicon interposer having TSVs to connect
all the chips together.

19. conDnued
• These products drew a lot of a_enDon from the industry in 2013.
However, CSP is not a new technology. LED manufacturers had already
invested R&D resources early on. As the technology and market matures,
one could say that 2013 was the year of CSP components. Large
manufacturers such as Toshiba, Cree, and Philips Lumileds as well as major
Taiwanese LED chip manufacturers Epistar, FOREPI, TSMC Solid State
LighDng, Lextar, and package manufacturer Unistars were the first to
develop CSP products. Korean manufacturers and Chinese manufactures
are also compeDng to enter this market.
• CSP products use flip-chips as a base and eliminate the wire bonding and
lead frames, which allows the products to have luminosity on five sides
and at wider angles. It also allows them to reduce the size. CSP can also be
referred to as package free. Package free products name and definiDon
has sparked discussions in the market with each manufacturer having
their own perspecDve.

20. QuesDon 4
What is Flip Chip Packaging(FCP) technology?
Please discuss the pros and cons of the
technology.
Also discuss the technology market trends in the
last 10 years of FCP.

21. Flip chip packaging
• It is a method for interconnecDng
semiconductor devices such as IC chips and
microelectromechanical systems(MEMS), to
external circuitry with solder bumps that have
been deposited onto the chip pads.

22. Pros of FCP
• ResulDng completed flip chip is much smaller
than a tradiDonal carrier-based system.
• The chip sits directly on the circuit board, and
is much smaller than the carrier both in area
and height.
• Reduced inductance which allows higher-
speed signals.
• Conducts heat be_er.
• Be_er power distribuDon

23. Cons of FCP
• It is not suitable for easy replacement or
manual installaDon due to lack of carrier.
• It requires very flat surface to mount which is
not always possible, or someDmes difficult to
maintain as the boards heat and cool.
• Thermal expansion of the chip must be
matched to the supporDng board because the
short connecDons are sDff.
• Expensive

24. Cons of FCP
• Underfill material acts as an intermediate
between the difference in coefficient of
thermal expansion of the chip and board.

25. Market trends
• There has been a long period of their use in flip chip assembly. With over 40 years
development, solder flip chip assembly has become the most mature process.
However, according to European RoHS, lead must be removed from most
electronic packages and circuit board assembly by 1 July 2006.
• Although high lead containing solders used in today’s flip chip packages are
currently exempted from this restricDon, many leading companies have already
commi_ed themselves to developing alternaDve flip chip bump systems for next-
generaDon electronic packaging. It is widely believed that the pressure to remove
lead from all electronic packages and assemblies will conDnue in the future from
both legislaDve and compeDDve sides. Flip chip assembly has to take up this
challenge.
• With the convergence of products, product funcDonality has never been more
demanding. Time-to-market is also more criDcal than ever. In order to be a viable
packaging method for next-generaDon electronics, flip chip technology must be
able to address these areas. Apart from quality and cost, green manufacturing is
equally important. The worldwide trend towards eliminaDng lead in electronic
products has a profound impact on flip chip assembly. Lead-containing solders
(eutecDc Dn-lead or high-lead alloys) are convenDonal flip chip bump materials.

26. conDnued
• Although high lead containing solders used in
today’s flip chip packages are currently exempted
from this restricDon, many leading companies
have already commi_ed themselves to
developing alternaDve flip chip bump systems for
next-generaDon electronic packaging. It is widely
believed that the pressure to remove lead from
all electronic packages and assemblies will
conDnue in the future from both legislaDve and
compeDDve sides. Flip chip assembly has to take
up this challenge.

27. QuesDon 5
Find the “Bill of Materials”of any iPhone.
Discuss the components and corresponding
packaging.

28. iPhone 6s price breakdown
Components Cost
ApplicaDon + baseband
processors
$58.50
Ba_ery $3.50
Camera $19.00
Radio $23.50
Touchscreen/Display $42.50
Memory $23.50
Mechanicals/Housings $28.00
Miscellaneous $15.50
Power management/Audio $7.50
Sensor $5.50
Test/Assembly/SupporDng
Materials
$18.00
Total $245.00

29. A9 chip and Packaging
• There would be a “new transistor architecture” in the A9,
which does sound like a euphemism for a switch to finFET.
In the A9, we have two blocks of SRAM in the lower centre,
a dual-core CPU at the lower right, and possibly a six-core
GPU at the upper right. And of course the M9 moDon
coprocessor is now apparently integrated onto the chip.
• If one of those SRAM blocks is 4 MB, then we can take a
guess as to the die size. In the A8 that block was 4.9 mm2,
so with a 80% linear shrink (64% area shrink) it would be
3.1 mm2, or with a 70% shrink it would be 2.4 mm2. If we
compare the block size with the whole die, that gives us
respecDve die sizes of 93 mm2 or 71 mm2, although given
the fuzzy edges in the image, there is room for error in
those numbers (the A8 was 89 mm2).

30. Components and packaging
Packaging components
• Apple A9 Processor - advanced Package-on-Package (PoP) structure
• Qualcomm Snapdragon - mulD-chip, smallest pitch on the board
• Dialog Power management - largest ball count WLP (380-ball)
• Wi-Fi & Bluetooth combo module
• Power Amplifier Module
Sensors:
• Fingerprint sensor - new generaDon: new packaging, new processes (includes TSV)
• eCompass - new supplier, custom product which has never been used in a
smartphone
• Microphone - new process improving the SNR
• 6-Axis IMU - new reference, custom design
• Ambient light sensor - new reference, wafer-level package
• Front and rear camera modules
• Flash LED - flip-chip integraDon