Hardware Architecture for Calculating LBP-Based Image Region Descriptors

Introduction
The implemented algorithm
The implemented system
Results
Conclusions
Hardware Architecture for Calculating LBP-Based
Image Region Descriptors
Michał Fularz1 Marek Kraft1
1Poznań University of Technology
Institute of Control and Information Engineering
May 27, 2015
M. Fularz, M. Kraft A Hardware Architecture for Calculating LBP-Based...

Introduction
Results
Conclusions
Table of contents
Goal and motivation
1 Introduction
Table of contents
Goal and motivation
2 The implemented algorithm
Non-redundant uniform local binary patterns (NRULBP)
Region descriptor formation
3 The implemented system
System architecture
NRULBP computation
Local histogram computation
4 Results
Summary of used resources
Processing speed
5 Conclusions

Introduction
Results
Conclusions
Table of contents
Goal and motivation
Goal
To implement an eﬃcient hardware architecture, enabling the
computation of LBP-based image region descriptors with
corresponding occurrence histograms
Motivation
LBP-based descriptors can be used in a wide range of
computer vision applications
Computation of features as well as their distributions in the
form of the local occurrence histograms for the whole image is
a compute-intensive task

Introduction
Results
Conclusions
Table of contents
Goal and motivation
Sample applications of LBP-based descriptors

Introduction
Results
Conclusions
Descriptor formation
Regular LBP is formed based on gray level value comparison
operations in 8-neighborhood, giving rise to 256 diﬀerent LBP
variants
Over 90% of LBPs are ones with less than 3 transitions in the
binary vector - so called uniform LBPs (ULBP) with 59
diﬀerent variants
Further reduction with non-redundant ULBPs - ULBPs and
their binary negation (e.g. 0b00000110 - 0b11111001)
considered the same, reducing the number of variants to 30

Introduction
Results
Conclusions
LBPs or their variants can be used to construct region descriptors:
histograms of descriptors are computed within smaller cells
the cells form a grid whose dimensions correspond to the
expected dimensions of described object
individual histograms are concatenated to form the full
descriptor

Introduction
Results
Conclusions
System architecture
NRULBP computation
Block diagram of the coprocessor
The input data are the image pixels in progressive scan mode

Introduction
Results
Conclusions
System architecture
NRULBP computation
The input pixels are arranged to form a 3 × 3 window

Introduction
Results
Conclusions
System architecture
NRULBP computation
Block diagram of the coprocessor - NRULBP computation
the raw LBP value is computed based on the results from a set
of comparators
the NRULBP is computed from the raw value using a lookup
table

Introduction
Results
Conclusions
System architecture
NRULBP computation
Block diagram of the coprocessor - local histogram computation
The resulting NRULBP stream is arranged as a 50 × 1 window,
enabling parallel computation of local histograms

Introduction
Results
Conclusions
System architecture
NRULBP computation
Block diagram of the coprocessor - local histogram computation
local histogram modiﬁed based on the entry and exit histogram
fully pipelined and systolic approach

Introduction
Results
Conclusions
System architecture
NRULBP computation
Block diagram of the coprocessor - data arrangement
Final spatial arrangement ensured by the cell delay blocks

Introduction
Results
Conclusions
System architecture
NRULBP computation
Descriptor type, cell size and arrangement can be easily changed

Introduction
Results
Conclusions
Processing speed
Summary of programmable logic resources used for implementation
The designations are: FF – ﬂipﬂops, LUT – lookup tables, BRAM –
BlockRAM memory blocks. The total amount of resources available
in example target devices is given for reference in the bottom row
of the table.
FF LUT BRAM
Resource utilization used % of avail. used % of avail. used % of avail.
10 × 5 13816 12,98 23223 46,63 26 18,57
5 × 5 6966 6,55 12789 24,04 13 9,29
6 × 3 6536 6,14 12163 22,86 16 11,07
XC7Z020 106400 53200 140
XC7Z045 437200 218600 545

Introduction
Results
Conclusions
Processing speed
Processing speed
Tests were performed using a 10 × 5 grid of 5 × 5 cells on all image
pixels. The power consumption is well below 3W. Clock frequency
is 75MHz.
Number of frames per second that the proposed hardware
accelerator can process for diﬀerent image sizes:
resolution processing time [ms] frames per second
640 x 480 3,84 260,4
1280 x 720 11,52 86,8
1920 x 1080 25,92 38,6
PC implementation achieves 1,5 FPS on VGA resolution images.

Introduction
Results
Conclusions
Conclusions
The system oﬀers high performance at low power in a small
footprint
The architecture can be easily adapted to a range of tasks
requiring various cell size or cell grid size. Change of descriptor
type (e.g. to HoG) requires more work, but is also possible
Future work will be focused on integrating the implemented
architecture with a coprocessor performing a classiﬁcation task

Introduction
Results
Conclusions
Thank you for your attention
The project was ﬁnanced by the National Science Center under the contract decision number
DEC-2011/03/N/ST6/03022,
New concept of the network of smart cameras with enhanced autonomy for automatic surveillance
systems

Hardware Architecture for Calculating LBP-Based Image Region Descriptors

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