This paper presents the design and development of a customized low-cost GPS receiver to be tested on the PNSS-1 microsatellite. The GPS receiver is optimized to meet PNSS-1 requirements including positional accuracy better than 20m and update rate greater than 1 Hz. The receiver uses COTS components including an FPGA and consists of a front-end module and processing system. The front-end receives and digitizes GPS signals, while the processing system performs correlation, decoding, tracking and acquisition to determine satellite position and velocity information. Preliminary results suggest the design meets PNSS-1 specifications using space-graded components.

1. Design and Development of GPS Receiver for PNSS-1
Asif Ali Khan, Mazhar Abbas, Zainab Jamil
Dept. of Computer Systems Engineering, UET, Peshawar,
Pakistan
Asif.ali@nwfpuet.edu.pk, mazhar4793@gmail.com,
angelzaini12@gmail.com
Salim Ullah, Laiq Hasan, Naila Rehman
Dept. of Computer Systems Engineering, UET, Peshawar,
Pakistan
saleemullah@nwfpuet.edu.pk, laiqhasan@nwfpuet.edu.pk,
nailarehman74@yahoo.com
This paper presents a customized low cost Global Positioning
System (GPS) receiver. The space agency of Pakistan, Space and
Upper Atmosphere Research Commission (SUPARCO) will test
it on board in an educational microsatellite named Pakistan
National Student Satellite One (PNSS-1). The proposed GPS
receiver has specifically been optimized and designed to meet
PNSS-1 requirements and functional specifications. These
functional requirements include: determination of satellite’s
velocity and orbital position, time information, positional
accuracy better than 20m, update rate greater than 1 Hz and
velocity accuracy better than 1 m/s. Commercial Off The Shelf
(COTS) equipments are used in order to harness the
performance of the cutting-edge technologies. The use of Space-
graded FPGA, virtex-5, as a System-On-Chip(SOC) does not only
reduce the power consumption but also provides a fault-tolerant,
reconfigurable and computationally efficient solution. The GPS
receiver mainly consists of two parts: Front end module and
processing system. The front end module senses the GPS L1
signal through antenna, passes it through different filters and
digitizes it. The processing system correlates the received signal
with the locally generated carrier code using FPGA and performs
other operations like decoding, tracking and acquisition using
soft-core processor MicroBlaze.
Keywords—Global Positioning System (GPS), COTS FPGAs,
Micro Blaze, SOC, Coarse/Acquisition
I. INTRODUCTION
Humans have a curiosity for knowing the unknown and that
makes them to explore the universe. Exploring the universe
demands navigation tools. Early on, humans used stars to
navigate before the compass came. Now the era is of digital
communication and humans have replaced stars with artificial
satellites. Among other useful functions of satellites, one of its
most important functions is to provide global positioning
system data for navigation purpose.
The first of its kind, Navigation System with Timing and
Ranging Global Positioning System (NAVSTAR) GPS was
developed by the U.S. Department of Defense to assist its
ground navigation systems. It needed 24 satellites to find the
location of any receiver on or above earth. On 22nd February
1978, first GPS satellite was launched into orbit and currently
there are 31 operational satellites in 6 different orbits at a
height of 20,180 km. These orbits are at inclination of 55
degree to equator so that at least 4 satellites are always
available for finding the exact position of any GPS receiver
using 3-D trilateration. The satellites complete their orbits in
approximately 12 hours.
GPS satellites communicate with GPS receivers using a
radio signal of L1 frequency band (1575.42MHz) and L2
frequency (1227.60MHz). It contains time and position
information of the satellite in orbit. The receiver decodes it,
finds the time delay to the receiver and using the velocity of
light, the distance (pseudo-range) between satellite and the
location of receiver can be found.
In this paper, we propose a customized and low cost GPS
receiver for PNSS-1. The proposed module not only provides
the orbital position and velocity information of the satellite but
is also responsible for time and telemetry information. The
rest of the paper is organized as follows: Section II provides a
brief review of the work already done in this area. Section III
describes the design and implementation of the proposed GPS
receiver followed by some preliminary results presented in
section IV. Section V concludes the paper and describes the
possible future work.
II. RELATED WORK
GPS receivers have got many applications and are
everywhere these days. Starting from a handheld device to a
spacecraft, all use GPS receivers for location tracking and
various other purposes. Commercial and academic GPS
receivers are designed either hardware or software based. For
instance, in [1], an FPGA and MicroBlaze based GPS receiver
is presented. FPGA is used to generate C/A and carrier code
while MicroBlaze is used for implementing tracking and
acquisition algorithms. The parallel implementation of
correlator on FPGA not only improved the performance
efficiency but also gave accurate results.
In [2], a real time hardware based GPS receiver has been
implemented using Altera DE2 FPGA board and GPS Demo
Board using RF front end Antenna with it. Two types of data
were received, location information and time information from
the transmitter. In GPS demo board, there is Micro-Nav
(uNav) 8130 baseband Processor that decodes the GPS signal
and makes data packets in the required format.
Software based GPS receivers are also available and are
fully capable to perform all operations. Software receivers
provide more flexibility to implement different algorithms and
are adoptable to various changing signals as well [3]. The
received signal is a combination of signals from different

2. satellites and is affected by various multi-paths effects, noise
and other unwanted effects. The RF front-end module
amplifies the signal, down converts it and then samples it. For
simulation, Intermediate Frequency (IF) of 1.75MHz and
sampling frequency 6 MHz has been used.
NAVSYS has developed a Software based GPS receiver
that can handle many issues associated with space-based GPS
receiver [4]. These challenges include: tracking of GPS
satellites that are in higher orbits than the GPS, visibility of
satellites in space and other dynamic issues, like tracking, are
specific to space-based GPS receivers. 3D digital beam
steering technology has been used to address all these issues.
Almost every GPS receiver is implemented using either 2 or
three different platforms. FPGA is most of the time used to
implement the correlator and code generator module of the
GPS receiver while DSP platform is used to implement
various tracking and acquisition algorithms. However, single
platform based implementations are also available. A
complete GPS receiver implemented on C6713 DSP through
Simulink is presented in [5]. A real time implementation of the
GPS receiver, based on Software Defined Radio (SDR), on
multi-core microprocessor is presented in [6] but these types
of implementations are not practical in satellites because of
limited resources. Various approaches for capturing satellite
signals, amplifying the weaker satellite inputs, analysis and
simulation of the received signals using different approaches
are presented in [7-10].
III. IMPLEMENTATION
The basic purpose of the GPS receiver, as discussed in the
previous section, is to provide the orbital position and velocity
information of the satellite. This section provides the
architecture and implementation of the proposed GPS
receiver. The abstract level diagram is shown in Figure 1. The
Antenna senses/receives the signal and forwards it to the front-
end module which samples the received signal and passes it to
the processing system. The processing system consists of
acquisition module, tracking and navigation module. The
calculated output is sent to the On-Board Computer (OBC) of
the PNSS-1. The received signal consists of three parts i.e.
carrier, Coarse/Acquisition (C/A) code and navigation data.
The net signal obtained from satellite is the multiplication of
the 3 signals as shown in Equation 1.
(1)
Where Pc, Pl1, Pl2 are powers of C/A codes. D(t) is
navigation data; Fl1 and Fl2 are carrier band frequencies L1
and L2.
Figure 1: Block Diagram of GPS Receiver
The GPS receiver has four main modules as follows:
a) RF Front-End module
Front end module of the GPS receiver consists of an
antenna, frequency down converter and Analog to Digital
(A/D) converter as shown in Figure 2. The Frequency down
convertor further consists of three parts, which are: Low Noise
Amplifier (LNA), Band-Pass Filter (BPF) and Frequency-
Mixer. LNA amplifies the input signal with minimum noise
amplification. Band-pass filter selects the required signal and
removes the extra noise part of the signal, which has been
included in the signal during transmission.
The functionality of the front end module is, to receive the
signal through antenna and provide to the next phase after
digitizing at some sampling rate.
Many Commercial of the Shelf (COTS) RF Front end
modules are available for space applications [11, 12]. In the
proposed system, we are using STA5620 chip which is an
ASIC based GPS RF-Front end IC. RF signal is amplified and
then down-converted to an Intermediate frequency of 4.092
MHz. It is then sampled at a sampling frequency of 16.368
MHz. and provided to the next phase.
b) Acquisition Phase
Satellite signals are fully interpreted if and only if
i. Local carrier matches with the carrier of incoming
signal
ii. Local Pseudo Random Noise (PRN) codes should be
well aligned in time with the PRN of the
incoming signal so that the PRN code can easily
be separated from the original signal.
For this, we need PRN code, which is explained as follows:
Pseudo Random code is a unique code of each and every
satellite which does not correlate well with any other satellite's
PRN code. In other words, the PRN codes are highly
orthogonal to one another. That’s why PRN code is used to
identify the in-view satellites. The PRN code generator
consists of two registers as described by two polynomials
below.

3. Figure 2: GPS Receiver Front End Module
Initially G1 and G2 are setup to ‘1111111111’. The GPS
signal can be tracked if generator is able to control its phase.
G1 and G2 are two shift registers where first register is of
1023 bit length and clocked at 1.023MHz while second one is
32 bit length and clocked by 16MHz as shown in Figure 3.
The main purpose of the acquisition block or phase is to find
the coarse values of carrier frequency, phase of the C/A code
and number of visible satellites. The basic working principle
of acquisition is the correlation of locally generated carrier and
PRN code to that of incoming signal's carrier and PRN code.
There are `n` acquisition units to search for the specific PRN
sequence of their respective satellites. Each acquisition unit
contains a C/A code generator, acquisition controller and
accumulation units. The acquisition controller gives a specific
frequency bin of Doppler’s shift to every accumulation unit.
The incoming signal is demodulated with that Doppler’s
frequency and then correlated with the C/A code that is locally
generated and save the magnitude with its corresponding
Doppler’s shift and C/A code and compare the magnitude with
a predefined value to determine whether the satellite is located
or not. The module repeats this process for all the specified
frequencies. Vertex-5 QV, a space-graded FPGA, will be used
to implement this module. The architecture of the acquisition
module is as shown in Figure 3.
c) Tracking Loops
In acquisition phase, we calculate the accumulated In-
phase (I) and Quadrature (Q) values of the carrier frequency
and phase of the C/A code. In this phase for tracking, these
loops follow the incoming signal and adjust itself according to
the signal for process of de-spreading and de-modulation as
shown in Figure 4.
We need two types of the loops for tracking the signal. For
carrier tracking, we need Frequency Lock Loop (FLL) and/or
Phase Lock Loop (PLL), which will track only the carrier of
the incoming signal while for code tracking, we use Delay
Lock Loop (DLL).
Figure 3: Acquisition module of the GPS Receiver
d) Navigation
After the best correlated value is generated by a signal, the
signal is sent to the navigation unit. Where firstly, the signal is
demodulated by the frequency that was checked in the
channels. Then the signal is decoded to get the almanac,
ephemeris and the atmospheric correction parameter like
signal corruption and delay in ionosphere or troposphere. This
data along with the results obtained in tracking and acquisition
phase are sent to MicroBlaze where it calculates the pseudo-

4. range by applying kalman filter. Both serial and CAN
interface can be used to send the calculated value to the OBC.
Figure 4: Tracking module
IV. PRELIMINARY RESULTS
The proposed system is designed to satisfy all the
functional requirements and specifications of the PNSS-1
satellite. The use of the space-graded COTS components
and state of the art algorithms makes it superior to the
existing GPS receivers. The space-graded Vertex-5 QV
FPGA provides CAN interface for communication with On-
Board Computer. Further, the said FPGA also meets the
power and space requirements of the PNSS-1.
V. CONCLUSION
A detailed design of the GPS receiver with positional accuracy
better than 20m and update rate greater than 1 Hz is presented.
The detailed architecture and functionality of individual
module is discussed while its prototype is under development.
In future, space-graded COTS components described in the
implementation part will be used to implement the system and
test it on board in PNSS-1.
Acknowledgment
The work has been carried out as a part of the PNSS-1 project.
We greatly acknowledge the support from SUPARCO for
providing us the required document and functional
specifications of the GPS receiver.
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