SiFive offers several high-speed interface IP cores including: - HBM IP up to 3.2Gbps for applications requiring high bandwidth and density like HPC and AI. - Interlaken IP up to 1.2Tbps for chip-to-chip connectivity in applications such as networking and data centers. - A new D2D PHY and controller IP for connecting dies through an interposer or organic substrate at speeds up to 6Gbps for applications such as AI and HPC. - Ethernet MAC and PCS IP supporting speeds from 10G to 400G. - USB controller and PHY IP from USB 1.1 to USB 3.2 for device and host connectivity.

1. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
SiFive SoC IP

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SiFive Memory and Interface IP Portfolio
PHY
(Foundry Specific)
IP Type N7 N16/12
Memory HBM2/2E Silicon Production
Controller IP IP Type Generations
Memory HBM HBM2 (2.4Gbps) HBM2E (3.2Gbps) HBM3 (4Gbps)*
Interface IP
Interlaken Chip-2-Chip (C2C) 600Gbps 1.2Tbps
ILKN-LL, ILKN-LA, 2.0Tbps*
(Low Latency, Look-Aside)
Die-2-Die (D2D)*
USB USB1.x USB2.x/USB3.x USB3.2 Re-timer
Ethernet 400Gbps (200/100/50/25/10Gbps) 100Gbps
FEC KR4 (528, 514) KP4 (544, 514)
TSMC
* Under Development
• Please download “Product Briefs” for each of the above IP at : https://www.sifive.com/soc-ip
• Or contact Sales@SiFIve.com

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SiFive Business Models – Both IP & ASIC/Custom Si
Customer
Package, Assembly
& Test
ASIC & Interposer
wafer
Packaged & Tested
Parts
IP
IP Enablement
(Test chip)
IP Model
Customer
Package, Assembly
& Test
ASIC & Interposer
wafer
Packaged & Tested
Parts
IP Enablement
(Test chip)
ASIC Model
Customer
ASIC,
Interposer
ASIC,
Interposer

4. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
HBM IP

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Why HBM2/2E?
SiFive HBM2/2E IP Subsystem
One Stop Solution: PHY & Controller

2.5D Interposer Design Service

Full ASIC Design Service

2.5D Based IP Experience 7+ Years
CoWoS Experience

Parameters LPDDR5/4 GDDR6 HBM2E
Interface Speed
(Gbps)
4.2 14 3.2
Density 1GB 1GB & 2GB 4GB/8GB/16GB
Power Efficiency
(pJ/b)
2-3x 8x 1x
Bus Width 64-bit 32-bit 1024-bit
Bandwidth 300Gbps 450Gbps 3250Gbps
Complexity Low Medium High
Applications Mobile, Consumers GPU, Automotive HPC, AI,
Networking
High
Density
Low
Power
High
Bandwidth
What type of memory
your system need?

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HBM IP Sub-System
HBM
Memory
KGD
8-CH HBM Controller 8-CH HBMPHY IO
PHY Slice 0
PHY Slice 1
PHY Slice n
Protocol Controller 0Multi port
UIF Interface
CA
DQ
CA
DQ
CA
DQ
Control
Interface
Protocol Controller 1
Protocol Controller N
Control & INIT Block
IEEE1500
Multi Port AXI
(optional)
Arbiter &
Address
Mapper
(optional)
Data
Interface
DFI

7. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
7
⭐ Successful
16nm HBM
2Gbps Silicon
1st Time right
Silicon with full
functionality
2017
⭐ 16nm HBM2
PHY Test Chip
Taped out TSMC
CoWoS based
test chip
2016
⭐ Industry’s 1st:
2.5D Based SoC
Two Multi core
CPU dies
interfacing with
each other using
D2D IOs in 28nm
2013
⭐ Industry’s 1st:
HMC Interface
Solution
1st company to
announce 3D
HMC Solution
2012
2.5D HBM2/E Experience and History with TSMC
⭐ HBM2E
7nm 3.2Gbps
Solution
Silicon proven HBM2E
3.2Gbps Interface in
2019
7nm HBM2E SoC taped
out in Jan 2020
5nm HBM3 & D2D SoC
plan in 2021
2020

8. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
Interlaken IP

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Interlaken In Chip-to-Chip Applications
Line Card
PHY &
Optics
EMAC or
Framer/Ma
pper
Packet
Processing
/NPU
Traffic
Mgmt
Fabric
I/F Chip
TCAM
LineSide
BackPlane(SwitchFabric)
Interlaken
FEC
Ethernet/PCS
Backplane
Line Card
Line Card
Line Card
Line Card
Switch
Fabrics/
Cards
Typical Data Center chassis layout
Ctrl &
Mgmt
Plane
C2C Interface IPs
Ethernet IPs
Applications
• Packet Processing/NPU
• Traffic Management
• Switch Fabric Interface
• Framer/Mapper
• Serial Memory (INLK-LA)
• Matrix Compute Arrays, Chiplets
• FPGA etc
NetworkingData Center AI/ML HPC/Cloud

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Interlaken and FEC IP
High Level Features
• Supports up to 48 SerDes lanes and up to 1.2Tbps bandwidth
• Supports SerDes from 3.125Gbps to 112Gbps
• Supports Flow Control (in band and out of band)
• Supports flexible user interface options including AXI Support
ASIC/FPGA
112GSerDes
FEC
CustomerLogic
ASIC/FPGA
112GSerDes
FEC
CustomerLogic
Interlaken
Interlaken
High Level Features
• Supports 112G PAM4 SerDes
• Supports Interlaken and Ethernet protocol
• Supports KR4, KP4 RS(544,514)
• Supports configurable alignment marker (AM)
Interlaken IP FEC IP
ILKN-Low-
Latency
for AI/ML
Applications
75+ Licenses
Sold to Tier1
customers
since 2010
Chip-to-Chip and Die-2-Die Connectivity Solution

11. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
D2D PHY + Controller IP Subsystem

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Die-2-Die (D2D) Background
User
Logic/
Protocol
D2D
Controller
PHY
User
Logic/
Protocol
D2D
Controller
PHY
Die A Die B
USR/XSR SerDes OR D2D Parallel Wires
• Today’s data intensive applications such as AI/ML and HPC require high-speed IO interfaces
• There is a limit to the number of IO interfaces that can be integrated on a Die
• Die size is further limited by power, reticle size of the wafer and associated yield at lower nodes
• There is a need to connect different die on heterogeneous process nodes
• Advanced packaging technology allows effective use of the beachfront with C4 and Micro-Bumps
Solution:
⇒ Split the die and connect them using low power, high-throughput, low latency links

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SiFive’s Solution to Interface for various application
PHY Type D2D-I1 USR/XSR
Protocol HBM IO single ended OIF based; CEI-xxx
Signal Rate Up to 4-6 Gbps Up to 112 Gbps
Clocking Clock Forwarding CDR based
Latency Medium High
Power/bit Medium (1-3pJ/b) High (>3pJ/b)
Package Choices Interposer Organic/Interposer
Bump Pitch 55u 130u/55u
B/W across die edge/mm 1-3 Tbps/mm ~1.8 Tbps/mm
Suitable Applications AI/HPC etc. Networking, Servers etc
Integrated PHY + Controller[1] SiFive provides both D2D
PHY and D2D Controller
SiFive Provides D2D Controller;
3rd party provides Serdes PHY
[1] D2D-I => SiFive’s Silicon Proven HBM Interposer Based PHY and Interlaken based Controller
Die-2-Die Connections
Si-Interposer based Interface
Organic Substrate or MCM

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• Low Power, High Bandwidth & Low
Latency D2D Controller + D2D-I PHY
• < 1 pJ/b Tx + Rx power
• Up to 3 Tbps by using scalable channels
• 4-6 Gbps per each single ended signals
• Clock forwarding architecture
• D2D-I PHY for Interposer Package
• Based on SiFive’s HBM IP expertise
• Standard uBump and 2.5D support
• ~55u pitch allows large signal density
• D2D Controller
• Based on SiFive’s Interlaken IP for Chip-2-Chip
connectivity
• Streamlined for both D2D-I PHY and USR/XSR
Serdes
• For More Information Contact:
• Sales@SiFive.com
D2D IP Subsystem Overview
Proven
Interlaken C2C
solution for 75+
Tier1 Customers
Proven 7nm HBM2E solution

15. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
Ethernet & USB IP

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100G MAC and PCS IP
High Level Features
• Supports packet streams into a 400/200/100/50/25/10GE Ports
• Configurable maximum bandwidth (e.g. 400G/800G/1.2T/1.6T)
• Configurable number of channels with flexible channel B/W provisioning
• Optional classic (802.3x) and priority-based flow control (802.1Qbb)
High Level Features
• Support for 400/200/100/50/25/10GE Ports
• Support for RS-FEC, FC-FEC, KR FEC and KP FEC
• Configuration to support industry standard PHYs
• MAC interface support CGMII/XLGMII/50GMII/25GMII and XGMII
MAC IP PCS IP

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• Controllers
• USB3.2 Gen2 Device Controller
AKA: USB3.1 Gen2
• USB3.2 Gen1 Dual Role OTG Controller
AKA: USB3.1 Gen1 & USB3.0
• USB3.0 Device Controller
• USB3.0 Embedded Host Controller
• Multi-Point USB2.0 HS OTG controller
• USB2.0 HS Function Controller
• USB2.0 FS Dual-Role Controller
• USB1.1 FS Function Controller
• PHYs
• Fully integrated with Partner PHYs (M31, and
Inno-silicon) in multiple foundries and nodes
• Software
• Only C-based samples drivers
• No xHCI/HUB support
• Test & Debug
• FPGA boards available for prototype
• Extensive in-house test-suites and external VIP
used for robustness
USB IPs

18. CONFIDENTIAL – COPYRIGHT 2018 SIFIVE. ALL RIGHTS RESERVED.
Thank You