The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
Implementation and Performance Analysis of a Vedic Multiplier Using Tanner ED...ijsrd.com
high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.
Implementation of an arithmetic logic using area efficient carry lookahead adderVLSICS Design
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer.
And it is a digital circuit comprised of the basic electronics components, which is used to perform various
function of arithmetic and logic and integral operations further the purpose of this work is to propose the
design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this
study consist of following main functions like addition also subtraction, increment, decrement, AND, OR,
NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the
airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach.
The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU
can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
Implementation and Performance Analysis of a Vedic Multiplier Using Tanner ED...ijsrd.com
high density, VLSI chips have led to rapid and innovative development in low power design during the recent years .The need for low power design is becoming a major issue in high performance digital systems such as microprocessor, digital signal processor and other applications. For these applications, Multiplier is the major core block. Based on the Multiplier design, an efficient processor is designed. Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "UrdhvaTriyakBhyam sutra., which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.
Design and Implementation of an Efficient 64 bit MACIJERA Editor
The design of optimized 64 bit multiplier and accumulator (MAC) unit is implemented in this paper. MAC unit plays major role in many of the digital signal processing (DSP) applications. The MAC unit is designed with the combinations of multipliers and adders. In the proposed method MAC unit is implemented using Vedic multiplier and the adder is done with ripple carry adder .The components are reduced by implementing Vedic multiplier using the techniques of Vedic mathematics that have been modified to improve performance. a high speed processor depends significantly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. The area is optimized effectively using Vedic multiplier .The total design implemented using Xilinx.
High Speed Low Power Veterbi Decoder Design for TCM Decodersijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
A SURVEY - COMPARISON OF MULTIPLIERS USING DIFFERENT LOGIC STYLEEditor IJMTER
In a typical processor, Multiplication is one of the basic arithmetic operations and it
requires substantially more hardware resources and processing time than addition and subtraction. In
fact, approximately 8.72% of all the instruction in typical processing units is multipliers. In
computers, a typical CPU allot a considerable amount of processing time in implementing arithmetic
operations, multiplication operations. In this paper, comparision of different multipliers is done for
low power requirement and high speed. The paper gives information of “booth” algorithm of
Mathematics which is utilized for multiplication to improve the speed of multiplier and , area
parameters of multipliers
Design of an Adaptive Hearing Aid Algorithm using Booth-Wallace Tree MultiplierWaqas Tariq
The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multiplier. Booth Wallace multiplier consumes 40% less power compared to Booth multiplier. A novel digital hearing aid using spectral sharpening filter employing booth Wallace multiplier is proposed. The results reveal that the hardware requirement for implementing hearing aid using Booth Wallace multiplier is less when compared with that of a booth multiplier. Furthermore it is also demonstrated that digital hearing aid using Booth Wallace multiplier consumes less power and performs better in terms of speed.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
Multiplications and additions are most widely and more often used arithmetic computations performed in
all digital signal processing applications. Addition is the basic operation for many digital application. The
aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system
is mainly influenced by the performance of the adders. Multipliers are also very important component in
digital systems
Design of High Speed and Low Power Veterbi Decoder for Trellis Coded Modulati...ijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A Time-Area-Power Efficient High Speed Vedic Mathematics Multiplier using Com...Kumar Goud
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Keywords—4:2 Compressor, 7:2 Compressor, Booth’s multiplier, high speed multiplier, modified Booth’s multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.
Introducing the Concept of Back-Inking as an Efficient Model for Document Ret...IJITCA Journal
Today, many institutions and organizations are facing serious problem due to the tremendously increasing
size of documents, and this problem is further triggering the storage and retrieval problems due to the
continuously growing space and efficiency requirements. This problem is becoming more complex with
time and the increase in the size and number of documents in an organization. Therefore, there is a
growing demand to address this problem. This demand and challenge can be met by developing a
technique to enable specialized document imaging people to use when there is a need for storing
documents images. Thus, we need special and efficient storage techniques for this type of information
storage (IS) systems.
In this paper, we present an efficient storage technique for electronic documents. The proposed technique
uses the Information Pixels concept to make the technique more efficient for certain image formats. In
addition, we shall see how Storing Information Pixels Addresses ( SIPA ) method is an efficient method for
document storage and as a result makes the document image storage relatively efficient for most image
formats.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Multiplication is the most time consuming process in various signal processing operations like convolution,
circular convolution, auto-correlation and cross-correlation. With advances in technology, many researchers have
tried and are trying to design multipliers which offer either of the following- high speed, low power consumption,
regularity of layout and hence less area or even combination of them in multiplier. However area and speed are
two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best
trade off solution among the both of them. To have features like high speed and low power consumption
multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using various
algorithm in VLSI technology. The Wallace Tree Multipliers are compared with existing multipliers in terms of
improvement in features like area, delay and power consumption by using different logical operation.
Design and Implementation of an Efficient 64 bit MACIJERA Editor
The design of optimized 64 bit multiplier and accumulator (MAC) unit is implemented in this paper. MAC unit plays major role in many of the digital signal processing (DSP) applications. The MAC unit is designed with the combinations of multipliers and adders. In the proposed method MAC unit is implemented using Vedic multiplier and the adder is done with ripple carry adder .The components are reduced by implementing Vedic multiplier using the techniques of Vedic mathematics that have been modified to improve performance. a high speed processor depends significantly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. The area is optimized effectively using Vedic multiplier .The total design implemented using Xilinx.
High Speed Low Power Veterbi Decoder Design for TCM Decodersijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
A SURVEY - COMPARISON OF MULTIPLIERS USING DIFFERENT LOGIC STYLEEditor IJMTER
In a typical processor, Multiplication is one of the basic arithmetic operations and it
requires substantially more hardware resources and processing time than addition and subtraction. In
fact, approximately 8.72% of all the instruction in typical processing units is multipliers. In
computers, a typical CPU allot a considerable amount of processing time in implementing arithmetic
operations, multiplication operations. In this paper, comparision of different multipliers is done for
low power requirement and high speed. The paper gives information of “booth” algorithm of
Mathematics which is utilized for multiplication to improve the speed of multiplier and , area
parameters of multipliers
Design of an Adaptive Hearing Aid Algorithm using Booth-Wallace Tree MultiplierWaqas Tariq
The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multiplier. Booth Wallace multiplier consumes 40% less power compared to Booth multiplier. A novel digital hearing aid using spectral sharpening filter employing booth Wallace multiplier is proposed. The results reveal that the hardware requirement for implementing hearing aid using Booth Wallace multiplier is less when compared with that of a booth multiplier. Furthermore it is also demonstrated that digital hearing aid using Booth Wallace multiplier consumes less power and performs better in terms of speed.
IMPLEMENTATION OF UNSIGNED MULTIPLIER USING MODIFIED CSLAeeiej_journal
Multiplications and additions are most widely and more often used arithmetic computations performed in
all digital signal processing applications. Addition is the basic operation for many digital application. The
aim is to develop area efficient, high speed and low power devices. Accurate operation of a digital system
is mainly influenced by the performance of the adders. Multipliers are also very important component in
digital systems
Design of High Speed and Low Power Veterbi Decoder for Trellis Coded Modulati...ijsrd.com
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A Time-Area-Power Efficient High Speed Vedic Mathematics Multiplier using Com...Kumar Goud
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Keywords—4:2 Compressor, 7:2 Compressor, Booth’s multiplier, high speed multiplier, modified Booth’s multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.
Introducing the Concept of Back-Inking as an Efficient Model for Document Ret...IJITCA Journal
Today, many institutions and organizations are facing serious problem due to the tremendously increasing
size of documents, and this problem is further triggering the storage and retrieval problems due to the
continuously growing space and efficiency requirements. This problem is becoming more complex with
time and the increase in the size and number of documents in an organization. Therefore, there is a
growing demand to address this problem. This demand and challenge can be met by developing a
technique to enable specialized document imaging people to use when there is a need for storing
documents images. Thus, we need special and efficient storage techniques for this type of information
storage (IS) systems.
In this paper, we present an efficient storage technique for electronic documents. The proposed technique
uses the Information Pixels concept to make the technique more efficient for certain image formats. In
addition, we shall see how Storing Information Pixels Addresses ( SIPA ) method is an efficient method for
document storage and as a result makes the document image storage relatively efficient for most image
formats.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design and implementation of high speed baugh wooley and modified booth multi...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Multiplication is the most time consuming process in various signal processing operations like convolution,
circular convolution, auto-correlation and cross-correlation. With advances in technology, many researchers have
tried and are trying to design multipliers which offer either of the following- high speed, low power consumption,
regularity of layout and hence less area or even combination of them in multiplier. However area and speed are
two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best
trade off solution among the both of them. To have features like high speed and low power consumption
multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using various
algorithm in VLSI technology. The Wallace Tree Multipliers are compared with existing multipliers in terms of
improvement in features like area, delay and power consumption by using different logical operation.
VLSI ARCHITECTURE OF AN 8-BIT MULTIPLIER USING VEDIC MATHEMATICS IN 180NM TEC...P singh
A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics, a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation.
Design and Implementation of Single Precision Pipelined Floating Point Co-Pro...Silicon Mentor
Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. For more info download this file or visit us at:
http://www.siliconmentor.com/
Implemenation of Vedic Multiplier Using Reversible Gates csandit
With DSP applications evolving continuously, there is continuous need for improved multipliers which are faster and power efficient. Reversible logic is a new and promising field which addresses the problem of power dissipation. It has been shown to consume zero power theoretically. Vedic mathematics techniques have always proven to be fast and efficient for solving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyam algorithm using reversible logic thereby addressing two important issues – speed and power consumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier is optimized by reducing the number of logic gates, constant inputs, and garbage outputs. This multiplier can find its application in various fields like convolution, filter applications, cryptography, and communication.
Multipliers play an important role in today’s digital signal processing (DSP) and various other
applications. Multiplication is the most time consuming process in various signal processing operations like
convolution, circular convolution, auto-correlation and cross-correlation. With advances in technology, many
researchers have tried and are trying to design multipliers which offer either of the following- high speed, low
power consumption, regularity of layout and hence less area or even combination of them in multiplier. However
area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try
to find out the best trade off solution among the both of them. To have features like high speed and low power
consumption multipliers several algorithms have been introduced .In this paper, we describes Multipliers by using
various algorithm in VLSI technology.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIF...VLSICS Design
In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm
MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC
Design and testing of systolic array multiplier using fault injecting schemesCSITiaesprime
Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.
OPTIMIZED MULTIPLIER USING REVERSIBLE MULTICONTROL INPUT TOFFOLI GATESVLSICS Design
Reversible logic is an important area to carry the computation into the world of quantum computing. In this paper a 4-bit multiplier using a new reversible logic gate called BVPPG gate is presented. BVPPG gate is a 5 x 5 reversible gate which is designed to generate partial products required to perform multiplication and also duplication of operand bits is obtained. This reduces the total cost of the circuit. Toffoli gate is the universal and also most flexible reversible logic gate. So we have used the Toffoli gates to construct the designed multiplier.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to
around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is
evaluated by comparing its performance with those of some approximate and correct multipliers using
different design parameters. In this proposed approach combined the conventional RoBA multiplier with
Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA
multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved
the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the
DSP.
Similar to FPGA IMPLEMENTATION OF HIGH SPEED BAUGH-WOOLEY MULTIPLIER USING DECOMPOSITION LOGIC (20)
Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An ...eeiej_journal
Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international
Journal aims to bring together researchers and practitioners from academia and industry to focus on
recent systems and techniques in the broad field of electrical, instrumentation and communication
Engineering. Original research papers, state-of-the-art reviews are invited for publication in all areas
of Electrical Electronics & Instrumentation Engineering.
Authors are solicited to contribute to this journal by submitting articles that illustrate research
results, projects, surveying works and industrial experiences that describe significant advances in
the following areas, but are not limited to
Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An ...eeiej_journal
Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal aims to bring together researchers and practitioners from academia and industry to focus on recent systems and techniques in the broad field of electrical, instrumentation and communication Engineering. Original research papers, state-of-the-art reviews are invited for publication in all areas of Electrical Electronics & Instrumentation Engineering.
SINGLE AXIS PV-PANEL TRACKING FOR AUTOMATED STREET LIGHT CONTROLLER eeiej_journal
A Street Light Control framework which works naturally is least demanding as well as the canny framework. This project describes a street lighting application developed utilizing a hybrid powergeneration technology that combines solar energy into a single, unified power generation system. Solar energy vitality is quickly picking up notoriety as an essential method for growing renewable vitality assets. Solar energy following permits more vitality to be delivered in light of the fact that the sun oriented vitality has the capacity stay adjusted to sun
TOPOLOGY AND CONFIGURATION SELECTION FOR DC/DC CONVERTERS IN SPACE ELECTRICAL...eeiej_journal
Selection of DC/DC converter topology is one of the most challenging aspects in space Electrical Power Systems (EPS) design and development. It both highly, affects and is affected from EPS reliability requirements among the other EPS performance specifications. So ranking of DC/DC converters based on
End-Of-Life (EOL) reliability is an undeniable need.
TCSC AND SVC OPTIMAL LOCATION TO IMPROVE THE PERFORMANCE OF POWER SYSTEM WITH...eeiej_journal
Wind generation connection to power system affects steady state and transient stability. Furthermore, this
effect increases with the increase of wind penetration in generation capacity. In this paper optimal location
of FACTS devices is carried out to solve the steady state problems of wind penetration. Two case studies
are carried out on modified IEEE39 bus system one with wind reduction to 20% and the second with wind
penetration increase by 50% in the two cases system suffer from outage of one generator with load at bus
39 decreases from 1104 MW to 900 MW.
DESIGN OF RADIX-8 BOOTH MULTIPLIER USING KOGGESTONE ADDER FOR HIGH SPEED ARIT...eeiej_journal
This paper presents the design and implementation of radix-8 booth Multiplier .The number of partial
products are reduced to n/2 in radix-4We can reduce the number of partial products even further to n/3 by
using a higher radix-8 in the multiplier encoding, thereby obtaining a simpler CSA tree .This implies less
delay and a smaller area size .Since this multiplication operation is for both signed and unsigned
numbers,cost of the system can also be reduced.
IMPLEMENTATION OF PERTURB AND OBSERVE MPPT OF PV SYSTEM WITH DIRECT CONTROL M...eeiej_journal
The Maximum Power Point Tracking (MPPT) is a technique used in power electronic circuits to extract
maximum energy from the Photovoltaic (PV) Systems. In the recent decades, photovoltaic power generation
has become more important due its many benefits such as needs a few maintenance and environmental
advantages and fuel free. However, there are two major barriers for the use of PV systems, low energy
conversion efficiency and high initial cost. To improve the energy efficiency, it is important to work PV
system always at its maximum power point. So far, many researches are conducted and many papers were
published and suggested different methods for extracting maximum power point. This paper presents in
details implementation of Perturb and Observe MPPT using buck and buck-boost Converters. Some results
such as current, voltage and output power for each various combination have been recorded
Capacitance-voltage Profiling Techniques for Characterization of Semiconduct...eeiej_journal
A new capacitance-voltage profiling technique of semiconductor junctions is proposed for characterisation of semiconductor materials and devices. The measurement technique is simple, non-destructive and it has a greater accuracy compared with the classical C-V method of J. Hilibrand and R. D. Gold, developed in 1960.
Development of Improved Diode Clamped Multilevel Inverter Using Optimized Sel...eeiej_journal
In this paper the role of Selective Harmonic Elimination (SHE) is presented for diode clamped twelve-level multilevel inverter (DCMLI) based on dog leg optimization algorithm. Non-linear equations has been solved to eliminate specific low order harmonics, using the developed DOP algorithm, while at the same time the fundamental component is retained efficiently. The non-linear nature of transcendental equation provide multiple or even no solution for a particular modulation index. The proposed optimization method solving the nonlinear transcendental equations providing all possible solutions. The paper also showing the comparison between different modulation techniques including the proposed method. The entire system has been simulated using MATLAB/Simulink. Simulation results confirm the effectiveness with negligible
THD.
SINGLE AXIS PV-PANEL TRACKING FOR AUTOMATED STREET LIGHT CONTROLLER eeiej_journal
A Street Light Control framework which works naturally is least demanding as well as the canny framework. This project describes a street lighting application developed utilizing a hybrid power generation technology that combines solar energy into a single, unified power generation system. Solar
energy vitality is quickly picking up notoriety as an essential method for growing renewable vitality assets. Solar energy following permits more vitality to be delivered in light of the fact that the sun oriented vitality has the capacity stay adjusted to sun. The force from the sun blocked by the earth is roughly 1.8*1011MW, which is numerous a huge number of times bigger than the present utilization rate on the earth of all business vitality sources. The design objective of the solar renewable street-light system is to develop a self-sufficient street lighting system that generates and stores electric power whenever solar radiation are available, and then provides lighting during the night time. The bureau for the battery stockpiling and controller circuits ought to be sufficiently little with the goal that it can be promptly installable in many areas.
COMPARATIVE STUDY FOR PERFORMANCE ANALYSIS OF ROUTING PROTOCOLS IN MOBILITY A...eeiej_journal
A Mobile Ad-hoc Network (MANET) has a collection of numbers of wireless nodes which is each device in MANET having ability to free to move in any direction so that it is useful in all applications. In MANET nodes change position quite frequently, this means that we have need routing protocols that quickly adapts to topology changes. An ad-hoc network is self-organising and distributive in manner. The MANET is
works as router so that linked with the other nearest devices. A mobile ad hoc network (MANET) is a
wireless network follows the multiple hop routing instead of static network infra to provide network connectivity. Each device in a MANET is free to move independently in all direction freewaysand will
therefore nodes change position in large networks all routing protocols. The routing protocols are needed for conveying information in Ad-hoc network there are various performance parameters to compare the Ad-hoc routing protocols.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
The Benefits and Techniques of Trenchless Pipe Repair.pdf
FPGA IMPLEMENTATION OF HIGH SPEED BAUGH-WOOLEY MULTIPLIER USING DECOMPOSITION LOGIC
1. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal
(EEIEJ), Vol. 2, No. 3, August 2015
DOI : 10.5121/eeiej.2015.2301 1
FPGA IMPLEMENTATION OF HIGH SPEED
BAUGH-WOOLEY MULTIPLIER USING
DECOMPOSITION LOGIC
Ananda Kiran1
and Navdeep Prashar2
1
Department of Electronics and Communication Engineering, Bahra University,
Shimla-Hills, H.P, India
2
Assistant Professor in the Department of Electronics and Communication Engineering,
Bahra University, Shimla-Hills, H.P., India
Abstract
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital
signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the
speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and
implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth
multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3
device.
Keyword
Baugh-Wooley Multiplier, Decomposition Logic, Booth Multiplier
1.INTRODUCTION
Multipliers play a pivotal role in many high performance systems such as Microprocessor, FIR
filters, Digital Processors, etc. In its early stage, multiplication algorithms were proposed by
Burton and Noaks in the year1968, by Hoffman in the year 1986 and by Guilt and De Mori in the
year 1969 for positive numbers. In the year of 1973 and 1979, Baugh- Wooley and Hwang
proposed multiplication algorithm for numbers in two’s complement form. Multiplication is
hardware intensive and the main criteria of interest are higher speed, lower cost and lower power
[1].With development in technology, several researchers have tried multipliers which provide
design targets such as low power consumption, increased speed, and regularity of layout or
combination of them in one multiplier. This helps making them suitable for achieving compact
high speed and low power implementation.
The performance of a system is generally controlled by the performance of the multiplier as
the multiplier is usually the slowest element in the system. Furthermore, multiplier is normally
the most area consuming element in the system. Therefore, optimizing its speed and area are vital
design factors. However, area and speed are generally the conflicting constraints improving speed
which results mostly in large area.
With ever increasing applications in portable equipment and mobile communications, the demand
for high performance, low-power VLSI systems is gradually increasing. Digital signal processors
2. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal
(EEIEJ), Vol. 2, No. 3, August 2015
2
and application specific integrated circuits depend on the efficient implementation of arithmetic
circuits (adder and multiplier) to execute dedicated algorithm such as convolution, correlation and
filtering [2]. A Baugh-Wooley multiplier using decomposition logic is presented here which
increases speed when compared to the booth multiplier.
2.BAUGH-WOOLEY MULTIPLIER
In signed multiplication the length of the partial products and the number of partial products will
be very high. So an algorithm was introduced for signed multiplication called as Baugh-Wooley
algorithm. The Baugh-Wooley multiplication is one amongst the cost-effective ways to handle
the sign bits.This method has been developed so as to style regular multipliers, suited to 2's
compliment numbers.
2.1 .Baugh-Wooley Architecture
Baugh-Wooley multiplier hardware architecture is shown in figure 1. It follows left shift
algorithm. Mux can select which bit will multiply. Suppose we multiply +4 and -4 in decimal we
get ‘0’. Now, after representing these numbers in two’s compliment form we get +4 as 0100 and -
4 as 1100. On adding these two binary numbers we get 10000. Discard carry, then number is
represented as ‘0’.
Figure.1 Hardware implementation of Baugh-Wooley Multiplier [3]
Let two n-bit numbers, number (A) and number (B), A and B are often pictured as
3. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal
(EEIEJ), Vol. 2, No. 3, August 2015
3
ܣ = − ܽିଵ2ିଵ
+ ܽ2
ିଶ
ୀ
(1)
ܤ = −ܾିଵ2ିଵ
+ ܾ2
ିଶ
ୀ
(2)
Where ܽ and ܾ area unit the bits during A and B, severally and ܽିଵ and ܾିଵ area unit the sign
bits. The full precision product, P = A × B, is provided by the equation:
ܲ = ܣ × ܤ = ൭−ܽିଵ2ିଵ
+ ܽ2
ିଶ
ୀ
൱ × ൭−ܾିଵ2ିଵ
+ ܾ2
ିଶ
ୀ
൱൩
= ܽିଵܾିଵ2ଶିଶ
+ ܽ2
ିଵ
ୀ
ܾ2
− 2ିଵ
ܾܽିଵ2
ିଶ
ୀ
− 2ିଵ
ିଶ
ୀ
ܽିଵܾ2
ିଶ
ୀ
(3)
The first two terms of above equation are positive and last two terms are negative [4]. In order to
calculate the product, instead of subtracting the last two terms, it is possible to add the opposite
values [5].The above equation signifies the Baugh-Wooley algorithm for multiplication process in
two’s compliment form.
Baugh-Wooley Multiplierprovides a high speed, signed multiplication algorithm [5]. It uses
parallel products to complement multiplication and adjusts the partial products to maximize the
regularity of multiplication array [6]. When number is represented in two’s complement form,
sign of the number is embedded in Baugh-Wooley multiplier. This algorithm has the advantage
that the sign of the partial product bits are always kept positive so that array addition techniques
can be directly employed [6]. In the two’s complement multiplication, each partial product bit is
the AND of a multiplier bit and a multiplicand bit, and the sign of the partial product bits are
positive [6].
3.DECOMPOSITION LOGIC
The implementation of digital multiplier with decomposition logic is presented here. In this
technique the multiplication process is split into smaller sub-units (smaller multipliers) and their
outputs are combined to get the final result, the decomposition logic requires extra circuitry to
perform the final addition of outputs attained from the smaller multiplier [7]. However, due to
parallel processing, noticeable improvement in speed is achieved.
To check the performance of the multiplier structure, 8×8 multiplier structure is designed using
Baugh-Wooley algorithm and the decomposition logic. Fig. 2 [7] shows an 8×8 multiplier
implemented using the decomposition logic. In the first stage, four 4×4 multipliers are used to
combine all the partial products, the outputs from these 4×4 multipliers are then combined in a
treelike fashion to get the final results [7]. The 4×4 multiplier was implemented using Baugh-
Wooley method. For 16×16 multiplication, three decomposition structures can be implemented.
The first using 4×4 Baugh-Wooley multipliers, the second using 8×8 Baugh-Wooley multipliers
and the third using 8×8 decomposition structure [7].
4. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal
(EEIEJ), Vol. 2, No. 3, August 2015
4
Figure 2.Decomposition structure for 8×8 multiplication
Figure 3 shows the RTL view of Baugh-Wooley Multiplier with decomposition logic.
Figure 3. RTL view of Baugh-Wooley with decomposition logic
For any number of inputs one output is generated. Number of bits of the output depends on the
number of bits of the inputs; e.g. in figure 3 there are two inputs of 4 bits the output will be of
8bits.
5. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal
(EEIEJ), Vol. 2, No. 3, August 2015
5
4.SIMULATION AND RESULT
The code of Baugh-Wooley multiplier and decomposition logic is written in VHDL and
simulated using ISim (VHDL/Verilog). The proposed architecture is implemented on Virtex6
xc6vlx75t-3-ff484 device using XILINX 12.3. Table 1 shows the device utilization summary of
Baugh-Wooley multiplier using decomposition logic.
Table 1. Hardware Device Utilization Summary
S. NO. Logic Utilization Used Available
1 No. of bonded IO 16 240
2 No. of slice LUTs 13 46560
3 No. of occupied slices 6 11640
4.1Comparison of present work, Baugh-Wooley multiplier and decomposition logic
with the previous work
Present work is implemented on Virtex6 xc6vlx75t-3-ff484 device. Thus, finally comparison of
present work with previous work is done as shown in Table 2. The simulation results for 8×8
multipliers are summarized in Table 2. For the 8×8 multiplier structure, the Baugh-Wooley
method and decomposition logic show an improvement in delay compared to Booth
multiplication method due to parallel processing of data.
Table 2. Comparison of present work with the previous reference paper
8×8 Multiplier Booth Multiplier [13] Baugh-Wooley
Path Delay 15.345ns 10.516ns
No. of boned IO 36 32
Total real time to Xst
completion
12.00secs 6.00secs
No. of slice LUTs 190 13
Average fanout 4.00 3.43
Maximum Frequency
MHz
65.16 95.09
Frm Table 2, it is clear that present design shows an improvement in speed with reduction in used
resources on target device.
7. Emerging Trends in Electrical, Electronics & Instru
(EEIEJ), Vol. 2, No. 3, August 2015
Authors Biography
NavdeepPrashar has obtained his Bachelor of Technology degree from the CT Institute of
Engineering, Management and Technology, Jalandhar affiliated to Punjab Technical
University, Jalandhar in 2010 and Master of Technology degree from Centre for
Development of Advanced Computing (CDAC), Mohali.He is currently serving as
Assistant Professor in Bahra University, Waknaghat,Solan, H.P., India. He has 3+ years of
teaching experience to both undergraduate and postg
published one book and presented many papers in the International &National Journals and Conferences.
His current interest includes Embedded Systems, VLSI Design & Testing, Low Power techniques, and
System on Chip.
AnandaKiran has obtained her B.Tech. (Electronics and Communication Engineering)
degree from the LR Institute of Engineering and Technology, Solan affili
Pradesh University, in 2013, and
Communication Engineering) degree from Bahra University, Waknaghat. At present, she is
working on her M. Tech. (Electronics and Communication Engineering) the
interest is Embedded Systems, VLSI Design and Digital Signal Processing.
lectrical, Electronics & Instrumentation Engineering: An international Journal
(EEIEJ), Vol. 2, No. 3, August 2015
has obtained his Bachelor of Technology degree from the CT Institute of
Management and Technology, Jalandhar affiliated to Punjab Technical
University, Jalandhar in 2010 and Master of Technology degree from Centre for
Development of Advanced Computing (CDAC), Mohali.He is currently serving as
rsity, Waknaghat,Solan, H.P., India. He has 3+ years of
teaching experience to both undergraduate and postgraduate students. Mr. Prashar has
published one book and presented many papers in the International &National Journals and Conferences.
interest includes Embedded Systems, VLSI Design & Testing, Low Power techniques, and
B.Tech. (Electronics and Communication Engineering)
degree from the LR Institute of Engineering and Technology, Solan affiliated to Himachal
Pradesh University, in 2013, and presently she is doing M.Tech. (Electronics and
Communication Engineering) degree from Bahra University, Waknaghat. At present, she is
working on her M. Tech. (Electronics and Communication Engineering) thesis. Her area of
interest is Embedded Systems, VLSI Design and Digital Signal Processing.
mentation Engineering: An international Journal
7
published one book and presented many papers in the International &National Journals and Conferences.
interest includes Embedded Systems, VLSI Design & Testing, Low Power techniques, and