FPGA and CPLD are compared based on 11 parameters. FPGA uses look up tables in its fine grain architecture with around 100,000 blocks, SRAM for memory, and is more complex and costly than CPLD. CPLD uses logic functions in its course grain architecture with fewer blocks, EPROM for memory, and is less complex and costly than FPGA. A key difference is that the program stays in CPLD after power off but is lost in FPGA.

1. Comparison of FPGA
and CPLD
By Prof. Hitesh Dholakiya
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VLSI Lecture series
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2. Comparison of FPGA and CPLD
FPGA CPLD
Parameters
1. Complex Programable Logic Design
1. Field Programable Gate Array
1. Full Form
2. Based on “Logic Function”
2. Based on “Look up table”
2. Architecture
3. Few blocks
3. Around 100000
3. Blocks in Architecture
4. Course Grain Devices
4. Fine Grain Devices
4. Architecture tuning
5. EPROM
5. SRAM
5. Architectural Memory
6. Less
6. High
6. Complexity
7. Less
7. High
7. Cost
8. Instant ON
8. It takes time to load program
8. Time to ON
9. Program stays in CPLD
9. Program lost once power is OFF
9. Volatility of Program
10. Weaker Power Consumption
10. Ideal Power Consumption
10. Power Consumption
11. Easier to determine
11. Complex to determine
11. Timing Analysis
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