This document discusses energy-efficient hardware data prefetching. It begins with an introduction to data prefetching and why it is needed due to the growing gap between processor and memory speeds. It then covers different types of prefetching techniques including software-based, hardware-based, sequential, stride, and pointer prefetching. It also discusses the tradeoffs between software and hardware approaches. Finally, it introduces the concept of energy-aware data prefetching to reduce the increased energy consumption from aggressive prefetching techniques.
This document provides an overview of mass storage structures and operating system services for mass storage. It discusses disk structure, disk scheduling algorithms, swap space management, RAID structures, and stable storage implementation. The document also describes the physical structure of secondary and tertiary storage devices and their performance characteristics.
Cache memory is a type of fast RAM that a computer processor can access more quickly than regular RAM. It stores recently accessed data from main memory to allow for faster future access if the same data is needed again. Cache memory is organized into levels based on proximity and speed of access to the processor, with L1 cache being fastest as it is located directly on the CPU chip, and L2 cache and main memory being progressively slower as they are located further away. Modern processors integrate both L1 and L2 cache onto the CPU package to improve performance by reducing access time.
Cache coherence refers to maintaining consistency between data stored in caches and the main memory in a system with multiple processors that share memory. Without cache coherence protocols, modified data in one processor's cache may not be propagated to other caches or memory. There are different levels of cache coherence - from ensuring all processors see writes instantly to allowing different ordering of reads and writes. Cache coherence aims to ensure reads see the most recent writes and that write ordering is preserved across processors. Directory-based and snooping protocols are commonly used to maintain coherence between caches in multiprocessor systems.
The document discusses parallel databases and their architectures. It introduces parallel databases as systems that seek to improve performance through parallelizing operations like loading data, building indexes, and evaluating queries using multiple CPUs and disks. It describes three main architectures for parallel databases: shared memory, shared disk, and shared nothing. The shared nothing architecture provides linear scale-up and speed-up but is more difficult to program. The document also discusses measuring performance improvements from parallelization through speed-up and scale-up.
The document discusses different memory management strategies:
- Swapping allows processes to be swapped temporarily out of memory to disk, then back into memory for continued execution. This improves memory utilization but incurs long swap times.
- Contiguous memory allocation allocates processes into contiguous regions of physical memory using techniques like memory mapping and dynamic storage allocation with first-fit or best-fit. This can cause external and internal fragmentation over time.
- Paging permits the physical memory used by a process to be noncontiguous by dividing memory into pages and mapping virtual addresses to physical frames, allowing more efficient use of memory but requiring page tables for translation.
This document discusses different RAID levels for combining multiple disk drives into a logical unit for storage. It defines RAID and explains its purpose is to provide data redundancy, fault tolerance, increased storage capacity and performance. The document then covers RAID levels 0 through 5, describing their ideal uses, advantages, and disadvantages for striping, mirroring, parity and error correction approaches.
Back Propagation in Deep Neural NetworkVARUN KUMAR
The document discusses back propagation in neural networks. It begins with an introduction that explains back propagation is used to fine-tune weights in a neural network to minimize error. It then provides steps to solve a back propagation problem using an example neural network with two inputs, two outputs, and a single hidden layer. The steps include calculating outputs, errors, and updated weights using equations that propagate error backwards to adjust weights and reduce total error.
The cache is a small amount of fast memory located close to the CPU that stores frequently accessed and nearby data from main memory in order to speed up data access times for the CPU. Without cache, every data request from the CPU would require accessing the slower main memory. Caches exploit the principle of locality of reference, where programs tend to access the same data repeatedly, to improve performance by fulfilling many requests from the faster cache instead of main memory.
This document provides an overview of mass storage structures and operating system services for mass storage. It discusses disk structure, disk scheduling algorithms, swap space management, RAID structures, and stable storage implementation. The document also describes the physical structure of secondary and tertiary storage devices and their performance characteristics.
Cache memory is a type of fast RAM that a computer processor can access more quickly than regular RAM. It stores recently accessed data from main memory to allow for faster future access if the same data is needed again. Cache memory is organized into levels based on proximity and speed of access to the processor, with L1 cache being fastest as it is located directly on the CPU chip, and L2 cache and main memory being progressively slower as they are located further away. Modern processors integrate both L1 and L2 cache onto the CPU package to improve performance by reducing access time.
Cache coherence refers to maintaining consistency between data stored in caches and the main memory in a system with multiple processors that share memory. Without cache coherence protocols, modified data in one processor's cache may not be propagated to other caches or memory. There are different levels of cache coherence - from ensuring all processors see writes instantly to allowing different ordering of reads and writes. Cache coherence aims to ensure reads see the most recent writes and that write ordering is preserved across processors. Directory-based and snooping protocols are commonly used to maintain coherence between caches in multiprocessor systems.
The document discusses parallel databases and their architectures. It introduces parallel databases as systems that seek to improve performance through parallelizing operations like loading data, building indexes, and evaluating queries using multiple CPUs and disks. It describes three main architectures for parallel databases: shared memory, shared disk, and shared nothing. The shared nothing architecture provides linear scale-up and speed-up but is more difficult to program. The document also discusses measuring performance improvements from parallelization through speed-up and scale-up.
The document discusses different memory management strategies:
- Swapping allows processes to be swapped temporarily out of memory to disk, then back into memory for continued execution. This improves memory utilization but incurs long swap times.
- Contiguous memory allocation allocates processes into contiguous regions of physical memory using techniques like memory mapping and dynamic storage allocation with first-fit or best-fit. This can cause external and internal fragmentation over time.
- Paging permits the physical memory used by a process to be noncontiguous by dividing memory into pages and mapping virtual addresses to physical frames, allowing more efficient use of memory but requiring page tables for translation.
This document discusses different RAID levels for combining multiple disk drives into a logical unit for storage. It defines RAID and explains its purpose is to provide data redundancy, fault tolerance, increased storage capacity and performance. The document then covers RAID levels 0 through 5, describing their ideal uses, advantages, and disadvantages for striping, mirroring, parity and error correction approaches.
Back Propagation in Deep Neural NetworkVARUN KUMAR
The document discusses back propagation in neural networks. It begins with an introduction that explains back propagation is used to fine-tune weights in a neural network to minimize error. It then provides steps to solve a back propagation problem using an example neural network with two inputs, two outputs, and a single hidden layer. The steps include calculating outputs, errors, and updated weights using equations that propagate error backwards to adjust weights and reduce total error.
The cache is a small amount of fast memory located close to the CPU that stores frequently accessed and nearby data from main memory in order to speed up data access times for the CPU. Without cache, every data request from the CPU would require accessing the slower main memory. Caches exploit the principle of locality of reference, where programs tend to access the same data repeatedly, to improve performance by fulfilling many requests from the faster cache instead of main memory.
The document discusses the concept of virtual memory. Virtual memory allows a program to access more memory than what is physically available in RAM by storing unused portions of the program on disk. When a program requests data that is not currently in RAM, it triggers a page fault that causes the needed page to be swapped from disk into RAM. This allows the illusion of more memory than physically available through swapping pages between RAM and disk as needed by the program during execution.
This document provides an overview of an operating systems concepts textbook. It introduces key topics covered in the book like computer system organization, operating system structure and functions, process management, memory management, storage management, and security. The objectives are to provide a tour of major OS components and coverage of basic computer system organization. It describes the four main components of a computer system and how the operating system acts as an intermediary between the user, hardware, and application programs.
In recent years, we have seen an overwhelming number of TV commercials that promise that the Cloud can help with many problems, including some family issues. What stands behind the terms “Cloud” and “Cloud Computing,” and what we can actually expect from this phenomenon? A group of students of the Computer Systems Technology department and Dr. T. Malyuta, whom has been working with the Cloud technologies since its early days, will provide an overview of the business and technological aspects of the Cloud.
We are predicting Heart Disease by Taking 14 Medical Parameters as an inputs through 2 data Minning Techniques(Decision Tree(Faster) And KNN neighbour Algorithms(Slower)).
And Visualizing The dataset.If the output 1 then it means Higher Chances of getting Heart Attack ,if 0 then it means Less chances of Heart Attack.
Two-level paging is used to divide the large page table into smaller pieces called page tables. A logical address is divided into a page number and page offset, and the page number is further divided to index the outer page table and inner page table. Inverted page tables store one entry per physical page with the owning process and virtual page number instead of physical addresses. This reduces the page table size significantly but increases translation time. Hashed inverted page tables add a hash table to map process/virtual page number pairs to page table entries, reducing average translation time.
DSM system
Shared memory
On chip memory
Bus based multiprocessor
Working through cache
Write through cache
Write once protocol
Ring based multiprocessor
Protocol used
Similarities and differences b\w ring based and bus based
Introduction, Central Processing Unit (CPU) Memory, Communication between Various Units of a Computer System, The Instruction Format, Instruction Set, Processor Speed, Multiprocessor Systems.
The CPU acts as the computer's brain and carries out instructions from programs. It has two main components: the control unit, which selects and coordinates instruction execution, and the arithmetic logic unit, which performs calculations. Registers temporarily store data during instruction processing, including special purpose registers like the program counter, accumulator, and input/output registers. The CPU communicates with main memory, usually RAM, and cache memory for faster access to active data. It fetches instructions from memory and decodes and executes them in a multi-step process controlled by the control unit.
Here is how you can solve this problem using MapReduce and Unix commands:
Map step:
grep -o 'Blue\|Green' input.txt | wc -l > output
This uses grep to search the input file for the strings "Blue" or "Green" and print only the matches. The matches are piped to wc which counts the lines (matches).
Reduce step:
cat output
This isn't really needed as there is only one mapper. Cat prints the contents of the output file which has the count of Blue and Green.
So MapReduce has been simulated using grep for the map and cat for the reduce functionality. The key aspects are - grep extracts the relevant data (map
• What is MapReduce?
• What are MapReduce implementations?
Facing these questions I have make a personal research, and realize a synthesis, which has help me to clarify some ideas. The attached presentation does not intend to be exhaustive on the subject, but could perhaps bring you some useful insights.
The document discusses limitations of the Von Neumann architecture and opportunities for parallel processing through non-Von Neumann architectures. It provides background on the Von Neumann model and its key components. The document then explains how increasing demand for faster computers is driving researchers to explore parallel processing approaches like SIMD and MIMD that can solve larger, more complex problems by distributing work across multiple processors. It aims to describe non-Von Neumann architectures and parallel algorithms.
This document discusses deploying infrastructure as a service (IaaS) using Eucalyptus. Eucalyptus is an open-source software platform that provides IaaS and enables on-premise private clouds. It uses existing infrastructure to create a scalable, secure web services layer for compute, network and storage. The architecture of Eucalyptus includes a Cloud Controller, Cluster Controllers, Storage Controller, and Node Controllers that manage VM execution and network scheduling. Eucalyptus can dynamically scale resources based on application workloads. The document discusses using Ubuntu 12.04 on the Eucalyptus front-end and Xen as the underlying hypervisor on backend nodes.
Distributed database management systemsDhani Ahmad
This chapter discusses distributed database management systems (DDBMS). A DDBMS governs storage and processing of logically related data across interconnected computer systems. The chapter covers DDBMS components, levels of data and process distribution, transaction management, and design considerations like data fragmentation, replication, and allocation. Transparency and optimization techniques aim to make the distributed nature transparent to users.
The document discusses operating systems, their components, functions, and history. It provides an overview of:
1) What an operating system is and its main goals of executing programs, making the computer convenient to use, and efficiently managing hardware resources.
2) The typical components of a computer system including hardware, operating system, application programs, and users.
3) The functions of an operating system which include providing a user environment, resource management, and error detection.
The document discusses different buffering techniques and disk scheduling algorithms used in operating systems. It describes single buffering, double buffering, and circular buffering techniques. For disk scheduling, it explains first-come, first-served (FCFS), shortest seek time first (SSTF), SCAN, C-SCAN, LOOK, and C-LOOK algorithms. It provides examples to calculate head movements using FCFS and SSTF scheduling.
Abstract:
Extensive research has been done in prefetching techniques that hide memory latency in microprocessors leading to performance improvements. However, the energy aspect of prefetching is relatively unknown. While aggressive prefetching techniques often help to improve performance, they increase energy consumption by as much as 30% in the memory system. This paper provides a detailed evaluation on the energy impact of hardware data prefetching and then presents a set of new energy-aware techniques to overcome prefetching energy overhead of such schemes. These include compiler-assisted and hardware-based energy-aware techniques and a new power-aware prefetch engine that can reduce hardware prefetching related energy consumption by 7-11 ×. Combined with the effect of leakage energy reduction due to performance improvement, the total energy consumption for the memory system after the application of these techniques can be up to 12% less than the baseline with no prefetching.
The document discusses an instruction-based stride prefetcher that uses a reference prediction table (RPT) to track load instructions and memory addresses. It examines how the maximum prefetch degree affects prefetcher performance. The results show that increasing the maximum degree improves coverage but performance peaks at a degree of 5, providing the highest average speedup of 1.085 compared to no prefetching. While a higher degree increases coverage, prefetching too many blocks negatively impacts performance.
The document discusses the concept of virtual memory. Virtual memory allows a program to access more memory than what is physically available in RAM by storing unused portions of the program on disk. When a program requests data that is not currently in RAM, it triggers a page fault that causes the needed page to be swapped from disk into RAM. This allows the illusion of more memory than physically available through swapping pages between RAM and disk as needed by the program during execution.
This document provides an overview of an operating systems concepts textbook. It introduces key topics covered in the book like computer system organization, operating system structure and functions, process management, memory management, storage management, and security. The objectives are to provide a tour of major OS components and coverage of basic computer system organization. It describes the four main components of a computer system and how the operating system acts as an intermediary between the user, hardware, and application programs.
In recent years, we have seen an overwhelming number of TV commercials that promise that the Cloud can help with many problems, including some family issues. What stands behind the terms “Cloud” and “Cloud Computing,” and what we can actually expect from this phenomenon? A group of students of the Computer Systems Technology department and Dr. T. Malyuta, whom has been working with the Cloud technologies since its early days, will provide an overview of the business and technological aspects of the Cloud.
We are predicting Heart Disease by Taking 14 Medical Parameters as an inputs through 2 data Minning Techniques(Decision Tree(Faster) And KNN neighbour Algorithms(Slower)).
And Visualizing The dataset.If the output 1 then it means Higher Chances of getting Heart Attack ,if 0 then it means Less chances of Heart Attack.
Two-level paging is used to divide the large page table into smaller pieces called page tables. A logical address is divided into a page number and page offset, and the page number is further divided to index the outer page table and inner page table. Inverted page tables store one entry per physical page with the owning process and virtual page number instead of physical addresses. This reduces the page table size significantly but increases translation time. Hashed inverted page tables add a hash table to map process/virtual page number pairs to page table entries, reducing average translation time.
DSM system
Shared memory
On chip memory
Bus based multiprocessor
Working through cache
Write through cache
Write once protocol
Ring based multiprocessor
Protocol used
Similarities and differences b\w ring based and bus based
Introduction, Central Processing Unit (CPU) Memory, Communication between Various Units of a Computer System, The Instruction Format, Instruction Set, Processor Speed, Multiprocessor Systems.
The CPU acts as the computer's brain and carries out instructions from programs. It has two main components: the control unit, which selects and coordinates instruction execution, and the arithmetic logic unit, which performs calculations. Registers temporarily store data during instruction processing, including special purpose registers like the program counter, accumulator, and input/output registers. The CPU communicates with main memory, usually RAM, and cache memory for faster access to active data. It fetches instructions from memory and decodes and executes them in a multi-step process controlled by the control unit.
Here is how you can solve this problem using MapReduce and Unix commands:
Map step:
grep -o 'Blue\|Green' input.txt | wc -l > output
This uses grep to search the input file for the strings "Blue" or "Green" and print only the matches. The matches are piped to wc which counts the lines (matches).
Reduce step:
cat output
This isn't really needed as there is only one mapper. Cat prints the contents of the output file which has the count of Blue and Green.
So MapReduce has been simulated using grep for the map and cat for the reduce functionality. The key aspects are - grep extracts the relevant data (map
• What is MapReduce?
• What are MapReduce implementations?
Facing these questions I have make a personal research, and realize a synthesis, which has help me to clarify some ideas. The attached presentation does not intend to be exhaustive on the subject, but could perhaps bring you some useful insights.
The document discusses limitations of the Von Neumann architecture and opportunities for parallel processing through non-Von Neumann architectures. It provides background on the Von Neumann model and its key components. The document then explains how increasing demand for faster computers is driving researchers to explore parallel processing approaches like SIMD and MIMD that can solve larger, more complex problems by distributing work across multiple processors. It aims to describe non-Von Neumann architectures and parallel algorithms.
This document discusses deploying infrastructure as a service (IaaS) using Eucalyptus. Eucalyptus is an open-source software platform that provides IaaS and enables on-premise private clouds. It uses existing infrastructure to create a scalable, secure web services layer for compute, network and storage. The architecture of Eucalyptus includes a Cloud Controller, Cluster Controllers, Storage Controller, and Node Controllers that manage VM execution and network scheduling. Eucalyptus can dynamically scale resources based on application workloads. The document discusses using Ubuntu 12.04 on the Eucalyptus front-end and Xen as the underlying hypervisor on backend nodes.
Distributed database management systemsDhani Ahmad
This chapter discusses distributed database management systems (DDBMS). A DDBMS governs storage and processing of logically related data across interconnected computer systems. The chapter covers DDBMS components, levels of data and process distribution, transaction management, and design considerations like data fragmentation, replication, and allocation. Transparency and optimization techniques aim to make the distributed nature transparent to users.
The document discusses operating systems, their components, functions, and history. It provides an overview of:
1) What an operating system is and its main goals of executing programs, making the computer convenient to use, and efficiently managing hardware resources.
2) The typical components of a computer system including hardware, operating system, application programs, and users.
3) The functions of an operating system which include providing a user environment, resource management, and error detection.
The document discusses different buffering techniques and disk scheduling algorithms used in operating systems. It describes single buffering, double buffering, and circular buffering techniques. For disk scheduling, it explains first-come, first-served (FCFS), shortest seek time first (SSTF), SCAN, C-SCAN, LOOK, and C-LOOK algorithms. It provides examples to calculate head movements using FCFS and SSTF scheduling.
Abstract:
Extensive research has been done in prefetching techniques that hide memory latency in microprocessors leading to performance improvements. However, the energy aspect of prefetching is relatively unknown. While aggressive prefetching techniques often help to improve performance, they increase energy consumption by as much as 30% in the memory system. This paper provides a detailed evaluation on the energy impact of hardware data prefetching and then presents a set of new energy-aware techniques to overcome prefetching energy overhead of such schemes. These include compiler-assisted and hardware-based energy-aware techniques and a new power-aware prefetch engine that can reduce hardware prefetching related energy consumption by 7-11 ×. Combined with the effect of leakage energy reduction due to performance improvement, the total energy consumption for the memory system after the application of these techniques can be up to 12% less than the baseline with no prefetching.
The document discusses an instruction-based stride prefetcher that uses a reference prediction table (RPT) to track load instructions and memory addresses. It examines how the maximum prefetch degree affects prefetcher performance. The results show that increasing the maximum degree improves coverage but performance peaks at a degree of 5, providing the highest average speedup of 1.085 compared to no prefetching. While a higher degree increases coverage, prefetching too many blocks negatively impacts performance.
THE EFFECTIVE WAY OF PROCESSOR PERFORMANCE ENHANCEMENT BY PROPER BRANCH HANDL...cscpconf
The processor performance is highly dependent on the regular supply of correct instruction at
the right time. To reduce instruction cache misses, one of the proposed mechanism is the
instruction prefetching, which in turn will increase instructions supply to the processor. The
technology developments in these fields indicates that in future the gap between processing
speeds of processor and data transfer speed of memory is likely to be increased. Memory bandwidth can be increased significantly using the prefetching, but unsuccessful prefetches will pollute the primary cache. Prefetching can be done either with software or hardware. In software prefetching the compiler will insert a prefetch code in the program. In this case as actual memory capacity is not known to the compiler and it will lead to some harmful prefetches. In hardware prefetching instead of inserting prefetch code it will make use of extra hardware and which is utilized during the execution. The most significant source of lostperformance when the process waiting for the availability of the next instruction. All the prefetching methods are giving stress only to the fetching of the instruction for the execution, not to the overall performance of the processor. This paper is an attempt to study the branch handling in a uniprocessing environment, where, when ever branching is identified the proper cache memory management is enabled inside the memory management unit.
The effective way of processor performance enhancement by proper branch handlingcsandit
The processor performance is highly dependent on the regular supply of correct instruction at
the right time. To reduce instruction cache misses, one of the proposed mechanism is the
instruction prefetching, which in turn will increase instructions supply to the processor. The
technology developments in these fields indicates that in future the gap between processing
speeds of processor and data transfer speed of memory is likely to be increased. Memory
bandwidth can be increased significantly using the prefetching, but unsuccessful prefetches will
pollute the primary cache. Prefetching can be done either with software or hardware. In
software prefetching the compiler will insert a prefetch code in the program. In this case as
actual memory capacity is not known to the compiler and it will lead to some harmful
prefetches. In hardware prefetching instead of inserting prefetch code it will make use of extra
hardware and which is utilized during the execution. The most significant source of lost
performance when the process waiting for the availability of the next instruction. All the
prefetching methods are giving stress only to the fetching of the instruction for the execution,
not to the overall performance of the processor. This paper is an attempt to study the branch
handling in a uniprocessing environment, where, when ever branching is identified the proper
cache memory management is enabled inside the memory management unit.
The document describes several hardware-based data prefetching schemes that aim to reduce memory stalls by prefetching data into caches before it is needed by a program. It introduces fixed offset prefetching, stride-based prefetching, and tag correlated prefetching. It then discusses the simulation setup used to evaluate these schemes and presents results on their performance in terms of CPI, cache hit rate, and average memory access time. The tag correlated prefetching scheme achieved the best overall performance but at the cost of higher hardware complexity compared to the other schemes.
AFFECT OF PARALLEL COMPUTING ON MULTICORE PROCESSORScscpconf
Our main aim of research is to find the limit of Amdahl's Law for multicore processors, to make number of cores giving more efficiency to overall architecture of the CMP(Chip Multi
Processor a.k.a. Multicore Processor). As it is expected this limit will be in the architecture of Multicore Processor, or in the programming. We surveyed the architecture of the Multicore
processors of various chip manufacturers namely INTEL™, AMD™, IBM™ etc., and the various techniques there followed in, for improving the performance of the Multicore
Processors. We conducted cluster experiments to find this limit. In this paper we propose an alternate design of Multicore processor based on the results of our cluster experiment.
Affect of parallel computing on multicore processorscsandit
Our main aim of research is to find the limit of Amdahl's Law for multicore processors, to make
number of cores giving more efficiency to overall architecture of the CMP(Chip Multi
Processor a.k.a. Multicore Processor). As it is expected this limit will be in the architecture of
Multicore Processor, or in the programming. We surveyed the architecture of the Multicore
processors of various chip manufacturers namely INTEL™, AMD™, IBM™ etc., and the
various techniques there followed in, for improving the performance of the Multicore
Processors.
We conducted cluster experiments to find this limit. In this paper we propose an alternate design
of Multicore processor based on the results of our cluster experiment.
The paper includes a study of the most recent prefetching techniques developed for modern day processors, classifying them based on different criteria and performing a qualitative and quantitative evaluation of their performance. It also includes evaluation of the performance of compiler based data prefetching scheme using the built-in prefetcher of gcc compiler.
AN ATTEMPT TO IMPROVE THE PROCESSOR PERFORMANCE BY PROPER MEMORY MANAGEMENT F...IJCSEA Journal
The performanceof the processor is highly dependent on the regular supply of correct instruction at the right time. Whenever a data miss is occurring in the cache memory the processor has to spend more cycles for the fetching operation. One of the methodsused to reduce instruction cache miss is the instruction prefetching,which in turn will increase instructions supply to the processor.The technology developments in these fields indicates that in future the gap between processing speeds of processor and data transfer speed of memory is likely to be increased. Branch Predictor play a critical role in achieving effective performance in many modernpipelined microprocessor architecture.
Prefetching canbe done either with software or hardware. In software prefetching the compiler will insert a prefetch code in the program. In this case as actual memory capacity is not known to the compiler and it will lead to some harmful prefetches. In hardware prefetching instead of inserting prefetch code it will make use of extra hardware and which is utilized during the execution. The most significant source of lost performance when the process waiting for the availability of the next instruction. Thetime that is wasted in case of branch misprediction is equal to the number of stages in the pipeline, starting from fetch stage to execute stage. All the prefetching methods are givenstress only to the fetching of the instruction for the execution, not to the overall performance of the processor. The most significant source of lost performance is,when the process is waiting for the availability of the next instruction. The time that is wasted in case of branch misprediction is equal to the number of stages in the pipeline, starting from fetch stage to execution stage.This paper we made an attempt to study the branch handling in a uniprocessing environment, whenever branching is identified instead of invoking the branch prediction the proper cache memory management is enabled inside the memory management unit.
These days fast code needs to operate in harmony with its environment. At the deepest level this means working well with hardware: RAM, disks and SSDs. A unifying theme is treating memory access patterns in a uniform and predictable that is sympathetic to the underlying hardware. For example writing to and reading from RAM and Hard Disks can be significantly sped up by operating sequentially on the device, rather than randomly accessing the data.
In this talk we’ll cover why access patterns are important, what kind of speed gain you can get and how you can write simple high level code which works well with these kind of patterns.
The document discusses parallel computing platforms and trends in microprocessor architectures that enable implicit parallelism. It covers topics like pipelining, superscalar execution, limitations of memory performance, and how caches can improve effective memory latency. The key points are:
1) Microprocessor clock speeds have increased dramatically but limitations remain regarding memory latency and bandwidth. Parallelism addresses performance bottlenecks in processors, memory, and communication.
2) Techniques like pipelining and superscalar execution exploit implicit parallelism by executing multiple instructions concurrently, but dependencies and branch prediction limit performance gains.
3) Memory latency is often the bottleneck, but caches can reduce effective latency through data reuse and temporal locality.
This document provides an overview of cache partitioning techniques (CPTs) in multicore processors. It begins with background on the motivation for CPTs due to increasing cache contention with more cores. It then covers various classifications of CPTs including granularity (way, set, block), static vs dynamic, strict vs pseudo, and hardware vs software control. It discusses challenges of CPTs like profiling overhead and complexity. It also covers techniques for profiling cache usage and determining optimal partitions. The goal of CPTs is to improve performance by reducing interference between applications sharing a cache.
The document discusses key concepts in computer architecture including Amdahl's law for predicting speedup from parallelization, branch predictors for improving instruction flow, cache organization and types, hazards that can occur in pipelines, interrupts for responding to events, and jump instructions for breaking standard instruction flow. It provides simplified explanations of these concepts in an accessible way for learning purposes.
The document discusses key concepts in computer architecture including Amdahl's law for predicting speedup from parallelization, branch predictors for improving instruction flow, cache organization and types, hazards that can occur in pipelines, interrupts for responding to events, and jump instructions for breaking standard instruction flow. It provides simplified explanations of these concepts in an accessible way for learning purposes.
Four common events that lead to the creation of a process are:
1) A new batch job
2) An interactive logon
3) Being created by the operating system to provide a service
4) Being spawned by an existing process.
When context switching between processes, the kernel saves the state of the current process, determines the next process to run using the scheduler, and then restores the state of the next process.
A thread is a single sequential flow of control within a process. It shares the process's resources but has its own stack and registers. When a thread is created, a context including a register set and local stack is created.
High-Performance Physics Solver Design for Next Generation ConsolesSlide_N
This document discusses optimizing physics simulations on the Cell processor for next generation game consoles. It describes parallelizing simulations across the multiple cores of the Cell processor by distributing independent solvers or breaking single solvers into parallel tasks. It also discusses techniques for optimizing performance on each core like streaming data transfers to minimize memory usage, and double buffering to hide data transfer latency. Demos are provided of optimizing cloth and rigid body simulations using these techniques.
The document discusses buffering and caching in disk management. It defines buffering as temporarily storing data in memory as it moves between devices or applications. Buffers help adjust timing and act as placeholders. Caching stores a subset of frequently accessed data to improve performance. It increases data retrieval speed and application efficiency. There are different types of caches including site caches for static content, browser caches for clients, server caches for high traffic sites, and micro caches for dynamic sites. Caching provides advantages like reducing database costs and backend load, while disadvantages include limited storage capacity and temporary data storage.
This document discusses various techniques for optimizing website performance, including:
1. Network optimizations like compression, HTTP caching, and keeping connections alive.
2. Structuring content efficiently and using tools like YSlow to measure performance.
3. Application caching of pages, database queries, and other frequently accessed content.
4. Database tuning through indexing, query optimization, and offloading text searches.
5. Monitoring resource usage and business metrics to ensure performance meets targets.
DESIGNED DYNAMIC SEGMENTED LRU AND MODIFIED MOESI PROTOCOL FOR RING CONNECTED...Ilango Jeyasubramanian
This document proposes and evaluates several cache designs for improving performance and energy efficiency in multi-core processors. It introduces a filter cache shared among cores to reduce energy consumption. It then implements a segmented least recently used replacement policy and adaptive bypassing to further improve cache hit rates. Finally, it modifies the MOESI coherence protocol for a ring interconnect topology to address data coherence across cores. Simulations show the proposed cache designs reduce energy usage by 11% and increase cache hit rates by up to 7% compared to baseline designs.
This document discusses different memory management techniques:
- It describes swapping, where a process is temporarily moved out of memory to disk to make room for other processes. Paging and segmentation are also covered, where memory is divided into pages/segments and logical addresses are translated to physical addresses.
- Memory management aims to allocate processes efficiently in memory while avoiding issues like fragmentation. Techniques like contiguous allocation, paging, and segmentation map logical addresses to physical frames and protect memory access.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
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1. Made by- Himanshu Koli (2K10/CO/041)
Hiren Madan (2K10/CO/042)
Energy-Efficient Hardware Data Prefetching
SEMINAR
Delhi Technological University
(COE-416)
2. Contents
Introduction
What is Data Prefetching?
Prefetching Classification
How Prefetching works?
Software Prefetching
Limitations of Software based Prefetching
Hardware Prefetching
Hardware Vs. Software Approach
Energy Aware Data Prefetching
Energy Aware Prefetching Architecture
Energy Aware Prefetching Techniques
References
3. Introduction
Why need Data Prefetching?
Microprocessor performance has increased at a dramatic rate .
Expanding gap between microprocessor and DRAM performance has necessitated the
use of aggressive techniques designed to reduce the large latency of memory accesses.
Use of cache memory hierarchies have managed to keep pace with processor memory
request rates but continue to be too expensive for a main store technology.
Use of large cache hierarchies has proven to be effective in reducing the average
memory access penalty for programs that show a high degree of locality in their
addressing patterns .
But scientific and other data-intensive programs spend more than half their run
times stalled on memory requests.
5. On demand fetch policy, it will always result in a cache miss for
the first access to a cache block Such cache misses are known
as cold start or compulsory misses.
When we reference a large array, there is a high possibility of
the elements of the array to be overwritten
If we need the previous value of the array which has been
overwritten, then the processor need to make full main
memory access. This is called as capacity miss.
6. What is Data Prefetching ?
Data prefetching anticipates such misses and issues a fetch to
the memory system in advance of the actual memory reference,
rather than waiting for a cache miss to perform a memory fetch .
Prefetch proceeds in parallel with processor computation,
allowing the memory system time to transfer the desired data
from main memory to the cache.
Prefetch will complete just in time for the processor to access the
needed data in the cache without stalling the processor.
9. Prefetching Classification
Various prefetching techniques have been proposed-
Instruction Prefetching vs. Data Prefetching
Software-controlled prefetching vs. Hardware-controlled
prefetching.
Data prefetching for different structures in general purpose
programs:
Prefetching for array structures.
Prefetching for pointer and linked data structures.
10. Software Data Prefetching
Explicit “fetch” instructions
Non-blocking memory operation.
Cannot cause exceptions (e.g. page faults).
Additional instructions executed.
Modest hardware complexity
Challenge -- prefetch scheduling
Placement of fetch instruction relative to the matching load and store
instruction.
Hand-coded by programmer or automated by compiler.
11. Adding just a few prefetch directives to a program can substantially
improve performance.
Prefetching is most often used within loops responsible for large array
calculations.
Common in scientific codes
Poor cache utilization
Predictable array referencing patterns
Fetch instructions can be placed inside loop bodies so that current
iteration prefetches data for a future iteration.
12. Example : Vector Product
No prefetching
for (i = 0; i < N; i++)
{ sum += a[i]*b[i]; }
Assume each cache block holds 4
elements .
Code segment will cause a cache
miss every fourth iteration.
Simple prefetching
for (i = 0; i < N; i++)
{
fetch (&a[i+1]);
fetch (&b[i+1]);
sum += a[i]*b[i];
}
Problem-
Unnecessary prefetch operations
13. Example (contd.)
Prefetching + loop unrolling
for (i = 0; i < N; i+=4)
{
fetch (&a[i+4]);
fetch (&b[i+4]);
sum += a[i]*b[i];
sum += a[i+1]*b[i+1];
sum += a[i+2]*b[i+2];
sum += a[i+3]*b[i+3];
}
Problem
First and last iterations
fetch (&sum);
fetch (&a[0]);
fetch (&b[0]);
for (i = 0; i < N-4; i+=4
{
fetch (&a[i+4]);
fetch (&b[i+4]);
sum += a[i]*b[i];
sum += a[i+1]*b[i+1];
sum += a[i+2]*b[i+2];
sum += a[i+3]*b[i+3];
}
for (i = N-4; i < N; i++)
sum = sum + a[i]*b[i];
14. Example (contd.)
Previous assumption: prefetching 1
iteration ahead is sufficient to hide the
memory latency.
When loops contain small
computational bodies, it may be
necessary to initiate prefetches d
iterations before the data is referenced.
d: prefetch distance
l: avg. memory latency
s: is the estimated cycle time of the shortest possible
execution path through one loop iteration
fetch (&sum);
for (i = 0; i < 12; i += 4)
{
fetch (&a[i]);
fetch (&b[i]);
}
for (i = 0; i < N-12; i += 4)
{
fetch(&a[i+12]);
fetch(&b[i+12]);
sum = sum + a[i] *b[i];
sum = sum + a[i+1]*b[i+1];
sum = sum + a[i+2]*b[i+2];
sum = sum + a[i+3]*b[i+3];
}
for (i = N-12; i < N; i++)
sum = sum + a[i]*b[i];
s
l
d
15. Limitation of Software-based
Prefetching
Normally restricted to loops with array accesses
Hard for general applications with irregular access
patterns
Processor execution overhead
Significant code expansion
Performed statically.
16. Hardware Data Prefetching
Special Hardware required.
No need for programmer or compiler intervention.
No changes to existing executable.
Take advantage of run-time information.
17. Sequential Prefetching
By grouping consecutive memory words into single units, caches exploit the principle of spatial locality to
implicitly prefetch data that is likely to be referenced in the near future.
Larger cache blocks suffer from
cache pollution
false sharing in multiprocessors.
One block lookahead (OBL) approach
Initiate a prefetch for block b+1 when block b is accessed.
Prefetch-on-miss
Whenever an access for block b results in a cache miss
Tagged prefetch
Associates a tag bit with every memory block.
When a block is demand-fetched or a prefetched block is referenced for the first time, next block is
fetched.
Used in HP PA7200
18. OBL may not be initiated far enough in advance of the actual use to avoid a
processor memory stall.
To solve this, increase the number of blocks prefetched after a demand fetch
from one to K, where K is known as the degree of prefetching.
Aids the memory system in staying ahead of rapid processor requests.
As each prefetched block, b, is accessed for the first time, the cache is
interrogated to check if blocks b+1, ... b+K are present in the cache and, if
not, the missing blocks are fetched from memory.
19. Three Forms of Sequential Prefetching:
a) Prefetch on miss, b) Tagged Prefetch and
c) Sequential Prefetching with K = 2.
20. Shortcoming
Prefetch K > 1 subsequent blocks
Additional traffic and cache pollution.
Solution : Adaptive sequential prefetching
Vary the value of K during program execution
High spatial locality large K value
Prefetch efficiency metric periodically calculated
Ratio of useful prefetches to total prefetches
21. The value of K is initialized to one, incremented whenever the prefetch
efficiency exceeds a predetermined upper threshold and decremented
whenever the efficiency drops below a lower threshold
If K is reduced to zero, prefetching is disabled and the prefetch hardware
begins to monitor how often a cache miss to block b occurs while block b-
1 is cached
Prefetching restarts if the respective ratio of these two numbers exceeds
the lower threshold of the prefetch efficiency.
23. Stride Prefetching
Stride Prefetching monitors memory access patterns in the processor
to detect constant-stride array references originating from loop
structures.
Accomplished by comparing successive addresses used by memory
instructions.
Requires the previous address used by a memory instruction to be
stored along with the last detected stride, a hardware table called the
Reference Prediction Table (RPT), is added to hold the information
for the most recently used load instructions.
24. Each RPT entry contains the PC address of the load instruction, the
memory address previously accessed by the instruction, a stride value
for those entries that have established a stride, and a state field used to
control the actual prefetching.
Contains 64 entries; each entry of 64 bits.
Prefetch commands are issued only when a matching stride is detected
However, stride prefetching uses an associative hardware table which is
accessed whenever a load instruction is detected.
25. Pointer Prefetching
Effective for pointer intensive programs containing linked data
structures.
No constant stride.
Dependence based prefetching-
Uses two hardware tables.
Correlation table (CT) stores dependence correlationbetween a load
instruction that produces an address (producer) and a subsequent load that
uses that address (consumer).
The potential producer window (PPW) records the most recent loaded values
and the corresponding instructions. When a load commits, the
corresponding correlation is added to CT.
26. Combined Stride and Pointer
Prefetching
Objective to evaluate a technique that would work for all
types of memory access patterns.
Use both array and pointer
Better performance
All three tables (RPT, PPW, CT)
27. Hardware vs. Software Approach
Hardware
Perform. cost: low
Memory traffic: high
History-directed
could be less effective
Using profiling info.
Software
Perform. cost: high
Memory traffic: low
Better Improvement
Use human knowledge
inserted by hand
28. Energy Aware Data Prefetching
Energy and power efficiency have become key design objectives in
microprocessors, in both embedded and general-purpose domains.
Aggressive prefetching techniques often help to improve performance, in most of
the applications, but they increase memory system energy consumption by as
much as 30%.
Power-consumption sources
Prefetching hardware
Prefetch history tables
Control logic
Extra memory accesses
Unnecessary prefetching
29. Figure shows Power Dissipation in new
processors compared with other objects
4004
8008
8080
8085
8086
286 386
486
Pentium®
Processors
1
10
100
1000
10000
1970 1980 1990 2000 2010
PowerDensity(W/cm2)
Source: Intel
Hot Plate
Nuclear Reactor
Rocket Nozzle
Sun’s Surface
31. Prefetching Energy Sources
Prefetching hardware:
Data (history table) and control logic.
Extra tag-checks in L1 cache
When a prefetch hits in L1 (no prefetch needed)
Extra memory accesses to L2 Cache
Due to useless prefetches from L2 to L1.
Extra off-chip memory accesses
When data cannot be found in the L2 Cache.
33. Energy-Aware Prefetching Technique
Compiler-Based Selective Filtering (CBSF)
Only searching the prefetch hardware tables for selective memory instructions
identified by the compiler.
Compiler-Assisted Adaptive Prefetching (CAAP)
Selectively applying different prefetching schemes depending on predicted access
patterns.
Compiler-driven Filtering using Stride Counter (SC)
Reducing prefetching energy consumption wasted on memory access patterns
with very small strides.
Hardware-based Filtering using PFB (PFB)
Further reducing the L1 cache related energy overhead due to prefetching based
on locality with prefetching addresses.
34. Compiler-based Selective Filtering
Only searching the prefetch hardware tables for selective
memory instructions identified by the compiler.
Energy reduced by-
Using loop or recursive type memory access
Use only array and linked data structure memory access
35. Compiler-Assistive Adaptive Prefetching
Select different prefetching scheme based on
Memory access to an array which does not belongs to any larger
structure are only fed into the stride prefetcher.
Memory access to an array which belongs to a larger structure are
fed into both stride and pointer prefetchers.
Memory access to a linked data structure with no arrays are only
fed into the pointer prefetcher.
Memory access to a linked data structure that contains arrays are
fed into both prefetchers.
36. Compiler-Hinted Filtering Using a
Runtime SC
Reducing prefetching energy consumption wasted on memory
access patterns with very small strides.
Small strides are not used.
Stride can be larger than half the cache line size.
Each cache line contain
Program Counter(PC)
Stride counter
Counter is used to count how many times the instruction
occurs.
37. Hardware-based Filtering using PFB
To reduce the number of L1 tag-checks due to prefetching, we add a
PFB to remember the most recently prefetched cache tags.
We check the prefetching address against the PFB when a prefetching
request is issued by the prefetch engine.
If the address is found in the PFB, the prefetching request is dropped
and we assume that the data is already in the L1 cache.
When the data is not found in the PFB, we perform normal tag lookup
and proceed according to the lookup results.
The LRU replacement algorithm is used when the PFB is full.
38. Power Dissipation of Hardware Tables
The size of a typical history table is at least 64X64 bits, which is
implemented as a fully-associative CAM table.
Each prefetching access consumes more than 12 mW, which is higher
than our low-power cache access.
Low-power cache design techniques such as sub-banking don’t work.
39. Conclusion
Improve the performance.
Reduce the energy overhead of hardware data prefetching.
Reduce total energy consumption.
Compiler-assisted and hardware-based energy-aware
techniques and a new power-aware prefetch engine
techniques are used.
40. References
Yao Guo ,”Energy-Efficient Hardware Data Prefetching,” IEEE
,vol.19,no.2,Feb.2011
A. J. Smith, “Sequential program prefetching in memory
hierarchies,”IEEE Computer, vol. 11, no. 12, pp. 7–21, Dec.
1978.
A. Roth, A. Moshovos, and G. S. Sohi, “Dependence based
prefetching for linked data structures,” in Proc. ASPLOS-VIII,
Oct. 1998, pp.115–126.