This chapter discusses various biasing circuits used for field effect transistors (FETs). It describes fixed-bias, self-bias, and voltage divider bias configurations for JFETs and MOSFETs. The key steps to analyze self and voltage divider bias circuits are: 1) Plot the transistor transfer curve and bias line, 2) Find the Q-point where they intersect, 3) Use the Q-point values to calculate the other circuit voltages and currents. D-type MOSFET biasing is similar to JFET biasing, except they can operate with positive VGS values and higher ID values than IDSS.

1. CCCChhhhaaaapppptttteeeerrrr 7:
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2. Common CCCCCCCooooooommmmmmmmmmmmmmooooooonnnnnnn FFFFFFFFEEEEEEEETTTTTTTT BBBBBBBBiiiiiiiiaaaaaaaassssssssiiiiiiiinnnnnnnngggggggg CCCCCCCCiiiiiiiirrrrrrrrccccccccuuuuuuuuiiiiiiiittttttttssssssss
JJJJJJJJFFFFFFFFEEEEEEEETTTTTTTT BBBBBBBBiiiiiiiiaaaaaaaassssssssiiiiiiiinnnnnnnngggggggg CCCCCCCCiiiiiiiirrrrrrrrccccccccuuuuuuuuiiiiiiiittttttttssssssss
• FFFFiiiixxxxeeeedddd – BBBBiiiiaaaassss
• SSSSeeeellllffff-BBBBiiiiaaaassss
• VVVVoooollllttttaaaaggggeeee-DDDDiiiivvvviiiiddddeeeerrrr BBBBiiiiaaaassss
D-TTTTTTTTyyyyyyyyppppppppeeeeeeee MMMMMMMMOOOOOOOOSSSSSSSSFFFFFFFFEEEEEEEETTTTTTTT BBBBBBBBiiiiiiiiaaaaaaaassssssssiiiiiiiinnnnnnnngggggggg CCCCCCCCiiiiiiiirrrrrrrrccccccccuuuuuuuuiiiiiiiittttttttssssssss
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
•SSSSeeeellllffff-BBBBiiiiaaaassss
•VVVVoooollllttttaaaaggggeeee-DDDDiiiivvvviiiiddddeeeerrrr BBBBiiiiaaaassss
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•VVVVoooollllttttaaaaggggeeee-DDDDiiiivvvviiiiddddeeeerrrr BBBBiiiiaaaassss
2

3. Basic Current BBBBBBBaaaaaaasssssssiiiiiiiccccccc CCCCCCCuuuuuuurrrrrrrrrrrrrreeeeeeennnnnnnttttttt RRRRRRRReeeeeeeellllllllaaaaaaaattttttttiiiiiiiioooooooonnnnnnnnsssssssshhhhhhhhiiiiiiiippppppppssssssss
For all FETs:
IG ≅ 0A
ID=IS
For JFETS and D-Type MOSFETs:
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
D DSS V
Electronic Devices and Circuit Theory, 10/e
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2
GS
P
V

1 I I  


 


= −
For E-Type MOSFETs:
2
ID = k(VGS − VT )
3

4. FFFFFFFFiiiiiiiixxxxxxxxeeeeeeeedddddddd-BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCoooooooonnnnnnnnffffffffiiiiiiiigggggggguuuuuuuurrrrrrrraaaaaaaattttttttiiiiiiiioooooooonnnnnnnn
V = V −
I R
DS DD D D
V 0V
S
=
V =
V
C DS
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V V
GS
=
V = −
V
GS GG
Electronic Devices and Circuit Theory, 10/e
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5. SSSSSSSSeeeeeeeellllllllffffffff-BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCoooooooonnnnnnnnffffffffiiiiiiiigggggggguuuuuuuurrrrrrrraaaaaaaattttttttiiiiiiiioooooooonnnnnnnn
Copyright ©2009 by Pearson Education, Inc.
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
5

6. SSSSSSSSeeeeeeeellllllllffffffff-BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCaaaaaaaallllllllccccccccuuuuuuuullllllllaaaaaaaattttttttiiiiiiiioooooooonnnnnnnnssssssss
VGS = −IDRS
For the indicated loop,
TTTToooo ssssoooollllvvvveeee tttthhhhiiiissss eeeeqqqquuuuaaaattttiiiioooonnnn::::
• SSSSeeeelllleeeecccctttt aaaannnn IIIID <<<< IIIIDDDDSSSSSSSS aaaannnndddd uuuusssseeee tttthhhheeee ccccoooommmmppppoooonnnneeeennnntttt
vvvvaaaalllluuuueeee ooooffff RRRRSSSS ttttoooo ccccaaaallllccccuuuullllaaaatttteeee VVVVGGGGSSSS
• PPPPllllooootttt tttthhhheeee ppppooooiiiinnnntttt iiiiddddeeeennnnttttiiiiffffiiiieeeedddd bbbbyyyy IIIID aaaannnndddd VVVVGGGGSSSS. DDDDrrrraaaawwww aaaa
lllliiiinnnneeee ffffrrrroooommmm tttthhhheeee oooorrrriiiiggggiiiinnnn ooooffff tttthhhheeee aaaaxxxxiiiissss ttttoooo tttthhhhiiiissss ppppooooiiiinnnntttt.
• PPPPllllooootttt tttthhhheeee ttttrrrraaaannnnssssffffeeeerrrr ccccuuuurrrrvvvveeee uuuussssiiiinnnngggg IIIIDDDDSSSSSSSS aaaannnndddd
VP ((((VVVVP ==== VVVVGGGGSSSSooooffffffff iiiinnnn ssssppppeeeecccciiiiffffiiiiccccaaaattttiiiioooonnnn sssshhhheeeeeeeettttssss)))) aaaannnndddd aaaa ffffeeeewwww
ppppooooiiiinnnnttttssss ssssuuuucccchhhh aaaassss IIIID ==== IIIIDDDDSSSSSSSS / 4 aaaannnndddd IIIID ==== IIIIDDDDSSSSSSSS //// 2222 eeeettttcccc.
Copyright ©2009 by Pearson Education, Inc.
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The Q-point is located where the first line
intersects the transfer curve. Use the value
of ID at the Q-point (IDQ) to solve for the
other voltages:
V = V − I (R +
R )
DS DD D S D
V =
I R
S D S
V = V + V = V −
V
D DS S DD RD
Electronic Devices and Circuit Theory, 10/e
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7. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr BBBBBBBBiiiiiiiiaaaaaaaassssssss
IG ==== 0000 A
ID rrrreeeessssppppoooonnnnddddssss ttttoooo cccchhhhaaaannnnggggeeeessss iiiinnnn
VGGGGSSSS.
Copyright ©2009 by Pearson Education, Inc.
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
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8. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCaaaaaaaallllllllccccccccuuuuuuuullllllllaaaaaaaattttttttiiiiiiiioooooooonnnnnnnnssssssss
VG is equal to the voltage across
divider resistor R2:
R V
2 DD
G R R
1 2
V
+
=
Using Kirchhoff’s Law:
VGS = VG − IDRS
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TTTThhhheeee QQQQ ppppooooiiiinnnntttt iiiissss eeeessssttttaaaabbbblllliiiisssshhhheeeedddd bbbbyyyy
pppplllloooottttttttiiiinnnngggg aaaa lllliiiinnnneeee tttthhhhaaaatttt iiiinnnntttteeeerrrrsssseeeeccccttttssss tttthhhheeee
ttttrrrraaaannnnssssffffeeeerrrr ccccuuuurrrrvvvveeee.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
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9. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr QQQQQQQQ-ppppppppooooooooiiiiiiiinnnnnnnntttttttt
Step 1
Plot the line by plotting two points:
•VGS = VG, ID = 0 A
•VGS = 0 V, ID = VG / RS
Step 2
Plot the transfer curve by plotting
I , V and the calculated values
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IDSS, VP of ID
Step 3
The Q-point is located where the
line intersects the transfer curve
Electronic Devices and Circuit Theory, 10/e
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10. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCaaaaaaaallllllllccccccccuuuuuuuullllllllaaaaaaaattttttttiiiiiiiioooooooonnnnnnnnssssssss
UUUUssssiiiinnnngggg tttthhhheeee vvvvaaaalllluuuueeee ooooffff IIIID aaaatttt tttthhhheeee QQQQ-ppppooooiiiinnnntttt,,,, ssssoooollllvvvveeee ffffoooorrrr tttthhhheeee ooootttthhhheeeerrrr vvvvaaaarrrriiiiaaaabbbblllleeeessss iiiinnnn tttthhhheeee vvvvoooollllttttaaaaggggeeee-ddddiiiivvvviiiiddddeeeerrrr
bbbbiiiiaaaassss cccciiiirrrrccccuuuuiiiitttt::::
V = V − I (R +
R )
DS DD D D S
V = V −
I R
D DD D D
V =
I R
Copyright ©2009 by Pearson Education, Inc.
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
S D S V
DD
R1 R2 R R
1 2
I I
+
= =
10

11. D-Type TTTTTTTyyyyyyypppppppeeeeeee MMMMMMMMOOOOOOOOSSSSSSSSFFFFFFFFEEEEEEEETTTTTTTT BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCiiiiiiiirrrrrrrrccccccccuuuuuuuuiiiiiiiittttttttssssssss
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wwwwiiiitttthhhh ppppoooossssiiiittttiiiivvvveeee vvvvaaaalllluuuueeeessss ooooffff VVVVGGGGSSSS
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
aaaannnndddd wwwwiiiitttthhhh IIIID vvvvaaaalllluuuueeeessss tttthhhhaaaatttt eeeexxxxcccceeeeeeeedddd
IDDDDSSSSSSSS.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
11

12. SSSSSSSSeeeeeeeellllllllffffffff-BBBBBBBBiiiiiiiiaaaaaaaassssssss
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•VGGGGSSSS ==== VVVVG,,,, IIIID ==== 0000 A
•ID ==== VVVVG////RRRRS,,,, VVVVGGGGSSSS ==== 0000 V
SSSSSSSStttttttteeeeeeeepppppppp 2
PPPPllllooootttt tttthhhheeee ttttrrrraaaannnnssssffffeeeerrrr ccccuuuurrrrvvvveeee uuuussssiiiinnnngggg IIIIDDDDSSSSSSSS,,,, VVVVP aaaannnndddd
ccccaaaallllccccuuuullllaaaatttteeeedddd vvvvaaaalllluuuueeeessss ooooffff IIIID
Copyright ©2009 by Pearson Education, Inc.
TTTThhhheeee QQQQ-ppppooooiiiinnnntttt iiiissss llllooooccccaaaatttteeeedddd wwwwhhhheeeerrrreeee tttthhhheeee lllliiiinnnneeee
iiiinnnntttteeeerrrrsssseeeeccccttttssss tttthhhheeee ttttrrrraaaannnnssssffffeeeerrrr ccccuuuurrrrvvvveeee. Use the ID at
the Q-point to solve for the other variables
in the voltage-divider bias circuit.
These are the same steps used to analyze JFET self-bias circuits.
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SSSSSSSStttttttteeeeeeeepppppppp 3
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
12

13. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr BBBBBBBBiiiiiiiiaaaaaaaassssssss
SSSSSSSStttttttteeeeeeeepppppppp 1
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•VGGGGSSSS ==== VVVVG,,,, IIIID ==== 0000 A
•ID ==== VVVVG////RRRRS,,,, VVVVGGGGSSSS ==== 0000 V
SSSSSSSStttttttteeeeeeeepppppppp 2
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ccccaaaallllccccuuuullllaaaatttteeeedddd vvvvaaaalllluuuueeeessss ooooffff IIIID.
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
SSSSSSSStttttttteeeeeeeepppppppp 3
TTTThhhheeee QQQQ-ppppooooiiiinnnntttt iiiissss llllooooccccaaaatttteeeedddd wwwwhhhheeeerrrreeee tttthhhheeee lllliiiinnnneeee
iiiinnnntttteeeerrrrsssseeeeccccttttssss tttthhhheeee ttttrrrraaaannnnssssffffeeeerrrr ccccuuuurrrrvvvveeee iiiissss. UUUUsssseeee tttthhhheeee IIIID aaaatttt
tttthhhheeee QQQQ-ppppooooiiiinnnntttt ttttoooo ssssoooollllvvvveeee ffffoooorrrr tttthhhheeee ooootttthhhheeeerrrr vvvvaaaarrrriiiiaaaabbbblllleeeessss
iiiinnnn tttthhhheeee vvvvoooollllttttaaaaggggeeee-ddddiiiivvvviiiiddddeeeerrrr bbbbiiiiaaaassss cccciiiirrrrccccuuuuiiiitttt.
These are the same steps used to analyze
JFET voltage-divider bias circuits.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
13

14. E-Type TTTTTTTyyyyyyypppppppeeeeeee MMMMMMMMOOOOOOOOSSSSSSSSFFFFFFFFEEEEEEEETTTTTTTT BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCiiiiiiiirrrrrrrrccccccccuuuuuuuuiiiiiiiittttttttssssssss
TTTThhhheeee ttttrrrraaaannnnssssffffeeeerrrr cccchhhhaaaarrrraaaacccctttteeeerrrriiiissssttttiiiicccc ffffoooorrrr
tttthhhheeee eeee-ttttyyyyppppeeee MMMMOOOOSSSSFFFFEEEETTTT iiiissss vvvveeeerrrryyyy
ddddiiiiffffffffeeeerrrreeeennnntttt ffffrrrroooommmm tttthhhhaaaatttt ooooffff aaaa ssssiiiimmmmpppplllleeee
JJJJFFFFEEEETTTT oooorrrr tttthhhheeee dddd-ttttyyyyppppeeee MMMMOOOOSSSSFFFFEEEETTTT.
Copyright ©2009 by Pearson Education, Inc.
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
14

15. FFFFFFFFeeeeeeeeeeeeeeeeddddddddbbbbbbbbaaaaaaaacccccccckkkkkkkk BBBBBBBBiiiiiiiiaaaaaaaassssssss CCCCCCCCiiiiiiiirrrrrrrrccccccccuuuuuuuuiiiiiiiitttttttt
IG ==== 0000 AAAA
VRRRRGGGG ==== 0000 V
VDDDDSSSS ==== VVVVGGGGSSSS
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
VGGGGSSSS ==== VVVVDDDDDDDD – IDRD
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
15

16. FFFFFFFFeeeeeeeeeeeeeeeeddddddddbbbbbbbbaaaaaaaacccccccckkkkkkkk BBBBBBBBiiiiiiiiaaaaaaaassssssss QQQQQQQQ-PPPPPPPPooooooooiiiiiiiinnnnnnnntttttttt
Step 1
Plot the line using
•VGS = VDD, ID = 0 A
•ID = VDD / RD , VGS = 0 V
Step 2
Using values from the specification
sheet, plot the transfer curve with
•VGSTh , ID = 0 A
•V , I
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VGS(on), ID(on)
Step 3
The Q-point is located where the line
and the transfer curve intersect
Step 4
Using the value of ID at the Q-point,
solve for the other variables in the
bias circuit
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
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17. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr BBBBBBBBiiiiiiiiaaaaaaaassssssssiiiiiiiinnnnnnnngggggggg
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Q-ppppooooiiiinnnntttt. UUUUsssseeee tttthhhheeeesssseeee eeeeqqqquuuuaaaattttiiiioooonnnnssss::::
R V
2 DD
G R R
1 2
V
+
=
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
V GS = V G −
I D R
S
DS DD D S D
V = V − I (R +
R )
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
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18. VVVVVVVVoooooooollllllllttttttttaaaaaaaaggggggggeeeeeeee-DDDDDDDDiiiiiiiivvvvvvvviiiiiiiiddddddddeeeeeeeerrrrrrrr BBBBBBBBiiiiiiiiaaaaaaaassssssss QQQQQQQQ-PPPPPPPPooooooooiiiiiiiinnnnnnnntttttttt
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•VGGGGSSSS ==== VVVVG ==== ((((RRRR2VDDDDDDDD)))) //// ((((RRRR1 ++++ RRRR2)))),,,, IIIID ==== 0000 AAAA
•ID ==== VVVVG////RRRRS ,,,, VVVVGGGGSSSS ==== 0000 V
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•VGGGGSSSSTTTThhhh,,,, IIIID ==== 0000 A
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
•VGGGGSSSS((((oooonnnn)))) ,,,, IIIIDDDD((((oooonnnn))))
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
SSSSSSSStttttttteeeeeeeepppppppp 3
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vvvvaaaalllluuuueeeessss.
18

19. p-CCCCCCCChhhhhhhhaaaaaaaannnnnnnnnnnnnnnneeeeeeeellllllll FFFFFFFFEEEEEEEETTTTTTTTssssssss
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rrrreeeevvvveeeerrrrsssseeeedddd.
TTTTTTTThhhhhhhheeeeeeee ggggggggrrrrrrrraaaaaaaapppppppphhhhhhhhssssssss aaaaaaaarrrrrrrreeeeeeee mmmmmmmmiiiiiiiirrrrrrrrrrrrrrrroooooooorrrrrrrr iiiiiiiimmmmmmmmaaaaaaaaggggggggeeeeeeeessssssss ooooooooffffffff tttttttthhhhhhhheeeeeeee n-cccccccchhhhhhhhaaaaaaaannnnnnnnnnnnnnnneeeeeeeellllllll ggggggggrrrrrrrraaaaaaaapppppppphhhhhhhhssssssss.
Copyright ©2009 by Pearson Education, Inc.
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
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20. AAAAAAAApppppppppppppppplllllllliiiiiiiiccccccccaaaaaaaattttttttiiiiiiiioooooooonnnnnnnnssssssss
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TTTTiiiimmmmeeeerrrr nnnneeeettttwwwwoooorrrrkkkk
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MMMMOOOOSSSSFFFFEEEETTTT rrrreeeellllaaaayyyy ddddrrrriiiivvvveeeerrrr
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Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
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