ELECTRONIC DEVICES AND CIRCUIT THEORY 10th

Semiconductor Diodes
Chapter 1
Electronic Devices and Circuit Theory

Ch.1 Summary
Diodes
The diode is a 2-terminal device.
A diode ideally conducts
in only one direction.

Ch.1 Summary
Diode Characteristics
Conduction Region Non-Conduction Region
The voltage across the diode is 0 V
The current is infinite
The forward resistance is defined as
RF = VF / IF
The diode acts like a short
All of the voltage is across the diode
The current is 0 A
The reverse resistance is defined as
RR = VR / IR
The diode acts like open

Ch.1 Summary
Semiconductor Materials
Materials commonly used in the development of
semiconductor devices:
Silicon (Si)
Germanium (Ge)
Gallium Arsenide (GaAs)

Ch.1 Summary
Doping
The electrical characteristics of silicon and germanium are
improved by adding materials in a process called doping.
There are just two types of doped semiconductor materials:
n-type p-type
n-type materials contain
an excess of conduction
band electrons.
p-type materials contain an
excess of valence band holes.

Ch.1 Summary
p-n Junctions
The result is a p-n junction
One end of a silicon or germanium crystal can be
doped as a p-type material and the other end as an
n-type material.

Ch.1 Summary
p-n Junctions
The electrons in the n-type
material migrate across the
junction to the p-type material
(electron flow).
The result is the formation of a
depletion region around the
junction.
Electron migration results in a
negative charge on the p-type
side of the junction and a
positive charge on the n-type
side of the junction.
At the p-n junction, the excess conduction-band electrons
on the n-type side are attracted to the valence-band holes
on the p-type side.

Ch.1 Summary
Diode Operating Conditions
A diode has three operating conditions:
No bias
Reverse bias
Forward bias

Ch.1 Summary
No external voltage is applied: VD = 0 V
There is no diode current: ID = 0 A
Only a modest depletion region exists
No Bias

Ch.1 Summary
External voltage is applied
across the p-n junction in
the opposite polarity of the
p- and n-type materials.
Reverse Bias

Ch.1 Summary
Reverse Bias
The holes in the p-type material are attracted toward the negative
terminal of the voltage source.
The reverse voltage
causes the depletion
region to widen.
The electrons in the n-type
material are attracted
toward the positive terminal
of the voltage source.

Ch.1 Summary
Forward Bias
External voltage is
applied across the p-n
junction in the same
polarity as the p- and n-
type materials.

Ch.1 Summary
Forward Bias
The electrons and holes have sufficient energy to cross the p-n junction.
The forward voltage
causes the depletion
region to narrow.
The electrons and holes
are pushed toward the
p-n junction.

Ch.1 Summary
Actual Diode Characteristics
Note the regions for no
bias, reverse bias, and
forward bias
conditions.
Carefully note the scale
for each of these
conditions.

Ch.1 Summary
Majority and Minority Carriers
Two currents through a diode:
The minority carriers in p-type materials are electrons.
Majority Carriers
The majority carriers in n-type materials are electrons.
The majority carriers in p-type materials are holes.
Minority Carriers
The minority carriers in n-type materials are holes.

Ch.1 Summary
Zener Region
At some point the reverse bias voltage
is so large the diode breaks down and
the reverse current increases
dramatically.
The voltage that causes a diode to
enter the zener region of operation is
called the zener voltage (VZ).
The Zener region is in the diode’s reverse-bias region.
The maximum reverse voltage that
won’t take a diode into the zener
region is called the peak inverse
voltage or peak reverse voltage.

Ch.1 Summary
Forward Bias Voltage
The point at which the diode changes from no-bias condition
to forward-bias condition occurs when the electrons and
holes are given sufficient energy to cross the p-n junction.
This energy comes from the external voltage applied across
the diode.
The forward bias voltage required for a:
gallium arsenide diode  1.2 V
silicon diode  0.7 V
germanium diode  0.3 V

Ch.1 Summary
Temperature Effects
It reduces the required forward bias voltage for forward-
bias conduction.
It increases the amount of reverse current in the reverse-
bias condition.
It increases maximum reverse bias avalanche voltage.
As temperature increases it adds energy to the diode.
Germanium diodes are more sensitive to temperature variations
than silicon or gallium arsenide diodes.

Ch.1 Summary
Resistance Levels
DC (static) resistance
AC (dynamic) resistance
Average AC resistance
Semiconductors react differently to DC and AC currents.
There are three types of resistance:

Ch.1 Summary
DC (Static) Resistance
For a specific applied DC
voltage (VD) the diode has
a specific current (ID) and
a specific resistance (RD).
D
D
D
I
V
R 

Ch.1 Summary
AC (Dynamic) Resistance
The resistance depends on the amount of current (ID) in the diode.
The voltage across the diode is fairly constant (26 mV for 25C).
rB ranges from a typical 0.1  for high power devices to 2  for low
power, general purpose diodes. In some cases rB can be ignored.
B
D
d r
I
mV
26
r 





rd
In the forward bias region:
In the reverse bias region:
The resistance is effectively infinite. The diode acts like an open.

Ch.1 Summary
Average AC Resistance
AC resistance can be
calculated using the
current and voltage values
for two points on the diode
characteristic curve.
pt.
to
pt.
ΔI
ΔV
r
d
d
av 

Ch.1 Summary
Diode Equivalent Circuit

Ch.1 Summary
Diode Capacitance
When reverse biased, the depletion layer is very large. The diode’s
strong positive and negative polarities create capacitance (CT). The
amount of capacitance depends on the reverse voltage applied.
When forward
biased, storage
capacitance or
diffusion
capacitance (CD)
exists as the diode
voltage increases.

Ch.1 Summary
Reverse Recovery Time (trr)
Reverse recovery time is the time required for a diode to
stop conducting when switched from forward bias to
reverse bias.

Ch.1 Summary
Diode Symbol and Packaging
The anode is abbreviated A
The cathode is abbreviated K

Ch.1 Summary
Curve Tracer
A curve tracer displays
the characteristic curve of
a diode in the test circuit.
This curve can be
compared to the
specifications of the
diode from a data sheet.

Ch.1 Summary
Other Types of Diodes
Zener diodes
Light-emitting diodes
Diode arrays
There are several types of diodes besides the standard
p-n junction diode. Three of the more common are:

Ch.1 Summary
Zener Diode
A Zener diode is one that
is designed to safely
operate in its zener
region; i.e., biased at the
Zener voltage (VZ).
Common zener diode voltage ratings
are between 1.8 V and 200 V

Ch.1 Summary
Light-Emitting Diode (LED)
An LED emits light when it is forward biased,
which can be in the infrared or visible spectrum.
The forward bias voltage is usually
in the range of 2 V to 3 V.

Diode Applications
Chapter 2
Boylestad

Ch.2 Summary
Load-Line Analysis
The load line plots all
possible combinations of
diode current (ID) and
voltage (VD) for a given
circuit. The maximum ID
equals E/R, and the
maximum VD equals E.
The point where the load line and the characteristic curve intersect is the
Q-point, which identifies ID and VD for a particular diode in a given circuit.

Ch.2 Summary
Series Diode Configurations
Constants
Silicon Diode: VD = 0.7 V
Germanium Diode: VD = 0.3 V
Analysis (for silicon)
VD = 0.7 V (or VD = E if E < 0.7 V)
VR = E – VD
ID = IR = IT = VR / R
Forward Bias

Ch.2 Summary
Series Diode Configurations
Diodes ideally behave as
open circuits
Reverse Bias
Analysis
VD = E
VR = 0 V
ID = 0 A

Ch.2 Summary
Parallel Diode Configurations
mA
14
2
mA
28
D2
I
D1
I
mA
28
kΩ
.33
V
.7
V
10
R
D
V
E
R
I
V
9.3
R
V
V
0.7
o
V
D2
V
D1
V
V
0.7
D
V














Ch.2 Summary
Half-Wave Rectification
The diode
conducts only
when it is
forward
biased,
therefore only
half of the AC
cycle passes
through the
diode to the
output.
The DC output voltage is 0.318Vm, where Vm = the peak AC voltage.

Ch.2 Summary
PIV (PRV)
It is important that the reverse breakdown voltage rating of the
diode be high enough to withstand the peak, reverse-biasing AC
voltage.
PIV (or PRV) > Vm
Where PIV = Peak inverse voltage
PRV = Peak reverse voltage
Vm = Peak AC voltage
Because the diode is only forward biased for one-half of
the AC cycle, it is also reverse biased for one-half cycle.

Ch.2 Summary
Full-Wave Rectification
Half-wave: Vdc = 0.318Vm
Full-wave: Vdc = 0.636Vm
Full-wave rectification produces a
greater DC output:
The rectification process can be
improved by using a full-wave
rectifier circuit.

Ch.2 Summary
A full-wave rectifier with four
diodes that are connected in a
bridge configuration
VDC = 0.636Vm
Bridge Rectifier

Ch.2 Summary
Requires two diodes and a
center-tapped transformer
VDC = 0.636Vm
Center-Tapped
Transformer Rectifier

Ch.2 Summary
Summary of Rectifier Circuits
Vm = the peak AC voltage
Rectifier Ideal VDC Realistic VDC
Half Wave Rectifier VDC= 0.318Vm VDC = 0.318Vm – 0.7
Bridge Rectifier VDC = 0.636Vm VDC = 0.636Vm – 2(0.7 V)
Center-Tapped Transformer
Rectifier
VDC = 0.636Vm VDC = 0.636Vm – 0.7 V
In the center tapped transformer rectifier circuit, the peak AC
voltage is the transformer secondary voltage to the tap.

Ch.2 Summary
Zener Diodes
The Zener is a diode that is
operated in reverse bias at
the Zener Voltage (Vz).
When Vi  VZ
• The Zener is on
• Voltage across the Zener is VZ
• Zener current: IZ = IR – IRL
• The Zener Power: PZ = VZIZ
When Vi < VZ
• The Zener is off
• The Zener acts as an open circuit

Ch.2 Summary
Zener Resistor Values
m
in
L
Z
m
ax
L
I
V
R 
min
max
L
Z
L
L
L
R
V
R
V
I 

Z
i
Z
L
V
V
RV
R


min
If R is too large, the Zener diode cannot conduct
because IZ < IZK. The minimum current is given
by:
The maximum value of
resistance is:
If R is too small, IZ > IZM . The maximum
allowable current for the circuit is given by:
The minimum value of resistance is:
ZK
R
min
L I
I
I 


Ch.2 Summary
Voltage-Multiplier Circuits
Voltage Doubler
Voltage Tripler
Voltage Quadrupler
Voltage multiplier circuits use a combination of diodes
and capacitors to step up the output voltage of rectifier
circuits. Three common voltage multipliers are the:

Ch.2 Summary
Voltage Doubler
This half-wave voltage doubler’s output can be calculated
using:
Vout = VC2 = 2Vm
where Vm = peak secondary voltage of the transformer

Ch.2 Summary
Voltage Doubler
Vout = VC2 = 2Vm
Positive Half-Cycle D1 conducts
D2 is switched off
Capacitor C1 charges to Vm
Negative Half-Cycle D1 is switched off
D2 conducts
Capacitor C2 charges to Vm

Ch.2 Summary
Voltage Tripler and Quadrupler

Ch.2 Summary
Practical Applications
Rectifier Circuits
Conversions of AC to DC for DC operated circuits
Battery Charging Circuits
Simple Diode Circuits
Protective Circuits against
Overcurrent
Polarity Reversal
Currents caused by an inductive kick in a relay circuit
Zener Circuits
Overvoltage Protection
Setting Reference Voltages

Bipolar Junction Transistors
Chapter 3
Boylestad

Ch.3 Summary
Transistor Construction
There are two types of
transistors:
pnp and npn
The terminals are labeled:
E - Emitter
B - Base
C - Collector
pnp
npn

Ch.3 Summary
Transistor Operation
With the external sources, VEE and VCC, connected as
shown:
The emitter-base
junction is forward
biased
The base-collector
junction is reverse
biased

Ch.3 Summary
Currents in a Transistor
The collector current is comprised of
two currents:
B
I
C
I
E
I 

(minority)
CO
I
majority
C
I
C
I 

)
(
Emitter current is the sum of the
collector and base currents:

Ch.3 Summary
Common-Base Configuration
The base is common to both input (emitter–base) junction
and output (collector–base) junction of the transistor.

Ch.3 Summary
Common-Base Amplifier
Input Characteristics
This curve shows the
relationship between
of input current (IE) to
input voltage (VBE) for
three output voltage
(VCB) levels.

Ch.3 Summary
Common-Base Amplifier
This graph
demonstrates
the output
current (IC) to
an output
voltage (VCB)
for various
levels of input
current (IE).
Output Characteristics

Ch.3 Summary
Operating Regions
Active
Operating range of the amplifier.
Cutoff
The amplifier is basically off. There is
voltage, but little current.
Saturation
The amplifier is fully on. There is current,
but little voltage.

Ch.3 Summary
Approximations
E
C I
I 
Silicon)
(for
V
.
VBE 7
0

Emitter and collector currents:
Base-emitter voltage:

Ch.3 Summary
Alpha ()
Ideally:  = 1
In reality:  falls somewhere between
0.9 and 0.998
Alpha () is the ratio of IC to IE :
E
I
C
I
dc
α 
Alpha () in the AC mode:
E
I
Δ
C
I
Δ
ac
α 

Ch.3 Summary
Transistor Amplifier
Voltage Gain:
V
50
)
)(
(
mA
10
mA
10
20Ω
mV
200










kΩ
5
mA
10
R
L
I
L
V
i
I
L
I
E
I
C
I
i
R
i
V
i
I
E
I
Currents and
Voltages:
250
200
50



mV
V
V
V
v
A
i
L

Ch.3 Summary
Common-Emitter
Configuration
The emitter is common to
both input (base-emitter)
and output (collector-
emitter) circuits.
The input is applied to the
base and the output is
taken from the collector.

Ch.3 Summary
Common-Emitter Characteristics
Collector Characteristics Base Characteristics

Ch.3 Summary
Common-Emitter Amplifier Currents
IE = IC + IB IC =  IE
Actual Currents
When IB = 0 A the transistor is in
cutoff, but there is some minority
current flowing called ICEO.
μA
0
I
CBO
CEO B
α
I
I 


1
where ICBO = minority
collector current
ICBO is usually so small that it can be ignored, except in high
power transistors and in high temperature environments.
Ideal Currents
IC =  IE + ICBO

Ch.3 Summary
Beta ()
In DC mode:
In AC mode:
ac is sometimes referred to as hfe, a term used in transistor
modeling calculations
B
C
dc
I
I
β 
constant
V
B
C
ac CE
I
I





 represents the amplification factor of a transistor.

Ch.3 Summary
Beta ()
Determining  from a Graph
108
A
mA
.
β V
.
V
DC CE


  5
7
25
7
2
100
10
1
20
30
2
2
2
3
5
7








 V
.
V
AC
CE
A
mA
A)
A
(
mA)
.
mA
.
(
β

Ch.3 Summary
Beta ()
Relationship between amplification factors  and  :
1


β
β
α
1


α
α
β
Relationship Between Currents:
B
C βI
I  B
E )I
(β
I 1



Ch.3 Summary
Common-Collector Configuration
The input is on the
base and the
output is on the
emitter.

Ch.3 Summary
The characteristics
are similar to those
of the common-
emitter amplifier,
except the vertical
axis is IE.

Ch.3 Summary
Operating Limits
The transistor operates in the active region between saturation and cutoff.
VCE is maximum and IC is
minimum in the cutoff
region.
IC is maximum and VCE is
minimum in the saturation
region.
CEO
C I
I 
(max)
CEO
sat
CE
CE V
V
V 
 )
(
(max)

Ch.3 Summary
Power Dissipation
Common-collector:
C
CB
Cm
ax I
V
P 
C
CE
Cm
ax I
V
P 
E
CE
Cm
ax I
V
P 
Common-base:
Common-emitter:

Ch.3 Summary
Transistor Testing
Curve Tracer Provides a graph of the characteristic curves.
DMM Some DMMs measure DC or hFE.
Ohmmeter:

Ch.3 Summary
Transistor Terminal Identification

DC Biasing - BJTs
Chapter 4
Boylestad

Ch.4 Summary
Biasing
Biasing: Applying DC voltages to a transistor in order
to turn it on so that it can amplify AC signals.

Ch.4 Summary
Operating Point
The DC input
establishes an
operating or
quiescent point
called the Q-point.

Ch.4 Summary
The Three Operating Regions
Active or Linear Region Operation
• Base–Emitter junction is forward biased
• Base–Collector junction is reverse biased
Cutoff Region Operation
• Base–Emitter junction is reverse biased
Saturation Region Operation
• Base–Emitter junction is forward biased
• Base–Collector junction is forward biased

Ch.4 Summary
DC Biasing Circuits
Fixed-bias circuit
Emitter-stabilized bias circuit
Collector-emitter loop
Voltage divider bias circuit
DC bias with voltage feedback

Ch.4 Summary
The Base-Emitter Loop
From Kirchhoff’s voltage
law:
Solving for base current:
+VCC – IBRB – VBE = 0
B
BE
CC
B
R
V
V
I



Ch.4 Summary
Collector-Emitter Loop
Collector current:
From Kirchhoff’s voltage law:
B
C I
I 

C
C
CC
CE R
I
V
V 


Ch.4 Summary
Saturation
When the transistor is operating in saturation, current
through the transistor is at its maximum possible value.
C
R
CC
V
Csat
I 
V
CE
V 0


Ch.4 Summary
Load Line Analysis
ICsat
IC = VCC / RC
VCE = 0 V
VCEcutoff
VCE = VCC
IC = 0 mA
The Q-point is the operating point where the value of RB sets the
value of IB that controls the values of VCE and IC .
The load line end points are:

Ch.4 Summary
The Effect of VCC on the Q-Point

Ch.4 Summary
The Effect of RC on the Q-Point

Ch.4 Summary
The Effect of IB on the Q-Point

Ch.4 Summary
Emitter-Stabilized Bias Circuit
Adding a resistor
(RE) to the emitter
circuit stabilizes
the bias circuit.

Ch.4 Summary
Base-Emitter Loop
0
1 


 E
B
B
B
CC R
)I
(β
R
I
V
0
R
I
V
R
I
V E
E
BE
E
E
CC 




E
B
BE
CC
B
)R
(β
R
V
V
I
1




Since IE = ( + 1)IB:
Solving for IB:

Ch.4 Summary
0
V
R
I
V
R
I CC
C
C
CE
E
E 



Since IE  IC:
)
R
(R
– I
V
V E
C
C
CC
CE 

Also:
E
BE
B
R
CC
B
C
C
CC
E
CE
C
E
E
E
V
V
R
– I
V
V
R
I
V
V
V
V
R
I
V









Ch.4 Summary
Improved Biased Stability
Stability refers to a condition in which the currents and
voltages remain fairly constant over a wide range of
temperatures and transistor Beta () values.
Adding RE to the emitter improves
the stability of a transistor.

Ch.4 Summary
Saturation Level
VCEcutoff: ICsat:
The endpoints can be determined from the load line.
mA
0
I
V
V
C
CC
CE


E
R
C
R
CC
V
C
I
VCE


 V
0

Ch.4 Summary
Voltage Divider Bias
The currents and
voltages are nearly
independent of any
variations in .
This is a very stable bias circuit.

Ch.4 Summary
Approximate Analysis
Where IB << I1 and I1  I2 :
Where RE > 10R2:
2
1
CC
2
B
R
R
V
R
V


E
E
E
R
V
I 
BE
B
E V
V
V 

E
E
C
C
CC
CE R
I
R
I
V
V 


)
R
(R
I
V
V
I
I
E
C
C
CC
CE
C
E





Ch.4 Summary
Voltage Divider Bias Analysis
Transistor Saturation Level
E
C
CC
Cmax
Csat
R
R
V
I
I



Cutoff: Saturation:
mA
0
I
V
V
C
CC
CE


V
0
VCE
E
R
C
R
CC
V
C
I



Load Line Analysis

Ch.4 Summary
DC Bias With Voltage Feedback
Another way to improve
the stability of a bias
circuit is to add a
feedback path from
collector to base.
In this bias circuit the
Q-point is only slightly
dependent on the
transistor beta, .

Ch.4 Summary
Base-Emitter Loop
)
R
β(R
R
V
V
I
E
C
B
BE
CC
B




0

 E
E
BE
B
B
C
C
CC R
–I
–V
R
–I
R
I
–
V
Where IB << IC: C
B
C
C I
I
I
I' 


Knowing IC = IB and IE  IC, the
loop equation becomes:
0



 E
B
BE
B
B
C
B
CC R
βI
V
R
I
R
– β–
V
Solving for IB:

Applying Kirchoff’s voltage law:
IE + VCE + I’CRC – VCC = 0
Since IC  IC and IC = IB:
IC(RC + RE) + VCE – VCC =0
Solving for VCE:
VCE = VCC – IC(RC + RE)
Ch.4 Summary

Ch.4 Summary
Base-Emitter Bias Analysis
Transistor Saturation Level
E
C
CC
Cmax
Csat
R
R
V
I
I



Cutoff Saturation
mA
0
I
V
V
C
CC
CE


V
0
VCE
E
R
C
R
CC
V
C
I



Load Line Analysis

Ch.4 Summary
Transistor Switching Networks
Transistors with only the DC source applied can be
used as electronic switches.

Ch.4 Summary
Switching Circuit Calculations
C
CC
Csat
R
V
I 
dc
Csat
B
β
I
I 
Csat
CEsat
sat
I
V
R 
CEO
CC
cutoff
I
V
R 
Saturation current:
To ensure saturation:
Emitter-collector
resistance at
saturation and cutoff:

Ch.4 Summary
Switching Time
Transistor switching times:
d
r
on t
t
t 

f
s
off t
t
t 


Ch.4 Summary
PNP Transistors
The analysis for pnp transistor biasing circuits is
the same as that for npn transistor circuits. The
only difference is that the currents are flowing in
the opposite direction.

BJT AC Analysis
Chapter 5
Boylestad

Ch.5 Summary
BJT Transistor Modeling
A model is an equivalent circuit that represents
the AC characteristics of the transistor.
A model uses circuit elements that approximate
the behavior of the transistor.
There are two models commonly used in small
signal AC analysis of a transistor:
re model
Hybrid equivalent model

Ch.5 Summary
The re Transistor Model
BJTs are basically current-controlled devices; therefore
the re model uses a diode and a current source to
duplicate the behavior of the transistor.
One disadvantage to this model is its sensitivity to the
DC level. This model is designed for specific circuit
conditions.

Ch.5 Summary
e
e
I
mV
26
r  e
i r
Z 



o
Z
e
L
e
L
V
r
R
r
R
A 


1





i
A
Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
Common-Emitter Configuration
  b
b
e I
I
I 



 1
e
e
I
mV
26
r 
The diode re model
can be replaced by
the resistor re.

Ch.5 Summary
Common-Emitter Configuration
e
i r
Z 




 o
o r
Z
e
L
V
r
R
A 




 o
r
i
A
Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
e
i r
Z )
1
( 


E
e
o R
r
Z ||

e
E
E
V
r
R
R
A


1

 β
Ai
Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
The Hybrid Equivalent Model
Hybrid parameters are developed and used for modeling the
transistor. These parameters can be found on a transistor’s
specification sheet:
hi = input resistance
hr = reverse transfer voltage ratio (Vi/Vo)  0
hf = forward transfer current ratio (Io/Ii)
ho = output conductance

Ch.5 Summary
Simplified General h-Parameter Model
hi = input resistance
hf = forward transfer current ratio (Io/Ii)

Ch.5 Summary
re vs. h-Parameter Model
ac
fe
e
ie
β
h
βr
h


Common-Emitter
Common-Base
1





α
h
r
h
fb
e
ib

Ch.5 Summary
The Hybrid  Model
The hybrid pi model is most useful for analysis
of high-frequency transistor applications.
At lower frequencies the hybrid pi model closely
approximate the re parameters, and can be
replaced by them.

Ch.5 Summary
Common-Emitter Fixed-Bias
Configuration
The input is applied to the base
The output is taken from the
collector
High input impedance
Low output impedance
High voltage and current gain
Phase shift between input and
output is 180

Ch.5 Summary
Common-Emitter
Fixed-Bias
Configuration
AC equivalent
re,model

Ch.5 Summary
Common-Emitter
Fixed-Bias
Calculations
C
o R
r
e
C
v
e
o
C
i
o
v
r
R
A
r
)
||r
(R
V
V
A
10






e
B
C
o βr
, R
R
r
i
e
B
C
o
o
B
i
o
i
β
A
)
βr
)(R
R
(r
r
βR
I
I
A
10
10 






C
i
V
i
R
Z
A
A 

Current gain
from voltage gain:
Input
impedance:
Output
impedance:
Voltage gain:
Current gain:
e
E βr
R
e
i
e
B
i
βr
Z
||β|
R
Z
10



C
o
O
R
r
C
o
C
o
R
Z
||r
R
Z
10




Ch.5 Summary
Common-Emitter Voltage-Divider Bias
re model requires you to
determine , re, and ro.

Ch.5 Summary
Common-Emitter
Voltage-Divider Bias
Calculations
Input impedance
e
i
2
1
βr
||
R
Z
R
||
R
R




Output impedance
C
o 10R
r
C
o
o
C
o
R
Z
r
||
R
Z



Voltage gain
C
o 10R
r
e
C
i
o
v
e
o
C
i
o
v
r
R
V
V
A
r
r
||
R
V
V
A







Current gain
e
C
o
C
o
r
10
R
,
10R
r
i
o
i
10R
r
e
i
o
i
e
C
o
o
i
o
i
I
I
A
r
R
R
I
I
A
)
r
R
)(
R
(r
r
R
I
I
A























Current gain from Av
C
i
v
i
R
Z
A
A 


Ch.5 Summary
Common-Emitter Emitter-Bias
Configuration

Ch.5 Summary
Impedance Calculations
E
b
E
e
b
E
e
b
b
B
i
R
Z
)
R
(r
Z
1)R
(
r
Z
Z
||
R
Z











Input impedance:
Output impedance:
C
o R
Z 

Ch.5 Summary
Gain Calculations
Current gain from Av:
Voltage gain:
Current gain:
E
b
E
e
b
R
Z
E
C
i
o
v
)
R
(r
Z
E
e
C
i
o
v
b
C
i
o
v
R
R
V
V
A
R
r
R
V
V
A
Z
R
V
V
A
















b
B
B
i
o
i
Z
R
R
I
I
A




C
i
v
i
R
Z
A
A 


Ch.5 Summary
Emitter-Follower Configuration
This is also known as the common-collector configuration.
The input is applied to the base and the output is taken from the emitter.
There is no phase shift between input and output.

Ch.5 Summary
Impedance
Calculations
Input impedance:
Output impedance:
e
E r
R
e
o
e
E
o
r
Z
||r
R
Z



E
b
E
e
b
E
e
b
b
B
i
βR
Z
)
R
β(r
Z
)R
(β
βr
Z
||Z
R
Z







1

Ch.5 Summary
Gain Calculations
Current gain from voltage gain:
Voltage gain:
Current gain:
E
e
E
e
E R
r
, R
r
R
i
o
v
e
E
E
i
o
v
V
V
A
r
R
R
V
V
A








1
b
B
B
i
Z
R
βR
A



E
i
v
i
R
Z
A
A 


Ch.5 Summary
The input is applied to the emitter
The output is taken from the
collector
Low input impedance.
High output impedance
Current gain less than unity
Very high voltage gain
No phase shift between input
and output

Ch.5 Summary
Calculations
e
E
i r
||
R
Z 
C
o R
Z 
e
C
e
C
i
o
v
r
R
r
R
V
V
A 



1
I
I
A
i
o
i 





Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
Common-Emitter Collector Feedback
Configuration
• A variation of the common-emitter fixed-bias configuration
• Input is applied to the base
• Output is taken from the collector
• There is a 180 phase shift between the input and output

Ch.5 Summary
Calculations
F
C
e
i
R
R
β
r
Z


1
F
C
o R
||
R
Z 
e
C
i
o
v
r
R
V
V
A 


C
F
i
o
i
C
F
F
i
o
i
R
R
I
I
A
βR
R
βR
I
I
A





Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
Collector DC Feedback
Configuration
• The input is applied to the
base
• The output is taken from
the collector
• There is a 180 phase shift
between input and output
This is a variation of the common-
emitter, fixed-bias configuration

Ch.5 Summary
Calculations
F
C
e
i
R
R
β
r
Z


1
F
C
o ||R
R
Z 
e
C
i
o
v
r
R
V
V
A 


C
F
i
o
i
C
F
F
i
o
i
R
R
I
I
A
R
R
R
I
I
A







Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
Two-Port Systems Approach
o
o
Th R
Z
Z 

With Vi set to 0 V:
The voltage across
the open terminals is:
where AvNL is the no-
load voltage gain
i
vNL
Th V
A
E 

Ch.5 Summary
Effect of Load Impedance on Gain
L
i
v
i
R
Z
A
A 

This model can be applied
to any current- or voltage-
controlled amplifier.
Adding a load reduces the
gain of the amplifier:
vNL
o
L
L
i
o
v A
R
R
R
V
V
A




Ch.5 Summary
Effect of Source Impedance on Gain
The amplitude of the
applied signal that
reaches the input of
the amplifier is:
s
i
s
i
i
R
R
V
R
V


vNL
s
i
i
s
o
vs A
R
R
R
V
V
A



The internal resistance of the signal source reduces the overall
gain:

Ch.5 Summary
Combined Effects of RS and RL on
Voltage Gain
Effects of RL:
Effects of RL and RS:
L
i
v
i
o
L
vNL
L
i
o
v
R
R
A
A
R
R
A
R
V
V
A





L
i
s
vs
is
vNL
o
L
L
s
i
i
s
o
vs
R
R
R
A
A
A
R
R
R
R
R
R
V
V
A








Ch.5 Summary
Cascaded Systems
• The output of one amplifier is the input to the next
amplifier
• The overall voltage gain is determined by the product of
gains of the individual stages
• The DC bias circuits are isolated from each other by the
coupling capacitors
• The DC calculations are independent of the cascading
• The AC calculations for gain and impedance are
interdependent

Ch.5 Summary
R-C Coupled BJT Amplifiers
C
o R
Z 
Input impedance,
first stage:
Output impedance,
second stage:
Voltage gain:
e
i R
R
R
Z 
 ||
|| 2
1
2
1
2
2
1
1
||
||
||
v
v
v
e
C
v
e
e
C
v
A
A
A
r
R
A
r
R
R
R
R
A





Ch.5 Summary
Cascode Connection
This example is a CE–CB
combination. This arrangement
provides high input impedance
but a low voltage gain.
The low voltage gain of the
input stage reduces the Miller
input capacitance, making this
combination suitable for high-
frequency applications.

Ch.5 Summary
Darlington Connection
The Darlington circuit provides
very high current gain, equal to the
product of the individual current
gains:
D = 1 2
The practical significance is that
the circuit provides a very high
input impedance.

Ch.5 Summary
DC Bias of Darlington Circuits
B
D
B
D
E I
I
I 



 )
1
(
E
E
E R
I
V 
E
D
B
BE
CC
B
R
R
V
V
I




Base current:
Emitter current:
Emitter voltage:
Base voltage:
BE
E
B V
V
V 


Ch.5 Summary
Feedback Pair
This is a two-transistor circuit that operates like a Darlington
pair, but it is not a Darlington pair.
It has similar characteristics:
• High current gain
• Voltage gain near unity
• Low output impedance
• High input impedance
The difference is that a Darlington uses a pair of like
transistors, whereas the feedback-pair configuration uses
complementary transistors.

Ch.5 Summary
Current Mirror Circuits
Current mirror
circuits provide
constant current in
integrated circuits.

Ch.5 Summary
Current Source Circuits
Constant-current sources can be built using FETs, BJTs, and
combinations of these devices.
IE  IC
E
BE
Z
E
R
V
V
I
I




Ch.5 Summary
Current Source Circuits
VGS = 0V
ID = IDSS = 10 mA

Ch.5 Summary
Fixed-Bias
ie
B
i h
R
Z ||

oe
C
o h
R
Z /
1
||

 
ie
o
C
fe
i
o
v
h
e
h
R
h
V
V
A
/
1
||



fe
i
o
i h
I
I
A 

Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
Voltage-Divider Configuration
ie
fe
i
h
R
R
h
A





ie
i h
||
R
Z 

C
o R
Z 
 
ie
oe
C
fe
v
h
1/h
||
R
h
A 

Input impedance:
Output impedance:
Voltage gain:
Current gain:

Ch.5 Summary
Emitter-Follower Configuration
b
o
i
E
fe
b
Z
||
R
Z
R
h
Z


b
o
i
E
fe
b
Z
R
Z
R
h
Z
||


Input impedance:
Output impedance:
Voltage gain:
Current gain:
fe
ie
E
o
h
h
R
Z ||

fe
ie
E
E
i
o
v
h
h
R
R
V
V
A
/



E
i
v
i
b
B
B
fe
i
R
Z
A
A
Z
R
R
h
A





Ch.5 Summary
ib
E
i h
||
R
Z 
C
o R
Z 
ib
C
fb
i
o
v
h
R
h
V
V
A 


1
h
I
I
A fb
i
o
i 



Input impedance:
Output impedance:
Voltage gain:
Current gain:

Field-Effect Transistors
Chapter 6
Boylestad

Ch.6 Summary
FETs vs. BJTs
FETs are voltage controlled devices. BJTs are
current controlled devices.
FETs have higher input impedance. BJTs have
higher gain.
FETs are less sensitive to temperature variations
and are better suited for integrated circuits
FETs are generally more static sensitive than
BJTs.
Similarities: Amplifiers
Switching devices
Impedance matching circuits
Differences:

Ch.6 Summary
FET Types
JFET: Junction FET
MOSFET: Metal–Oxide–Semiconductor FET
D-MOSFET: Depletion MOSFET
E-MOSFET: Enhancement MOSFET

Ch.6 Summary
JFET Construction
The n-channel is the more widely used
of the two.
The Gate (G) is connected to the p-type material
There are two types of JFETs:
JFETs have three terminals:
n-channel
p-channel
The Drain (D) and Source (S)
are connected to the n-channel

Ch.6 Summary
JFET Operation: The Basic Idea
JFET operation can be compared to that of a water spigot.
The gate controls the width of the n-
channel and, therefore, the flow of
charges from source to drain.
The source is the accumulation of
electrons at the negative pole of the
drain-source voltage.
The drain is the electron deficiency
(or holes) at the positive pole of the
applied voltage.

Ch.6 Summary
JFET Operating Characteristics
• VGS = 0 V, VDS increasing to some positive value
• VGS < 0 V, VDS at some positive value
• Voltage-controlled resistor
There are three basic operating conditions for a JFET:

Ch.6 Summary
JFET Characteristics: VGS=0V
• Even though the n-channel resistance is
increasing, the current from source to
drain (ID) through the n-channel is
increasing because VDS is increasing.
Three things happen when VGS = 0 V and VDS increases
from 0 V to a more positive voltage:
• The size of the depletion region between
p- type gate and n-channel increases.
• Increasing the size of the depletion
region decreases the width of the n-
channel, which increases its resistance.

Ch.6 Summary
JFET Characteristics: Pinch Off
• This suggests that the current in
channel (ID) drops to 0 A, but it does
not: As VDS increases, so does ID.
However, once pinch off occurs,
further increases in VDS do not
cause ID to increase.
• If VGS = 0 V and VDS continually
increases to a more positive voltage, a
point is reached where the depletion
region gets so large that it pinches off
the channel.

Ch.6 Summary
JFET Characteristics: Saturation
At the pinch-off point:
Any further increase in VDS
does not produce any increase
in ID. VDS at pinch-off is
denoted as Vp
ID is at saturation or maximum,
and is referred to as IDSS.

Ch.6 Summary
As VGS becomes more
negative, the depletion
region increases.

Ch.6 Summary
• ID eventually drops to 0 A.
The value of VGS that causes
this to occur is designated
VGS(off).
Note that at high levels of VDS the JFET reaches a breakdown situation. ID
increases uncontrollably if VDS > VDSmax, and the JFET is likely destroyed.
As VGS becomes more negative:
• The JFET experiences
pinch-off at a lower voltage
(VP).
• ID decreases (ID < IDSS)
even when VDS increases

Ch.6 Summary
Voltage-Controlled Resistor
2
P
GS
o
d
V
V
1
r
r










The region to the left of the
pinch-off point is called the
ohmic region.
The JFET can be used as a
variable resistor, where VGS
controls the drain-source
resistance (rd).
As VGS becomes more negative, the resistance (rd)
increases.

Ch.6 Summary
P-Channel JFETs
The p-channel JFET
behaves the same as the
n-channel JFET. The only
differences are that the
voltage polarities and
current directions are
reversed.

Ch.6 Summary
P-Channel JFET Characteristics
Also note that at high levels of VDS the JFET reaches a breakdown
situation: ID increases uncontrollably if VDS > VDSmax.
• The depletion region increases,
and ID decreases (ID < IDSS)
As VGS becomes more positive:
• ID eventually drops to 0 A
(when VGS = VGSoff)
• The JFET experiences pinch-off
at a lower voltage (VP).

Ch.6 Summary
N-Channel JFET Symbol

Ch.6 Summary
JFET Transfer Characteristics
2
V
V
1
DSS
D
P
GS
I
I 









JFET input-to-output transfer characteristics are not
as straightforward as they are for a BJT.
• BJT:  indicates the relationship between IB (input) and IC
(output).
• JFET: The relationship of VGS (input) and ID (output) is a little
more complicated:

Ch.6 Summary
JFET Transfer Curve
This graph shows
the value of ID for
a given value of
VGS.

Ch.6 Summary
Plotting the JFET Transfer Curve
Using IDSS and Vp (VGS(off)) values found in a specification sheet, the
transfer curve can be plotted according to these three steps:
1. Solving for VGS = 0 V: ID = IDSS
2. Solving for VGS = VGS(off): ID = 0 A
3. Solving for VGS = 0 V to VGS(off): 0 A < ID < IDSS
2
V
V
1
DSS
D
P
GS
I
I 










Ch.6 Summary
JFET Specification Sheet
Electrical
Characteristics

Ch.6 Summary
JFET Specification Sheet
Maximum Ratings

Ch.6 Summary
Case and Terminal Identification

Ch.6 Summary
Testing JFETs
Curve Tracer
A curve tracer displays the ID versus VDS graph for
various levels of VGS.
Specialized FET Testers
These testers show IDSS for the JFET under test.

Ch.6 Summary
MOSFETs
There are two types of MOSFETs:
Depletion-Type
Enhancement-Type
MOSFETs have characteristics similar to those of
JFETs and additional characteristics that make then
very useful.

Ch.6 Summary
Depletion-Type MOSFET Construction
The Drain (D) and Source (S)
connect to the to n-type regions.
These n-typed regions are
connected via an n-channel. This
n-channel is connected to the
Gate (G) via a thin insulating
layer of silicon dioxide (SiO2).
The n-type material lies on a p-
type substrate that may have an
additional terminal connection
called the Substrate (SS).

Ch.6 Summary
Basic MOSFET Operation
A depletion-type MOSFET can operate in two modes:
Depletion mode
Enhancement mode

Ch.6 Summary
Depletion Mode Operation (D-MOSFET)
When VGS = 0 V, ID = IDSS
When VGS < 0 V, ID < IDSS
The characteristics are
similar to a JFET.
The formula used to plot the
transfer curve for a JFET applies to
a D-MOSFET as well:
2
V
V
1
DSS
D
P
GS
I
I 










Ch.6 Summary
Enhancement Mode Operation
(D-MOSFET)
VGS > 0 V, ID increases
above IDSS (ID > IDSS)
Note that VGS is now positive
The formula used to
plot the transfer curve
still applies:
2
V
V
1
DSS
D
P
GS
I
I 










Ch.6 Summary
p-Channel D-Type MOSFET

Ch.6 Summary
D-Type MOSFET Symbols

Ch.6 Summary
E-Type MOSFET Construction
The Gate (G) connects to the p-type
substrate via a thin insulating layer of
silicon dioxide (SiO2)
There is no channel
The n-type material lies on a p-type
substrate that may have an additional
terminal connection called the
Substrate (SS)
The Drain (D) and Source (S) connect to the to n-type regions.
These n-type regions are connected via an n-channel

Ch.6 Summary
E-Type MOSFET Operation
VGS is always positive
As VGS increases, ID
increases
As VGS is kept constant
and VDS is increased,
then ID saturates (IDSS)
and the saturation level
(VDSsat) is reached
The enhancement-type MOSFET (E-MOSFET) operates only
in the enhancement mode.

Ch.6 Summary
E-Type MOSFET Transfer Curve
where:
VT = the E-MOSFET
threshold voltage
2
)
( T
GS
D V
V
k
I 

k, a constant, can be
determined by using
values at a specific point
and the formula:
2
T
GS(ON)
D(ON)
)
V
(V
I
k


VDSsat can be calculated using:
T
GS
DSsat V
V
V 

To determine ID given VGS:

Ch.6 Summary
p-Channel E-Type MOSFETs
The p-channel enhancement-type MOSFET is similar
to its n-channel counterpart, except that the voltage
polarities and current directions are reversed.

Ch.6 Summary
Handling MOSFETs
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
• Apply voltage limiting devices between the gate and source,
such as back-to-back Zeners to limit any transient voltage.
Because of the very thin SiO2 layer between the external terminals
and the layers of the device, any small electrical discharge can
create an unwanted conduction.
Protection
MOSFETs are very sensitive to static electricity.

Ch.6 Summary
VMOS Devices
VMOS (vertical MOSFET) is a component structure that
provides greater
surface area.
Advantages
VMOS devices handle
higher currents by
providing more surface
area to dissipate the heat.
VMOS devices also have
faster switching times.

Ch.6 Summary
CMOS Devices
Advantages
• Useful in logic circuit designs
• Higher input impedance
• Faster switching speeds
• Lower operating power levels
CMOS (complementary MOSFET) uses a p-channel and
n-channel MOSFET; often on the same substrate as
shown here.

FET Biasing
Chapter 7
Boylestad

Ch.7 Summary
Common FET Biasing Circuits
JFET Biasing Circuits
Fixed-Bias
Self-Bias
D-Type MOSFET Biasing Circuits
Self-Bias
E-Type MOSFET Biasing Circuits
Feedback Configuration

2
1 









P
GS
DSS
D
V
V
I
I
Ch.7 Summary
Basic Current Relationships
For all FETs:
A
0
IG  S
D I
I 
For JFETS and D-Type MOSFETs:
For E-Type MOSFETs:
2
)
( T
GS
D V
V
k
I 


Ch.7 Summary
Fixed-Bias Configuration
GG
GS
GS
DS
C
S
D
D
DD
DS
V
V
V
V
V
V
V
R
I
V
V







V
0

Ch.7 Summary
Self-Bias Configuration

)
( D
S
D
DD
DS R
R
I
V
V 


Ch.7 Summary
Self-Bias Calculations
S
D
S R
I
V 
S
D
GS R
I
V 

2. Plot the transfer curve using IDSS and VP
(VP = |VGSoff| on spec sheets) and a few
points such as VGS = VP / 4 and VGS = VP / 2
etc.
The Q-point is located where the first
line intersects the transfer curve. Using
the value of ID at the Q-point (IDQ):
1. Select a value of ID < IDSS and use the component value of RS to calculate
VGS. Plot the point identified by ID and VGS and draw a line from the origin of
the axis to this point.
RD
DD
S
DS
D V
V
V
V
V 




Ch.7 Summary
IG = 0 A
ID responds to changes
in VGS.

Ch.7 Summary
Voltage-Divider Bias Calculations
The Q-point is established by plotting a line that intersects the transfer
curve.
2
1
2
R
R
V
R
V DD
G


VG is equal to the voltage across
divider resistor R2:
Using Kirchhoff’s Law:
S
D
G
GS R
I
V
V 


Ch.7 Summary
Voltage-Divider Q-Point
Plot the transfer curve by
plotting IDSS, VP and the
calculated values of ID
Plot the line that is defined
by these two points:
VGS = VG, ID = 0 A
VGS = 0 V, ID = VG / RS
The Q-point is located where the line intersects the transfer
curve

Ch.7 Summary
Voltage-Divider Bias Calculations
Using the value of ID at the Q-point, solve for the other
values in the voltage-divider bias circuit:
S
D
S
D
D
DD
D
S
D
D
DD
DS
R
I
V
R
I
V
V
R
R
I
V
V





 )
(

Ch.7 Summary
D-Type MOSFET Bias Circuits
Depletion-type MOSFET
bias circuits are similar
to those used to bias
JFETs. The only
difference is that D-type
MOSFETs can operate
with positive values of
VGS and with ID values
that exceed IDSS.

Ch.7 Summary
Self-Bias Q-Point (D-MOSFET)
Plot the line that is defined by these
two points:
VGS = VG, ID = 0 A
ID = VG /RS, VGS = 0 V
Plot the transfer curve using IDSS, VP
and calculated values of ID.
The Q-point is located where the line
intersects the transfer curve. Use the
value of ID at the Q-point to solve for
the other circuit values.
These are the same steps used to analyze JFET self-bias circuits.

Ch.7 Summary
Voltage-Divider Bias (D-MOSFET)
Plot the line that is defined by these two
points:
VGS = VG, ID = 0 A
ID = VG/RS, VGS = 0 V
Plot the transfer curve using IDSS, VP and
calculated values of ID.
The Q-point is located where the line
intersects the transfer curve. Use the
value of ID at the Q-point to solve for the
other variables in the circuit.
These are the same steps used to analyze JFET voltage-divider bias circuits.

Ch.7 Summary
E-Type MOSFET Bias Circuits
The transfer curve for
the E-MOSFET is
very different from
that of a simple JFET
or D-MOSFET.

Ch.7 Summary
Feedback Bias Circuit (E-MOSFET)
D
D
DD
GS
GS
DS
RG
G
R
I
V
V
V
V
V
I





V
0
A
0

Ch.7 Summary
Feedback Bias Q-Point (E-MOSFET)
Using these values from the
spec sheet, plot the transfer
curve:
VGSTh , ID = 0 A
VGS(on), ID(on)
Plot the line that is defined
by these two points:
VGS = VDD, ID = 0 A
ID = VDD / RD , VGS = 0 V
Using the value of ID at the Q-point,
solve for the other variables in the
circuit
The Q-point is located where
the line and the transfer curve
intersect

Ch.7 Summary
Voltage-Divider Biasing
Plot the line and the transfer
curve to find the Q-point using
these equations:
2
1
2
R
R
V
R
V DD
G


)
( D
S
D
DD
DS
S
D
G
GS
R
R
I
V
V
R
I
V
V






Ch.7 Summary
Voltage-Divider Bias Q-Point
(E-MOSFET)
Plot the line using
VGS = VG , ID = 0 A
ID = VG / RS , VGS = 0 V
Using these values from the spec sheet, plot the transfer curve:
VGSTh, ID = 0 A
VGS(on) , ID(on)
The point where the line and the transfer curve intersect is the Q-point.
Using the value of ID at the Q-point, solve for the other circuit values.

Ch.7 Summary
p-Channel FETs
For p-channel FETs the same calculations and graphs
are used, except that the voltage polarities and current
directions are reversed.
The graphs are mirror images of the n-channel graphs.

Ch.7 Summary
Applications
Voltage-controlled resistor
JFET voltmeter
Timer network
Fiber optic circuitry
MOSFET relay driver

FET Amplifiers
Chapter 8
Boylestad

Ch.8 Summary
Introduction
FETs provide:
• Excellent voltage gain
• High input impedance
• Low-power consumption
• Good frequency response

Ch.8 Summary
FET Small-Signal Model
Transconductance: The ratio of a change in ID to
the corresponding change in VGS
• Transconductance is denoted gm and given by:
GS
D
m
ΔV
ΔI
g 

Ch.8 Summary
Geographical Determination of gm

Ch.8 Summary
Mathematical Definitions of gm
GS
D
m
ΔV
ΔI
g 








P
GS
P
DSS
m
V
V
V
I
g 1
2
P
DSS
m
V
I
g
2
0 
DSS
D
m
P
GS
m
m
I
I
g
V
V
g
g 0
0 1 








For VGS = 0 V

Ch.8 Summary
FET Impedence
Ω


i
Z
Input impedance:
Output Impedance:
os
d
o
y
r
Z
1

 constant
VGS 

D
DS
d
ΔI
ΔV
r
where
yos= admittance parameter listed on FET spec sheets

Ch.8 Summary
FET AC Equivalent Circuit

Ch.8 Summary
Common-Source (CS) Fixed-Bias
The input is applied to the gate and
the output is taken from the drain
There is a 180 phase shift between
the circuit input and output

Ch.8 Summary
Calculations
G
i R
Z 
d
D
o ||r
R
Z 
10R
r
D
o
D
d
R
Z


Input impedance:
Output impedance:
)
( D
d
m
i
o
v ||R
r
g
V
V
A 


D
d R
r
D
m
i
o
v R
g
V
V
A
10




Voltage gain:

Ch.8 Summary
Common-Source (CS) Self-Bias
This is a common-source amplifier
configuration, so the input is applied
to the gate and the output is taken
from the drain.
There is a 180 phase shift
between input and output.

Ch.8 Summary
Calculations
G
i R
Z 
D
d
o ||R
r
Z 
R
r
D
o
D
d
R
Z
10


Input impedance:
Output impedance:
)
( D
d
m
v ||R
r
g
A 

D
d R
r
D
m
v R
g
A
10



Voltage gain:

Ch.8 Summary
Common-Source (CS) Self-Bias
Removing Cs affects
the gain of the circuit.

R
r
D
o
D
d
R
Z
10


Ch.8 Summary
Calculations
G
i R
Z 
Output impedance:
d
S
D
S
m
D
m
i
o
v
r
R
R
R
g
R
g
V
V
A






1
)
(
10
1 S
D
d R
R
r
S
m
D
m
i
o
v
R
g
R
g
V
V
A 





Voltage gain:
Input impedance:

Ch.8 Summary
Common-Source (CS)
This is a common-source
amplifier configuration, so the
input is applied to the gate and
the output is taken from the
drain.

Ch.8 Summary
Impedances
2
1||R
R
Zi 
D
d
o ||R
r
Z 
R
r
D
o
D
d
R
Z
10


Input impedance:
Output impedance:
)
( D
d
m
v ||R
r
g
A 

D
d R
r
D
m
v R
g
A
10



Voltage gain:

Ch.8 Summary
Source Follower (Common-Drain)
In a common-drain amplifier
configuration, the input is applied
to the gate, but the output is taken
from the source.
There is no phase shift between
input and output.

Ch.8 Summary
Impedances
m
S
d
o
g
||
||R
r
Z
1

S
d R
r
m
S
o
g
||
R
Z 10
1


G
i R
Z 
Input impedance:
Output impedance:
)
(
1
)
(
S
d
m
S
d
m
i
o
v
||R
r
g
||R
r
g
V
V
A


 10
1



 d
r
S
m
S
m
i
o
v
R
g
R
g
V
V
A
Voltage gain:

Ch.8 Summary
Common-Gate (CG) Circuit
The input is applied to the
source and the output is
taken from the drain.
There is no phase shift

Ch.8 Summary
Calculations
Input impedance:
Output impedance:









d
m
D
d
S
i
r
g
R
r
||
R
Z
1
D
d R
r
m
S
i
g
||
R
Z 10
1


d
D
o ||r
R
Z 
10

 d
r
D
o R
Z
















d
D
d
D
D
m
i
o
v
r
R
r
R
R
g
V
V
A
1
R
r
D
m
v D
d
R
g
A 10


Voltage gain:

Ch.8 Summary
D-Type MOSFET AC Equivalent

Ch.8 Summary
E-Type MOSFET AC Equivalent
gm and rd can be
found in the
specification sheet
for the FET.

Ch.8 Summary
Common-Source Drain-Feedback
There is a 180 phase shift

Ch.8 Summary
Calculations
Input impedance:
Output impedance:
)
(
1 D
d
m
D
d
F
i
||R
r
g
||R
r
R
Z



D
d
D
d
F R
,r
||R
r
R
D
m
F
i
R
g
R
Z 10
1




D
d
F
o ||R
||r
R
Z 
D
d
D
d
F R
,r
||R
r
R
D
o R
Z 10



)
( D
d
F
m
v ||R
||r
R
g
A 
 D
m
v D
R
d
r
,
D
||R
d
r
F
R
R
g
A 10




Voltage gain:

Ch.8 Summary
Common-Source Voltage-Divider Bias
The input is applied to the gate and
the output is taken from the drain.
There is a 180º voltage phase
shift between input and output.

Ch.8 Summary
Calculations
2
1||R
R
Zi 
Input impedance:
Output impedance:
D
d
o ||R
r
Z 
10

 d
r
D
o R
Z
)
( D
d
m
v ||R
r
g
A 
 D
d R
r
D
m
v R
g
A 10



Voltage gain:

Ch.8 Summary
Practical Applications
• Three-Channel Audio Mixer
• Silent Switching
• Phase Shift Networks
• Motion Detection System

ELECTRONIC DEVICES AND CIRCUIT THEORY 10th

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