This document discusses the datapath and control circuitry for a simple processor. It begins with background on instruction execution procedures and CPU overview. It then covers the datapath design, starting with R-format instructions involving register reads and ALU operations, then extending to I-format instructions adding memory access. The control circuitry derivation from the instruction register is explained. Finally, the full datapath and control is shown for R-type, load, branch, and jump instructions. Performance issues are noted, with pipelining suggested as an improvement.
This document provides an overview of implementing a processor that executes a subset of the MIPS instruction set. It describes the basic components needed, including an instruction memory to store and fetch instructions, registers to hold data, an ALU to perform arithmetic and logical operations, multiplexers to direct data flow, and a program counter to keep track of the next instruction address. The implementation is built up incrementally, first explaining how instructions are fetched and the program counter updated. It then describes adding components for R-type instructions like arithmetic and logical operations. Finally, it discusses adding units to support load/store memory instructions by sign-extending offsets and calculating effective addresses. The goal is to explain at a high level how the MIPS
This document provides an introduction to the 8085 microprocessor. It describes the main components of the 8085 including the ALU, register set, flags, and pin diagram. It also explains the addressing modes, instruction set, and basics of writing assembly language programs for the 8085 microprocessor.
This document provides an overview of computer architecture and microprocessors. It describes what a microprocessor is, its key design objectives of maximizing performance and productivity within constraints like power and area. It outlines the internal structure of a processor including the control unit, ALU, and register file. The document also discusses instruction set architecture, assembly code, types of instructions, encoding instructions into binary, and different number systems used.
The document discusses timing diagrams of the 8085 microprocessor and the 8255 Programmable Peripheral Interface (PPI). It provides a timing diagram example for the MVI A, 30H instruction in the 8085. It also explains that the 8255 PPI is a general purpose programmable I/O device that can be used to interface a CPU to external devices like ADCs and DACs. The 8255 has three 8-bit ports (A, B, C) that can be programmed as either inputs or outputs. The 8255 operates in either a bit set/reset mode or input/output mode.
The document discusses the design and implementation of a MIPS processor datapath. It describes building the datapath incrementally, starting with the basic components needed for instruction fetch, register-type instructions, load/store instructions, and branch instructions. Multiplexers are used to select between different data sources for different instruction types. Control signals are derived from the instruction fields to determine the operations during each step of the instruction execution cycle. The performance of a single-cycle and multicycle implementation is also analyzed.
The document provides an overview of key components of a computer's central processing unit (CPU). It discusses the CPU's arithmetic logic unit (ALU) and control unit, as well as registers, buses, cache memory, and main memory. It also describes machine language instructions and how programs are executed through fetching, decoding, and executing instructions in sequence.
This document discusses computer architecture and pipelining. It begins with defining the differences between computer organization and architecture. It then outlines the components needed for a MIPS processor implementation including registers, ALU, register file, memory units, and control signals. The document analyzes pipeline hazards such as data, structural, and control hazards. It also evaluates pipeline performance based on clock period, cycles per instruction, and interrupt frequency.
This document provides an overview of implementing a processor that executes a subset of the MIPS instruction set. It describes the basic components needed, including an instruction memory to store and fetch instructions, registers to hold data, an ALU to perform arithmetic and logical operations, multiplexers to direct data flow, and a program counter to keep track of the next instruction address. The implementation is built up incrementally, first explaining how instructions are fetched and the program counter updated. It then describes adding components for R-type instructions like arithmetic and logical operations. Finally, it discusses adding units to support load/store memory instructions by sign-extending offsets and calculating effective addresses. The goal is to explain at a high level how the MIPS
This document provides an introduction to the 8085 microprocessor. It describes the main components of the 8085 including the ALU, register set, flags, and pin diagram. It also explains the addressing modes, instruction set, and basics of writing assembly language programs for the 8085 microprocessor.
This document provides an overview of computer architecture and microprocessors. It describes what a microprocessor is, its key design objectives of maximizing performance and productivity within constraints like power and area. It outlines the internal structure of a processor including the control unit, ALU, and register file. The document also discusses instruction set architecture, assembly code, types of instructions, encoding instructions into binary, and different number systems used.
The document discusses timing diagrams of the 8085 microprocessor and the 8255 Programmable Peripheral Interface (PPI). It provides a timing diagram example for the MVI A, 30H instruction in the 8085. It also explains that the 8255 PPI is a general purpose programmable I/O device that can be used to interface a CPU to external devices like ADCs and DACs. The 8255 has three 8-bit ports (A, B, C) that can be programmed as either inputs or outputs. The 8255 operates in either a bit set/reset mode or input/output mode.
The document discusses the design and implementation of a MIPS processor datapath. It describes building the datapath incrementally, starting with the basic components needed for instruction fetch, register-type instructions, load/store instructions, and branch instructions. Multiplexers are used to select between different data sources for different instruction types. Control signals are derived from the instruction fields to determine the operations during each step of the instruction execution cycle. The performance of a single-cycle and multicycle implementation is also analyzed.
The document provides an overview of key components of a computer's central processing unit (CPU). It discusses the CPU's arithmetic logic unit (ALU) and control unit, as well as registers, buses, cache memory, and main memory. It also describes machine language instructions and how programs are executed through fetching, decoding, and executing instructions in sequence.
This document discusses computer architecture and pipelining. It begins with defining the differences between computer organization and architecture. It then outlines the components needed for a MIPS processor implementation including registers, ALU, register file, memory units, and control signals. The document analyzes pipeline hazards such as data, structural, and control hazards. It also evaluates pipeline performance based on clock period, cycles per instruction, and interrupt frequency.
This document describes instruction codes and the instruction cycle in a computer. It discusses how instruction codes specify operations for the computer to perform. The instruction cycle has four phases: 1) fetch an instruction from memory, 2) decode the instruction, 3) read the effective address if indirect addressing is used, and 4) execute the instruction. It then describes the fetch and decode phases in more detail, including transferring the program counter value to the address register to fetch the instruction from memory location and loading the instruction register.
The document describes the multi-cycle datapath and control approach for implementing a processor. It explains how instructions can be broken down into multiple execution steps that are each completed within a single clock cycle, allowing for simpler hardware at the cost of increased execution time per instruction. Additional registers are used to store intermediate results between cycles, and multiplexers allow functional units like the ALU and memory to be reused across cycles for different purposes. Control signals coordinate the movement of data between registers and functional units across each step of the multi-cycle implementation.
This document provides information about the PIC16F877A microcontroller. It discusses:
- The PIC16F877A is a popular 8-bit microcontroller with features like RAM, ROM, timers, ADC and I/O pins.
- It provides a block diagram showing the architecture and memory mapping of the chip.
- Programming and interfacing aspects like I/O pin operation, ADC, interrupts and communication protocols are described.
microprocessor8085 power point presentationrohitkuarm5667
The document provides an introduction to microprocessors and the 8085 microprocessor. It discusses that a microprocessor is a programmable VLSI chip that includes an ALU, registers, and control circuits. The 8085 is an 8-bit microprocessor developed by Intel that can address 64KB of memory. It has 40 pins and uses a three-stage fetch-decode-execute cycle to process instructions stored in memory.
Computer Architecture – An IntroductionDilum Bandara
Overview on high-level design of internal components of a computer. Cover step-by-step execution of a program through ALU while accessing & updating registers
Pipelining is a technique used in computer processors to overlap the execution of instructions to enhance performance. It works by dividing instruction execution into discrete stages, such as fetch, decode, execute, memory, and write-back, so that multiple instructions can be in different stages at the same time. In a pipelined processor, the average time to complete an instruction is reduced compared to a non-pipelined processor, leading to higher throughput. However, special techniques are needed to handle data and structural hazards that can occur when instructions interact in unexpected ways within the pipeline.
The document describes the 8085 microprocessor. It provides details on the architecture of the 8085 microprocessor including its pin configuration, address and data buses, control signals, interrupts, and block diagram. It also discusses the instruction set of the 8085 which includes data transfer, arithmetic, logical, and branching instructions. Programming models involving registers, flags, stacks, counters, and delays are explained. An example of a traffic light control system using the 8085 is also provided.
The 8085 microprocessor has the following key features:
- It is an 8-bit microprocessor that can operate on a single +5V supply and has a maximum clock frequency of 3MHz. It has 40 pins and uses NMOS technology.
- It has an 8-bit register array including general purpose and flag registers, as well as 16-bit program counter and stack pointer registers.
- The architecture consists of an ALU and logical group, instruction decoder, timing and control circuitry, and interrupt control group.
- It has an 8-bit multiplexed address/data bus that reduces the number of pins, allowing it to access 64KB of memory with 16 address lines.
The document discusses timing diagrams and machine cycles in the 8085 microprocessor. It provides details on the different machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write. It explains that the 8085 has a clock signal divided into T-states that represent portions of machine cycle operations. Examples are given of timing diagrams for instructions like MOV B,C, MVI B,43, and STA 526A to illustrate the sequence of events over multiple T-states.
The document provides an overview of computer architecture and microprocessors. It discusses microprocessor components like the accumulator, registers, flags, and control bus. It describes microprocessor operations like memory reads, writes and I/O. It also covers the 8085 microprocessor architecture in detail, including its pin configuration, buses, registers, interrupts and timing.
The document provides an overview of microprocessors and microcontrollers. It discusses the functional blocks of a microprocessor system including the CPU, memory, and I/O devices. It then covers various number systems used in microprocessors like binary, hexadecimal, and their advantages. The document reviews logic devices like tri-state buffers and latches. It provides details on the 8085 microprocessor including its features, registers, interrupts, pin diagram, instruction format and classification.
This document provides an overview of the topics that will be covered in lectures 6-9 of a course on the ATmega328 microcontroller and Arduino. Lecture 6 will introduce the ATmega architecture, instruction set, I/O pins, and the Arduino programming language. Lecture 7 will cover controlling time with interrupts and timers. Lecture 8 will include a guest lecture on radio communication. Lecture 9 will discuss designing PID controllers. The document then provides details on the ATmega328 architecture, memory, registers, instruction set, I/O interfaces and Arduino programming.
The document provides information about the 8085 microprocessor, including its architecture, features, instruction formats, and addressing modes. The 8085 is an 8-bit microprocessor with an accumulator, registers, arithmetic logic unit (ALU), flags, and I/O controls. It has three types of instructions that are 1, 2, or 3 bytes long. The addressing modes allow instructions to specify operands and include immediate, direct, register, register indirect, and implicit modes.
PIC Introduction and explained in detailedAnkita Tiwari
The document provides an introduction to the PIC microcontroller. It discusses what a microcontroller is, compares microcontrollers to general purpose microprocessors, and briefly outlines the history of the PIC microcontroller. It then describes features of the PIC16F84 microcontroller including its clock generator, reset function, ports, central processing unit, and memory organization including flash memory, RAM, and ROM. It also covers the timer and prescalar functions.
The document provides an overview of computer organization and architecture. It discusses the basic components of a computer including the CPU, memory, and registers. It then describes the specific architecture of a basic computer model, including its instruction set, addressing modes, and register set. The basic computer uses a 16-bit word size and has instructions for memory access, register operations, and input/output. It connects its registers through a common 16-bit bus controlled by three lines.
This document provides an overview of the instruction set of the 8085 microprocessor. It discusses the different types of instructions including one-byte, two-byte, and three-byte instructions. It describes the various instruction categories such as data transfer, arithmetic, logical, branching, and machine control instructions. It also covers addressing modes, assembly language programming, and examples of arithmetic operations and first programs. The document serves as an introduction to understanding the instruction set and programming of the 8085 microprocessor.
This document provides information about the objectives, outcomes, and modules of a computer organization course. The course aims to explain computer subsystems and their organization, illustrate how programs are executed as machine instructions, and describe memory hierarchy and arithmetic/logical operations. It will also cover the organization of simple and pipelined processors. The course outcomes include explaining basic computer organization and demonstrating how subsystems like the processor, memory, and I/O systems function.
This document provides an outline and overview of the topics that will be covered in Lecture 6 of the CSE P567 course, including the ATmega328 architecture, I/O pins, the Arduino C++ language, and timing functions. It discusses the ATmega328's Harvard architecture with separate flash, SRAM, and EEPROM memory spaces. It describes the AVR CPU, registers, addressing modes, instruction set, and I/O functionality. It also covers the Arduino development board's pin mapping and digital/analog I/O functions.
This document describes instruction codes and the instruction cycle in a computer. It discusses how instruction codes specify operations for the computer to perform. The instruction cycle has four phases: 1) fetch an instruction from memory, 2) decode the instruction, 3) read the effective address if indirect addressing is used, and 4) execute the instruction. It then describes the fetch and decode phases in more detail, including transferring the program counter value to the address register to fetch the instruction from memory location and loading the instruction register.
The document describes the multi-cycle datapath and control approach for implementing a processor. It explains how instructions can be broken down into multiple execution steps that are each completed within a single clock cycle, allowing for simpler hardware at the cost of increased execution time per instruction. Additional registers are used to store intermediate results between cycles, and multiplexers allow functional units like the ALU and memory to be reused across cycles for different purposes. Control signals coordinate the movement of data between registers and functional units across each step of the multi-cycle implementation.
This document provides information about the PIC16F877A microcontroller. It discusses:
- The PIC16F877A is a popular 8-bit microcontroller with features like RAM, ROM, timers, ADC and I/O pins.
- It provides a block diagram showing the architecture and memory mapping of the chip.
- Programming and interfacing aspects like I/O pin operation, ADC, interrupts and communication protocols are described.
microprocessor8085 power point presentationrohitkuarm5667
The document provides an introduction to microprocessors and the 8085 microprocessor. It discusses that a microprocessor is a programmable VLSI chip that includes an ALU, registers, and control circuits. The 8085 is an 8-bit microprocessor developed by Intel that can address 64KB of memory. It has 40 pins and uses a three-stage fetch-decode-execute cycle to process instructions stored in memory.
Computer Architecture – An IntroductionDilum Bandara
Overview on high-level design of internal components of a computer. Cover step-by-step execution of a program through ALU while accessing & updating registers
Pipelining is a technique used in computer processors to overlap the execution of instructions to enhance performance. It works by dividing instruction execution into discrete stages, such as fetch, decode, execute, memory, and write-back, so that multiple instructions can be in different stages at the same time. In a pipelined processor, the average time to complete an instruction is reduced compared to a non-pipelined processor, leading to higher throughput. However, special techniques are needed to handle data and structural hazards that can occur when instructions interact in unexpected ways within the pipeline.
The document describes the 8085 microprocessor. It provides details on the architecture of the 8085 microprocessor including its pin configuration, address and data buses, control signals, interrupts, and block diagram. It also discusses the instruction set of the 8085 which includes data transfer, arithmetic, logical, and branching instructions. Programming models involving registers, flags, stacks, counters, and delays are explained. An example of a traffic light control system using the 8085 is also provided.
The 8085 microprocessor has the following key features:
- It is an 8-bit microprocessor that can operate on a single +5V supply and has a maximum clock frequency of 3MHz. It has 40 pins and uses NMOS technology.
- It has an 8-bit register array including general purpose and flag registers, as well as 16-bit program counter and stack pointer registers.
- The architecture consists of an ALU and logical group, instruction decoder, timing and control circuitry, and interrupt control group.
- It has an 8-bit multiplexed address/data bus that reduces the number of pins, allowing it to access 64KB of memory with 16 address lines.
The document discusses timing diagrams and machine cycles in the 8085 microprocessor. It provides details on the different machine cycles - opcode fetch, memory read, memory write, I/O read, and I/O write. It explains that the 8085 has a clock signal divided into T-states that represent portions of machine cycle operations. Examples are given of timing diagrams for instructions like MOV B,C, MVI B,43, and STA 526A to illustrate the sequence of events over multiple T-states.
The document provides an overview of computer architecture and microprocessors. It discusses microprocessor components like the accumulator, registers, flags, and control bus. It describes microprocessor operations like memory reads, writes and I/O. It also covers the 8085 microprocessor architecture in detail, including its pin configuration, buses, registers, interrupts and timing.
The document provides an overview of microprocessors and microcontrollers. It discusses the functional blocks of a microprocessor system including the CPU, memory, and I/O devices. It then covers various number systems used in microprocessors like binary, hexadecimal, and their advantages. The document reviews logic devices like tri-state buffers and latches. It provides details on the 8085 microprocessor including its features, registers, interrupts, pin diagram, instruction format and classification.
This document provides an overview of the topics that will be covered in lectures 6-9 of a course on the ATmega328 microcontroller and Arduino. Lecture 6 will introduce the ATmega architecture, instruction set, I/O pins, and the Arduino programming language. Lecture 7 will cover controlling time with interrupts and timers. Lecture 8 will include a guest lecture on radio communication. Lecture 9 will discuss designing PID controllers. The document then provides details on the ATmega328 architecture, memory, registers, instruction set, I/O interfaces and Arduino programming.
The document provides information about the 8085 microprocessor, including its architecture, features, instruction formats, and addressing modes. The 8085 is an 8-bit microprocessor with an accumulator, registers, arithmetic logic unit (ALU), flags, and I/O controls. It has three types of instructions that are 1, 2, or 3 bytes long. The addressing modes allow instructions to specify operands and include immediate, direct, register, register indirect, and implicit modes.
PIC Introduction and explained in detailedAnkita Tiwari
The document provides an introduction to the PIC microcontroller. It discusses what a microcontroller is, compares microcontrollers to general purpose microprocessors, and briefly outlines the history of the PIC microcontroller. It then describes features of the PIC16F84 microcontroller including its clock generator, reset function, ports, central processing unit, and memory organization including flash memory, RAM, and ROM. It also covers the timer and prescalar functions.
The document provides an overview of computer organization and architecture. It discusses the basic components of a computer including the CPU, memory, and registers. It then describes the specific architecture of a basic computer model, including its instruction set, addressing modes, and register set. The basic computer uses a 16-bit word size and has instructions for memory access, register operations, and input/output. It connects its registers through a common 16-bit bus controlled by three lines.
This document provides an overview of the instruction set of the 8085 microprocessor. It discusses the different types of instructions including one-byte, two-byte, and three-byte instructions. It describes the various instruction categories such as data transfer, arithmetic, logical, branching, and machine control instructions. It also covers addressing modes, assembly language programming, and examples of arithmetic operations and first programs. The document serves as an introduction to understanding the instruction set and programming of the 8085 microprocessor.
This document provides information about the objectives, outcomes, and modules of a computer organization course. The course aims to explain computer subsystems and their organization, illustrate how programs are executed as machine instructions, and describe memory hierarchy and arithmetic/logical operations. It will also cover the organization of simple and pipelined processors. The course outcomes include explaining basic computer organization and demonstrating how subsystems like the processor, memory, and I/O systems function.
This document provides an outline and overview of the topics that will be covered in Lecture 6 of the CSE P567 course, including the ATmega328 architecture, I/O pins, the Arduino C++ language, and timing functions. It discusses the ATmega328's Harvard architecture with separate flash, SRAM, and EEPROM memory spaces. It describes the AVR CPU, registers, addressing modes, instruction set, and I/O functionality. It also covers the Arduino development board's pin mapping and digital/analog I/O functions.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
artificial intelligence and data science contents.pptxGauravCar
What is artificial intelligence? Artificial intelligence is the ability of a computer or computer-controlled robot to perform tasks that are commonly associated with the intellectual processes characteristic of humans, such as the ability to reason.
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International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
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Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
3. Background
Introduction
CPU performance factors
Instruction count
? Determined by ISA and Compiler
CPI and Cycle time
? Determined by CPU hardware
Implementations Covered MIPS (Microprocessor without Interlocked
Pipelined Stages) implementations
A simplified version
An improved version by pipelining technique
Instructions covered for MIPS implementation
Memory reference: lw, sw
Arithmetic/logical: add, sub, and, or, slt
Control transfer: beq, j
ECE 374 U. Tida 3 / 38
4. Background
Instruction Execution Procedure
1 PC (program counter) → instruction memory, fetch instruction
2 Register numbers → register file, read
3 Instruction determines ALU to calculate:
Arithmetic/logic result
Memory address for load/store
Branch target address
4 Access data memory for load/store or write to register
5 PC ← target address or PC+4
ECE 374 U. Tida 4 / 38
6. Background
CPU Overview
We cannot join wires together and expect it to select whatever we
need by itself.
Use multiplexer to select between data
ECE 374 U. Tida 6 / 38
8. Background Logic Design
Logic Design Basics
Binary Encoded Information
Two states: Low voltage = 0 and High voltage = 1. (Traditional
method)
One wire per bit
Multi-bit data encoded on multi-wire buses
Combinational Element
Operate on data continuously
Output is a function of input
State (Sequential Element
Store information for a certain period
ECE 374 U. Tida 8 / 38
9. Background Logic Design
Typical Combinational Elements
Given a set of inputs, it always produces the same output
AND-gate
Y = A & B
Adder
Y = A + B
Multiplexer
Y = S ? I1 : I0
Arithmetic Logical Unit (ALU)
Y = F(A , B)
ECE 374 U. Tida 9 / 38
10. Background Logic Design
Sequential Element
Register: Stores data in a circuit
Clock signal determines when to update the stored value
Edge-triggered flip flop: update data when clk changes 0 to 1 =⇒
positive triggered (1 to 0 =⇒ negative triggered)
ECE 374 U. Tida 10 / 38
11. Background Logic Design
Sequential Element with write control
Register with write control
Only updates on clock edge when write control input is 1
ECE 374 U. Tida 11 / 38
12. Background Logic Design
Maximum clock speed
Combinational logic transforms data between clock edges
Longest delay for data to travel [input state element → combinational
logic → output state element] determines clock period
ECE 374 U. Tida 12 / 38
13. Datapath Design
Datapath Design Approach
Datapath design
Design of elements that process data and addresses (of data memory
and instruction memory) in the CPU
Consists of Registers, ALU, Mux’s, memories, ...
Approach
Let’s start with one set of instructions and include rest systematically
by refining the overall design of previous step.
Instruction-set Design Sequence we follow
1 R-format instructions
2 I-format instructions
3 J-format instructions
ECE 374 U. Tida 13 / 38
14. Datapath Design
Step 1: Instruction Fetch
Program Counter (PC) Register
Holds address of the current instruction
Increment by 4 after each fetch!
Common step for all instruction type execution
ECE 374 U. Tida 14 / 38
15. Datapath Design R-format
Datapath design for R-type instructions
Register format (R-format)
Instruction Fields:
op: operation code or opcode of an instruction.
rs: first source register number (READ)
rt: second source register number (READ)
rd: destination register number (WRITE)
shamt: shift amount
funct: function code
ECE 374 U. Tida 15 / 38
16. Datapath Design R-format
Step 2: Read registers
R-format instruction has two register addresses of a register file and
this information is used to read the two registers simulataneously!
ECE 374 U. Tida 16 / 38
17. Datapath Design R-format
Step 3: Perform operation
The register read in Step 2 will be given to the ALU to perform the
required opeartion!
ECE 374 U. Tida 17 / 38
18. Datapath Design R-format
Step 4: Write back result
ALU result will be stored in the destination register
RegWrite is a control signal that will be high almost at the end of
clock cycle!
ECE 374 U. Tida 18 / 38
19. Datapath Design I-format
Datapath design extension to include I-format instructions
Immediate format (I-format)
Instruction Fields:
op: operation code or opcode of an instruction. Determined by the
hardware control
rs: first source register number (READ)
rt: destination register number (READ (SW)/WRITE (LW))
constant: 16 bit size
address: 16 bit offset added to base address in rs
Different formats complicate decoding but allow 32-bit instructions
uniformly.
ECE 374 U. Tida 19 / 38
20. Datapath Design I-format
Step 2: Read registers
Two reads occur for sw instruction and only one read occurs for lw
instruction
ECE 374 U. Tida 20 / 38
21. Datapath Design I-format
Step 3: Address calculation
The register read in Step 2 will be given to the ALU to perform the
required opeartion!
ECE 374 U. Tida 21 / 38
28. Control circuitry
ALU operation
Utilize it for
1 Addition in Load/Store instructions for memory address calculation
2 Subtraction in branch if equal (beq) instruction
3 Operation depending on funct field for R-type instructions!
ALU operation (4-bit) Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR
ECE 374 U. Tida 28 / 38
29. Control circuitry
ALU control
ALU operation (4-bits) are set depending on opcode and funct bits
Since there are only 4 different opcodes possible i.e., lw, sw, beq and
R-type, we can assume 2 ALUOp bits derived from opcode
We will design a combination logic circuits based on truth table to
obtain ALU operation bits
inst ALUOp Operation funct ALU function ALU operation
lw 00 load word XXXXXX add 0010
sw 00 load word XXXXXX add 0010
beq 01 branch if equal XXXXXX subtract 0110
R-type 10
add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set on less than 101010 set on less than 0111
ECE 374 U. Tida 29 / 38
30. Control circuitry
Main control circuit from instruction register
Control signals are derived from instruction register!
ECE 374 U. Tida 30 / 38
32. Datapath and control: Processor
Datapath and control of R-type instruction
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33. Datapath and control: Processor
Datapath and control of load instruction
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34. Datapath and control: Processor
Datapath and control of branch-on-equal instruction
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35. Datapath and control: Processor
How about Unconditional Jump (j)?
Jump uses word address
Update PC with concatenation of
? Top 4-bit of old PC
? 26-bit jump address
? 00 (multiply by 4)
Need an extra control signal decoded from opcode
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36. Datapath and control: Processor
Datapath and control with Jumps added
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37. Datapath and control: Processor
Performance metric and issues
Longest delay determines clock period
Critical path: load instruction
? Instruction memory → Register file → ALU → Data memory →
Register file
What happens if the frequency of load instruction is low?
We can improve performance by pipelining (will be covered in next
lecture series!)
Sincere suggestion: Revise the lecture slides, clear doubts, practice many
problems, prepare to become a computer engineer!
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38. What have we learnt today?
1 Background
Logic Design
2 Datapath Design
R-format
I-format
3 Control circuitry
4 Datapath and control: Processor
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