Digital Design Session 18

Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2
Session 18: Focus
 Latches and Flip-flops
◦ Level and Edge-triggered clocks
◦ Clock edges (+ve and –ve)
 Edge-triggered D Flip-flops
◦ Negative edge-triggered (Master-Slave)

Latches and Flip-flops

D-Latch: Transparent Latch
 The Control is called a trigger to the latch which allows
changes to the output of the latch based on the input (D)
 When Control is HIGH, any changes to D is reflected at the
output (Q) of the latch
 Which means that the latch is transparent to the input when
the Control is HIGH
D
C
Q
Logic Diagrams
S
R
C
S
R

Latches as Storage Elements
 The state (Q) of a latch is switched by a change in
the D with control input (C) is enabled.
 This momentary change is called a trigger, and the
transition it causes is said to trigger the latch
 The state of latches change based on the level of the
control input (C)
 During the entire period of the control input the
latch output (Q) is connected to the input (D) value
 This creates an unstable state when these latches are
used in the feedback loop of sequential circuits

Latches in the Feedback loop
 Since the output of a latch is connected to
combinational circuit, and the output from the
combination circuit is feeding into Latches
 Any changes in this loop creates an unstable state due the
inherent nature of latches continuously changing its
output value based on the level of the inputs to it
 This can be prevented if latches are made to change state
based on the edges rather than levels of the inputs
Latches
Input
Latches
Output

Flip-Flops
 Flip-flop circuits are constructed in such a way as to make them
operate properly when they are part of a sequential circuit
 By controlling them with a common clock
 The key to the proper operation of a flip-flop is to trigger it only
during a signal transition
Flip-
Flops
Clock
Two possible
transitions
0 to 1: Positive Edge
1 to 0: Negative Edge

Clock Pulse Transitions
Clock Pulses
Period

Clock Responses
 The figure above shows when does the output of a
latch or a flip-flap change with respect to its control
input (clock)
Level triggered
Latches
Positive-edge
triggered
Flip-flops
Negative-edge
triggered
Flip-flops

Negative Edge-triggered
D Flip-flop
(Master-Slave)

D-Latch Construction
11
S
R
C
S
R
Basic S’R’ Latch
C
Function Table of S’R’ Latch
S’ R’
(after S’ = 1, R’ = 0)
(after S’ = 0, R’ = 1)
D Latch

Master-slave D Flip-flop
 The output Y of Master D Latch connects to input D
only when the Clk is HIGH
 But, during that time slave D latch is disabled, so Q is not
affected by the changes happening to Y
Master is
Enabled
Slave is Enabled
S2
D Q
S1
D Q
S1: Open: Clk LOW
S1: Closed: Clk HIGH
S2: Open: Clk HIGH
S2: Closed: Clk LOW

 When the Clk changes to LOW, Master is disabled after
having stored the state of D into it
 Now Slave gets enabled connecting the stable input Y to Q
 Thus, a change in the output (Y) of the flip-flop can be
triggered only by and during the transition of the clock
from 1 to 0
Master is
Enabled
Slave is Enabled

A Negative Edge-triggered
 The value that is produced at the output (Q) of the flip-flop is the
value that was stored in the master stage immediately before the
negative edge occurred
 So, the Master-slave construction of D Flip-flop is a negative
edge-triggered flip-flop
 The logic symbol of the negative edge-triggered D-flip-flop is
above
 Note that both Master and slave stages are D latches
 Or, the slave can be a SR Latch, but Master has to be a D Latch
Q
The state before
1-to-0
Transition is
Captured
> is the dynamic
indicator

Flip-flop Explained
 In a flip-flop, before an output can change, the path
from its inputs to its outputs is broken
 So a flip-flop cannot “see” the change of its output or
of the outputs of other similar flip-flops at its input
during the same clock pulse.
 Thus, the new state of a flip-flop depends only on the
immediately preceding state
◦ And the flip-flops do not go through multiple changes of
state.

Session 18: Summary
 Latches and Flip-flops
◦ Level and Edge-triggered clocks
◦ Clock edges (+ve and –ve)
 Edge-triggered D Flip-flops
◦ Negative edge-triggered (Master-Slave)

References
Ref 1 Ref 2

Digital Design Session 18

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