Digital Design Session 17

Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2
Session 17: Focus
 Storage Elements
◦ SR – Latches
 Using NOR gates
◦ S’R’-Latches
 Using NAND Gate
 D Latch (Transparent latch)
 Graphic Symbols of Latches

SR-Latches with NOR Gates
Logic Diagram Function Table
Active HIGH circuit
Active HIGH here corresponds to the control inputs (R & S)
When R = 1, Q is Reset to 0
When S = 1, Q is set to 1
Always Set means setting a value to ONE
Always Reset means resetting a value to ZERO
It is forbidden because
If both Set (1) and Reset (1)
Are given together
the next state of
Q and Q’ both will be zero
which is an incorrect state

Storage Elements
S’R’ Latches – With NAND Gates

S’R’-Latches with NAND Gates
Logic Diagram Function Table
Active LOW circuit
Active low here corresponds to the control inputs (R ‘& S’)
When R’ = 0, Q is Reset to 0
When S’ = 0, Q is set to 1
Always Set means setting a value to ONE
Always Reset means resetting a value to ZERO
It is forbidden because
If both Set (0) and Reset (0)
the next state of
Q and Q’ are indeterminate
S’ R’S’
R’
(after S’ = 1, R’ = 0)
R’
(after S’ = 0, R’ = 1)

S’R’-Latches with NAND Gates (Active Low)
 After both inputs go back to 1, we are allowed to change the state of
the latch by placing a 0 in the R’ input
 This action causes the circuit to go to the reset state and stay there
even after both inputs return to 1
 The condition that is forbidden for the NAND latch is both inputs
being equal to 0 at the same time,
 An input combination that should be avoided
 It operates normally with both inputs at 1,
unless the state of the latch has to be changed
 Giving a 0 to the S’ input causes output Q to go
to 1, putting the latch in the set state
 When the S’ input goes back to 1, the
circuit remains in the set state.
Active LOW circuit
R’
S’
S’ R’

S’R’-Latches with NAND Gates
 Note that the input signals for the NAND require the
complement of those values to be used for the NOR latch
 Because the NAND latch requires a 0 signal to change its state,
it is referred to as an S’R’ latch
 The primes (or, sometimes, bars over the letters) designate the
fact that the inputs must be in their complement form to
activate the circuit.
 NAND based implementation of S’R’ Latches are more
preferred than NOR based design
 Because NAND based designs are faster and smaller in size
 Though SR or S’R’ latches are not used in real circuits
 Other useful latches and flip-flops are constructed from it

Quiz 1: Draw the output waveform
S’
R’
Q
Active LOW circuit
S’
R’
(after S’ = 1, R’ = 0)
(after S’ = 0, R’ = 1)
S’ R’
S’
R’
1
1

SR-Latches with Enable or Control (C) Input
Logic Diagram
Adding C makes the NAND
implementation as Active-high
C
Function Table
C

Quiz 2: Draw the output waveform
C
C
C

D Latch
(Transparent Latch)

D Latch – Transparent Latch
Here SR inputs becoming 11 is eliminated
Logic Diagrams
Function Tables
SR-Latch D-Latch
S
R
C
S
R
C
C
C
Basic S’R’ Latch

D Latch – Transparent Latch
 One way to eliminate the undesirable condition of the
indeterminate state in the SR latch is
 To ensure that inputs S and R are never equal to 1 at the
same time.
 This is done in the D latch
 This has only two inputs D (data) and C (control)
 The D input goes directly to the S input, and its complement is
given to the R input
 The D latch receives that designation from its ability to hold
data in its internal storage
 It provides a path from D to the output, when C is enabled, so
it is also called Transparent Latch

D-Latch: Transparent Latch
 The Control is called a trigger to the latch which allows
changes to the output of the latch based on the input (D)
 When Control is HIGH, any changes to D is reflected at the
output (Q) of the latch
 Which means that the latch is transparent to the input when
the Control is HIGH
D
C
Q

Problem with the Latches
 When latches are used for the storage elements, a
serious difficulty arises.
 The state transitions of the latches start as soon as the
clock pulse (Control input) changes to the logic 1 or
High level.
 The new state of a latch may appear at its output while
the control or clock pulse is still active.
 The final state depends on how long the clock pulse
stays at the logic-1 level
 Because of this behaviour, output of a latch cannot be
given to another latch as input which runs on the same
clock pulse

Graphic Symbols of Latches
SR Latch
Built with NOR Gates
Active HIGH
S’R’ Latch
Built with NAND Gates
Active LOW
D Latch
Active HIGH

Session 17: Summary
 Storage Elements
◦ SR-Latches
 NAND Gate
◦ SR Latch with Enable Input
 D Latch (Transparent latch)
 Graphic Symbols of Latches

References
Ref 1 Ref 2

Digital Design Session 17

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Digital Design Session 17