Design verilog code [in ISE Project Navigator: Verilog Module, Verilog Text Fixture_TB] for: 4-bits synchronous up/down counter with an enable. This counter has three inputs Clock, ENABLE, and UP/DOWN’ and four outputs O3 (MSB),O2,O1, and O0 (LSB). The table below defines the circuit behavior: ENABLE UP/DOWN\' Function 0 X Stop counting 0 Count down: 15,14,...,1,0,15,14, Count up: 0,1,...,14,15,0,1 Solution What is the verilog code for 4-bit updown counter with synchronous clear? 2 ANSWERS [Sanket Naik] Sanket Naik, been there, done that...! 1.7k Views module up_dn_cnt ( input clk, input clr, //Active high clear input up, //Active high up count enable input dn, //Active down up count enable output [3:0] count ); always @(posedge clk, posedge clr) begin if(clr == 1) begin count <= \'b0; end else begin if(up == 1) begin count <= count + 1; end else if(dn == 1) begin count <= count - 1; end end end endmodule.

1. Design verilog code [in ISE Project Navigator: Verilog Module, Verilog Text Fixture_TB] for:
4-bits synchronous up/down counter with an enable. This counter has three inputs Clock,
ENABLE, and UP/DOWN’ and four outputs O3 (MSB),O2,O1, and O0 (LSB). The table below
defines the circuit behavior: ENABLE UP/DOWN' Function 0 X Stop counting 0 Count down:
15,14,...,1,0,15,14, Count up: 0,1,...,14,15,0,1
Solution
What is the verilog code for 4-bit updown counter with synchronous clear?
2 ANSWERS
[Sanket Naik]
Sanket Naik, been there, done that...!
1.7k Views
module up_dn_cnt (
input clk,
input clr, //Active high clear
input up, //Active high up count enable
input dn, //Active down up count enable
output [3:0] count
);
always @(posedge clk, posedge clr) begin
if(clr == 1) begin
count <= 'b0;
end else begin
if(up == 1) begin
count <= count + 1;
end else if(dn == 1) begin
count <= count - 1;
end
end
end
endmodule