1) The document discusses the design, simulation, and analysis of single electron transistor (SET) and SET-CMOS logic gates. 2) SETs operate using electron tunneling and have advantages like ultra-low power consumption compared to CMOS, but are limited to low temperatures. 3) The objective is to study the characteristics of SET logic gates like AND and OR, design a universal NAND gate, and propose a SET-CMOS cascaded logic gate to overcome the temperature limitations of SETs.

1. DESIGN SIMULATION AND ANALYSIS OF SET
& SET-CMOS LOGIC GATES

2. SET & IT’S HISTORY
The single electron transistor or SET is type of switching device that uses controlled
electron tunneling to amplify current. The transistor consists of a source electrode
and a source drain, which is joined with the help of a tunneling island that is
also capacitively connected to a gate. A single-electron transistor is usually
made by keeping two tunnel junctions in series. The electrons can travel to
another electrode only through the insulator.

4. OBJECTIVE
 To study the characteristics of SET
 To read the characteristics of different SET logic gates and
to comparison between each gate.
 Design Universal Logic gate NAND.
 Design SET-CMOS Cascaded Logic Gate.

5. WHY SET?
 Supply voltage requirement for a SET is 35mV whereas the supply
voltage requirement for a CMOS is 3.5V. SET based circuits consumes
almost 5 million times less power than CMOS inverter.
 Operation of sets is limited to low temperatures. We can use SET in
deep space research where temperature is too low.
 SET provide High sensitivity which gives us an opportunity to make
devices for sensitive research like LIGO, QUANTUM LEVEL
RESEARCH etc.
 Compact size, simplifier circuit and feature of reproducibility.
 SET provide straight forward co-integration with traditional CMOS
circuits.
 Performance of SET is better than the field effect transistors because of
their compact size.
 SET have high input and low voltage gain besides this these are also
very sensitive to random background charges, due to this set have
replaced the FET is many applications where low output impedances
and large gain necessary.

6. CMOS & SET: Competitor/Collaborator?
SET CMOS
 Nano-scale device
 Ultra low power dissipation
 New functionalities
 High Speed
 Very Stable Technology
– Lack of room temperature operable
technology
– Reproducibility at nanoscale
Low Current drive (~nA)
Background charge effect
SCE/DIBL(short-channel effect in MOSFETs referring
originally to a reduction of threshold voltage of the transistor at higher
drain voltages.)
 Power dissipation
 Process variations at
nanoscale
sourcesource
drain
source
drain
source
drain

7. BASIC PHYSICS OF SET
The basic physics of SET is the combination of different theories,
Coulomb Blockade: When surface of a conductor is very small electrons
inside the conductor will create a strong coulomb repulsion preventing other
electrons to flow.
Superconductivity : For a certain material when temperature is very low
exactly zero electrical resistance and expulsion of magnetic flux fields occur,
this is known as superconductivity. This phenomena only occur that time
when Coulomb Blockade is achieved.

8. Quantum Tunneling : Its a Quantum mechanical effect in which particles have
a finite probability of crossing an energy barrier, such as the energy needed
to break a bond with another particle, even though the particle's energy is
less than the energy barrier.
Quantum Dot: Quantum dots (QD) are very small semiconductor particles, only
several nanometers in size. Its so small that their optical and electronic
properties differ from those of larger particles. Quantum dots are also sometimes
referred to as artificial atoms. It is highly tunable properties. QD are of wide
interest. Fig, Shows Cadmium sulfide quantum dots on cells.

9. OPERATION OF SET
Fig. shows 100nm electron microscopic photo of a SET. Here a dot is
surrounded by three electrodes. All three electrodes are coupled to
the dot capacitively. Potential change in any of them can cause an
electrostatic energy change in the dot. Source and Drain are tunnel
coupled to the dot and electron transport is allowed only between the
dot and these two electrodes. Gate-2 is has been introduced for
proper switching shown in figure right. Gate-2 is always kept in
ground.

10. Below figures explain the action of a SET. The energy of an electron in drain is
expressed as ED and the energy of an electron in source is expressed as
Es. If a positive voltage is activated from source to drain, then Ed>Es. The
energy of energy level of the quantum dot or island which is not occupied by
an electron is taken as Ei.
For available energy level of island with zero gate bias,
For positive gate bias,

11. SIMULATION METHOD
Single Electron Device can be simulate using two method;
 Master Equation (ME)
1. It is effective only for simple circuits which have few islands.
2. This method can describe the time evolution probabilities of
the system in occupying discrete state.
3. It is a method for modeling all states of electron tunneling
process uniquely.
4. It’s a Numerical Process.
 Monte Carlo (MC)
1. Its slower than Master Equation.
2. It has the unique option for large systems.
3. It is a stochastic technique.
4. This method is based on random inputs which may obey any
type of distribution according to the nature of the
investigated problem.
5. Its more accurate than Master Equation.

12. AND GATE
AND logic is generally used to multiply two inputs. We get higher
output for two high input. AND gate can be design using two
parallel SET with two Series SET at a common point. Below
figure shows the input and output voltage of AND logic gate.

13. AND Gate at 4.2K

14. AND Gate at room temp.

15. AND Gate Output Current
Yellow 100K
Blue 77K
Red 11K
Green 4.2K

16. OR GATE
The OR gate is a digital logic gate that implements logical disjunction – it behaves
according to the truth table below. A HIGH output (1) results if one or both the inputs
to the gate are HIGH (1). If neither input is high, a LOW output (0) results. In another
sense, the function of OR effectively finds the maximum between two binary digits,
just as the complementary AND function finds the minimum.
INPUT OUTPUT
A B A OR B
0 0 0
0 1 1
1 0 1
1 1 1

17. OR Gate at 4.2 K 30K & 77K

18. DISADVANTAGE
 To operate SET’s at room temperatures is too
challenging.
 Large quantities of Nano particles less than 10nm in
diameter must be of synthesized to fabricate SET, but it is
very hard to fabricate large quantities of SET’s by
traditional optical lithography and semiconducting
process.
 It is difficult to link SET with the outside environment.

19. SET-CMOS CASCADED SYSTEM
We propose CMOS cascaded with SET system which can neglect major problem
of SET which is temperature limitation. Below figure shows how we can
fabricate SET-CMOS Cascaded System.

20. CVD= Chemical vapor deposition
This process is used to produce high quality, high-performance, solid
materials.
LTO=Low Temperature Oxide
LTO is silicon dioxide that is deposited on the surface of the wafer rather than
grown like thermal field or gate oxides.

21. CASCADED LOGIC GATE
Cascade CMOS gives a benefit of using SET neglecting the temperature effect of
SET. This Cascaded CHIP will be more Small & Powerful. Below a Cascaded
NAND Logic Gate is represented with all notation. SET based circuits
consumes almost 5 million times less power than CMOS inverter.

22. CASCADE NAND OUTPUT 4.2k TEMP & High Frequency

23. CASCADE NAND OUTPUT ROOM TEMP

24. PROPOSED SYSTEM ADVANTAGE &
DISVANTAGE
ADVANTAGES
 We can overcome temperature problem using CASCADED SET
design.
 Its much more efficient than general CMOS device.
 Supply voltage requirement for a Cascaded SET is 35mV whereas
the supply voltage requirement for a CMOS is 3.5V. SET based
circuits consumes almost 5 million times less power than CMOS
inverter.
 SETMOS is one such hybrid CMOS-SET architecture, which
combines the virtues of both devices and exhibits many novel
functionalities which are very difficult to achieve by either of these
technologies.
 Infamous randomness of the background charge recovery.

25. DISADVANTAGE
 We can not recover co-tunneling problem at all.
 Though we can overcome the temperature issue but
lithography is another challenge which is still a big challenge.
 As chip size small so interconnection of chip increase is too
much.
 Fabricating quantum dot is also a big challenge.

26. FUTURE WORK & LIMITATION
CASCADE LIMITATION
 SET works only very low temperature around 4.2K, which is
practically Not possible.
 Out Side Environment Linking with SETs.
 For SET Ec~100Kb T, which in practice means sub-nanometer
island size for room temperature operation. In VLSI circuits, this
fabrication technology level is very difficult.
 Another problem is Co-tunneling. The pressure essence of the effect
is that the tunneling of several electrons through different barriers at
the same time is possible as a single coherent quantum mechanical
process. The rate of the process is crudely less than that for the
single electron tunneling.

27. FUTURE WORK
 Remove temperature problem and make SET workable in
room temperature.
 Developing SET-CMOS device for Bio-medical application like
Neuron Cell.
 Multi Dot SET Fabrication which is Easier to fabricate than
single dot device.
 Developing SET-CMOS processor for advance computing.
 Power gain improvement for SET can be evaluated under the
influence of parameters (CG, RTD, CTD, RTS and CTS).

28. SUMMERY
• Single Electron Transistor (SET) is an attractive candidate for future ultra
low power Nano-electronics.
• Though it has some intrinsic limitations like low current drive, lack of
room temperature operable technology etc, it is unlikely that SET can
replace the CMOS world near future.
• SETs can be exploited to increase CMOS functionalities by hybrid
CMOS-SET approach.
• SET-CMOS is one of the great architecture, which combines the virtues
of both devices. SET-CMOS exhibits many novel functionalities which
are very difficult to achieve by either of these technologies.

29. For any help or support please feel free to mail be at
sabbibalam123@gmail.com