1) CoolMOS CE is Infineon's optimized MOSFET platform for consumer applications, offering a best-in-class price to performance ratio.
2) CoolMOS CE uses Super Junction technology to reduce conduction and switching losses through a lower on-resistance and gate charge compared to standard MOSFETs.
3) Testing showed the CoolMOS CE provides higher efficiency, lower temperatures, and meets EMI standards in a 10W adapter compared to other MOSFETs.
The power semiconductor, in terms of its physical properties, requires a high breakdown voltage to turn off, a low on-state resistance to reduce static loss, and a fast switching speed to reduce dynamic loss. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. This addresses the fact that breakdown voltage and on-state resistance are in a trade-off relationship with a parameter of the doping concentration in the drift region. Such a trade-off relationship is a hindrance to the development of power semiconductor devices that have idealistic characteristics.
In this study, the Supejunction Insulated Gate Bipolar Transistor (SJ-IGBT) device that uses Superjunction drift layer, which makes it possible to increase the breakdown voltage without changing the on-state resistance. More specifically in the simulated IGBT structure, a drift layer consists from interleaving P-N columns, which results in an alleviation of the trade-off relationship between the on-state resistance and the breakdown voltage. The increase of breakdown voltage in the proposed SJ-IGBT structure has been analyzed both theoretically and through simulations. We report the simulation results 1200V Super Junction (SJ) IGBT, and discuss the Quasi 3D numerical simulation limits. The SJ IGBT demonstrated results shows remarkable trade-off performance Eoff vs. Vce(sat) and has high latch-up immunity. Such latch-up immunity conditioned high drift region doping density which is natural for SJ devices. Simulated structure is fully manufacturable, short circuit ruggedness and hot leakage current were taken into account.
Development and Deployment of Saturated-Core Fault Current Limiters in Distri...Franco Moriconi
Zenergy Power has been developing an inductive-type of fault current limiter (FCL) for electric power grid applications. The FCL employs a magnetically saturating reactor concept which acts as a variable inductor in an electric circuit. In March 2009 Zenergy Power, with funding from the California Energy Commission and the U.S. Department of Energy (DOE), installed an FCL in the Avanti distribution circuit of Southern California Edison’s Shandin substation in San Bernardino, CA. Rated at 15 kV and 1,250 amperes steady-state, the “Avanti” device is the first superconductor FCL installed in a US utility. In January 2010, the “Avanti” device successfully limited its first series of real-world faults when the circuit experienced multiple single-phase and three-phase faults. After successfully validating the performance of a new “compact” saturated-core FCL, Zenergy Power received contracts to install a 12 kV, 1,250 amperes compact FCL in the CE Electric UK grid in early 2011 and a 138 kV, 1,300 amperes FCL at the Tidd substation of American Electric Power in late 2011.
The power semiconductor, in terms of its physical properties, requires a high breakdown voltage to turn off, a low on-state resistance to reduce static loss, and a fast switching speed to reduce dynamic loss. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. This addresses the fact that breakdown voltage and on-state resistance are in a trade-off relationship with a parameter of the doping concentration in the drift region. Such a trade-off relationship is a hindrance to the development of power semiconductor devices that have idealistic characteristics.
In this study, the Supejunction Insulated Gate Bipolar Transistor (SJ-IGBT) device that uses Superjunction drift layer, which makes it possible to increase the breakdown voltage without changing the on-state resistance. More specifically in the simulated IGBT structure, a drift layer consists from interleaving P-N columns, which results in an alleviation of the trade-off relationship between the on-state resistance and the breakdown voltage. The increase of breakdown voltage in the proposed SJ-IGBT structure has been analyzed both theoretically and through simulations. We report the simulation results 1200V Super Junction (SJ) IGBT, and discuss the Quasi 3D numerical simulation limits. The SJ IGBT demonstrated results shows remarkable trade-off performance Eoff vs. Vce(sat) and has high latch-up immunity. Such latch-up immunity conditioned high drift region doping density which is natural for SJ devices. Simulated structure is fully manufacturable, short circuit ruggedness and hot leakage current were taken into account.
Development and Deployment of Saturated-Core Fault Current Limiters in Distri...Franco Moriconi
Zenergy Power has been developing an inductive-type of fault current limiter (FCL) for electric power grid applications. The FCL employs a magnetically saturating reactor concept which acts as a variable inductor in an electric circuit. In March 2009 Zenergy Power, with funding from the California Energy Commission and the U.S. Department of Energy (DOE), installed an FCL in the Avanti distribution circuit of Southern California Edison’s Shandin substation in San Bernardino, CA. Rated at 15 kV and 1,250 amperes steady-state, the “Avanti” device is the first superconductor FCL installed in a US utility. In January 2010, the “Avanti” device successfully limited its first series of real-world faults when the circuit experienced multiple single-phase and three-phase faults. After successfully validating the performance of a new “compact” saturated-core FCL, Zenergy Power received contracts to install a 12 kV, 1,250 amperes compact FCL in the CE Electric UK grid in early 2011 and a 138 kV, 1,300 amperes FCL at the Tidd substation of American Electric Power in late 2011.
101 series understanding copper cabling’s balancing actsmithponting
You have likely heard copper network cabling referred to as balanced twisted-pair copper cabling, and maybe you’ve heard of the testing parameter referred to as DC resistance unbalance. But what does all this balance-related terminology really mean, and why should you care?
Analysis and Control of Wind Driven Self-Excited Induction Generator for Isol...IDES Editor
For isolated applications, the 3- self-excited
induction generator driven by wind energy source is more
suitable, where the minimum excitation capacitance required
for self-excitation of 3- induction generator is taken up in
this work and the detailed analysis is carried out to determine
the range of wind speed variation and consumer demand for
the designed capacitance value. An electronic load controller
is designed to maintain the load voltage constant for these
variations. The excess power resulting as a consequence of
rise in load voltage due to variation in load is pumped to dump
load along with battery storage. Simulation for battery feeding
the consumer load in the absence of wind power has been
undergone. Exhaustive simulations have been carried out for
such a scheme and the results have been presented in this
paper.
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
Analsis of very fast transient over voltages in gas insulated substationseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Relong’s RC300C is commercial microwave and RF laminate
material designed with low dielectric constant and very low
loss characteristics. This ceramic-filled, woven fiberglass
reinforced PTFE composite material is use unique chemistry
formulation and processing to offer RF and Microwave
designers an advantage for improving electrical properties
and mechanical performances.RC300C provides a significant
improvement in performance stability over the current
product line and other traditional fluoropolymer-glass
laminates.
Relong’s RC300E is commercial microwave and RF laminate
material designed with low dielectric constant and very low
loss characteristics. This ceramic-filled, woven fiberglass
reinforced PTFE composite material is use unique chemistry
formulation and processing to offer RF and Microwave
designers an advantage for improving electrical properties
and mechanical performances.RC300E provides a significant
improvement in performance stability over the current
product line and other traditional fluoropolymer-glass
laminates.
A concept paper on "On Chip High Voltage generator using Polysilicon Diodestheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
Theoretical work submitted to the Journal should be original in its motivation or modeling structure. Empirical analysis should be based on a theoretical framework and should be capable of replication. It is expected that all materials required for replication (including computer programs and data sets) should be available upon request to the authors.
The International Journal of Engineering & Science would take much care in making your article published without much delay with your kind cooperation.
High Step-Up Converter with Voltage Multiplier Module for Renewable Energy Sy...IJRES Journal
In this project, A novel high step-up converter, which is suitable for renewable energy system, is proposed.Through a voltage multiplier module composed of switched capacitors and coupled inductors, a conventional interleaved boost converter obtains high step-up gain without operating at extreme duty ratio.The configuration of the proposed converter not only reduces the current stress but also constrains the input current ripple, which decreases the conduction losses and lengthens the lifetime of the input source. In addition, due to the lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large voltage spikes across the main switches are alleviated, and the efficiency is improved.
Design Simulation and Analysis of SET & SET-CMOS GatesSabbib Alam
Single Electron Transistor is the best candidate in the era of Nano-Technology because of its very low power consumption, high switching speed and super sensitivity. In this paper two types of logic gates design have been proposed using Single Electron Transistor and SET-CMOS hybrid single electron transistor. Monte Carlo Simulation Method has been used to simulate the gate operation because of its high accuracy in quantum level. Widely used software PSPICE also support Monte Carlo Method and also provide many library functions. Simulating through Monte Carlo Method gives a clear view of inner work for both Single Electron Transistor and Hybrid Single Electron Transistor Circuits.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
101 series understanding copper cabling’s balancing actsmithponting
You have likely heard copper network cabling referred to as balanced twisted-pair copper cabling, and maybe you’ve heard of the testing parameter referred to as DC resistance unbalance. But what does all this balance-related terminology really mean, and why should you care?
Analysis and Control of Wind Driven Self-Excited Induction Generator for Isol...IDES Editor
For isolated applications, the 3- self-excited
induction generator driven by wind energy source is more
suitable, where the minimum excitation capacitance required
for self-excitation of 3- induction generator is taken up in
this work and the detailed analysis is carried out to determine
the range of wind speed variation and consumer demand for
the designed capacitance value. An electronic load controller
is designed to maintain the load voltage constant for these
variations. The excess power resulting as a consequence of
rise in load voltage due to variation in load is pumped to dump
load along with battery storage. Simulation for battery feeding
the consumer load in the absence of wind power has been
undergone. Exhaustive simulations have been carried out for
such a scheme and the results have been presented in this
paper.
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
Analsis of very fast transient over voltages in gas insulated substationseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Relong’s RC300C is commercial microwave and RF laminate
material designed with low dielectric constant and very low
loss characteristics. This ceramic-filled, woven fiberglass
reinforced PTFE composite material is use unique chemistry
formulation and processing to offer RF and Microwave
designers an advantage for improving electrical properties
and mechanical performances.RC300C provides a significant
improvement in performance stability over the current
product line and other traditional fluoropolymer-glass
laminates.
Relong’s RC300E is commercial microwave and RF laminate
material designed with low dielectric constant and very low
loss characteristics. This ceramic-filled, woven fiberglass
reinforced PTFE composite material is use unique chemistry
formulation and processing to offer RF and Microwave
designers an advantage for improving electrical properties
and mechanical performances.RC300E provides a significant
improvement in performance stability over the current
product line and other traditional fluoropolymer-glass
laminates.
A concept paper on "On Chip High Voltage generator using Polysilicon Diodestheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
Theoretical work submitted to the Journal should be original in its motivation or modeling structure. Empirical analysis should be based on a theoretical framework and should be capable of replication. It is expected that all materials required for replication (including computer programs and data sets) should be available upon request to the authors.
The International Journal of Engineering & Science would take much care in making your article published without much delay with your kind cooperation.
High Step-Up Converter with Voltage Multiplier Module for Renewable Energy Sy...IJRES Journal
In this project, A novel high step-up converter, which is suitable for renewable energy system, is proposed.Through a voltage multiplier module composed of switched capacitors and coupled inductors, a conventional interleaved boost converter obtains high step-up gain without operating at extreme duty ratio.The configuration of the proposed converter not only reduces the current stress but also constrains the input current ripple, which decreases the conduction losses and lengthens the lifetime of the input source. In addition, due to the lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large voltage spikes across the main switches are alleviated, and the efficiency is improved.
Design Simulation and Analysis of SET & SET-CMOS GatesSabbib Alam
Single Electron Transistor is the best candidate in the era of Nano-Technology because of its very low power consumption, high switching speed and super sensitivity. In this paper two types of logic gates design have been proposed using Single Electron Transistor and SET-CMOS hybrid single electron transistor. Monte Carlo Simulation Method has been used to simulate the gate operation because of its high accuracy in quantum level. Widely used software PSPICE also support Monte Carlo Method and also provide many library functions. Simulating through Monte Carlo Method gives a clear view of inner work for both Single Electron Transistor and Hybrid Single Electron Transistor Circuits.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
High Step-Up Converter with Voltage Multiplier Module for Renewable Energy Sy...irjes
In this project, A novel high step-up converter, which is suitable for renewable energy system, is proposed.Through a voltage multiplier module composed of switched capacitors and coupled inductors, a conventional interleaved boost converter obtains high step-up gain without operating at extreme duty ratio.The configuration of the proposed converter not only reduces the current stress but also constrains the input current ripple, which decreases the conduction losses and lengthens the lifetime of the input source. In addition, due to the lossless passive clamp performance, leakage energy is recycled to the output terminal. Hence, large voltage spikes across the main switches are alleviated, and the efficiency is improved.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Integrated AC-DC Five Level Converter Strategy for Power Factor Corre...IJMTST Journal
Multilevel configuration has the advantage of its simplicity and modularity over the configurations of the other converters. With the application of multilevel converter in the high voltage and large power occasions in recent years, its modulation strategy has become a research hot point in the field of power electronics. The proposed power-factor-correction circuit can achieve unity power factor and ripple-free input current using a coupled inductor. The proposed rectifier can also produce input currents that do not have dead band regions and an output current that is continuous for all load conditions. The features of this converter are that it has lower input section peak current stresses and a better harmonic content than similar converter with a non-interleaved output, the output current is continuous for all load ranges, and the dc bus voltage is less than 450 for all line and load conditions. In this paper, the operation of the new converter is explained, its steady-state characteristics are determined by analysis, and these characteristics are used to develop a procedure for the design of the converter. Hence the simulation results are obtained using MATLAB/SIMULINK software. The proposed system provides a closed loop control for variable output voltage. The SSPFC AC/DC converter can operate with lower peak voltage stresses across the switches and the DC bus capacitors as it is a three-level converter. The proposed concept can be implemented with 5-level for efficient output voltage.
Abhijit Gurav presented the latest data we've collected on our BME Ceramic DC Link capacitor platform. These C0G ceramic capacitors are designed for high frequency and high-temperature DC Link applications. This update was presented at APEC 2017 in Tampa, FL.
As we see the switching frequency of power converters rise, there is a clear need for a high-frequency and high-temperature capacitor solution. Some designs are looking to place a relatively small ceramic capacitor right at the silicon. These requirements mean these capacitors must withstand temperatures as high as 200°C while responding to frequencies in the MHz range. KEMET's Ceramic DC Link capacitors are based on our very popular C0G platform.
Our Base Metal Electrode (BME) development provides designers two options. Capacitors based on the ultra-stable C0G dielectric or U2J dielectric. In this presentation, KEMET shows potential packages, capacitances, and rated voltages with these two technologies.
LOW VOLTAGE LOW DROPOUT REGULATOR USING CURRENT SPLITTING TECHNIQUEEditor IJMTER
We proposed a low voltage low dropout regulator that converts an input of 1 v to an
output of 0.85-0.5 v with 90-nm CMOS technology. Current splitting technique used to boost the
gain by using an error amplifier. A power noise cancellation mechanism is formed in the rail-to-rail
output stage of the error amplifier, to minimize the size of power MOS transistor. In this paper we
achieve a fast transient response, high power supply rejection, low dropout regulator, low voltage,
and small area. CMOS processes have been used in Large scale integrated circuits like LSI and
microprocessor they have been miniaturized constantly. Taking full advantage of the miniaturization
technology, CMOS linear regulators have become the power management ICs that are widely used in
portable electronics products to realize low profile, low dropout, and low supply current.
Universal demand for power increases due to continuous development to fulfil all these demand. Resources
are used with optimization. A high efficiency and high power factor converters are the major parts of energy
transfer system. This paper present a general review on single stage forward and flyback converter topologies to get
better its performance. This is paper presents a kind general idea of increasing efficiency and power factor of single
stage forward and fly back converter.
BP_2010_05_High Eff Low Profile ACDC Power_SMappus May 2010_Edit SM
coolmos-ce-goes-consumer
1. CoolMOS CE goes consumer
Srivatsa Raghunath, Infineon TechnologiesAuthor:
01/27/2016Date:
EMI / EMC, MOSFETs & Power MOSFETs, Thermal ManagementCategories:
Key criteria for designing power supplies units (PSU) for consumer applications are low cost, high efficiency,
good thermal performance and low Electro-Magnetic Interference (EMI). Starting with an optimal power
conversion topology assists the design process. Flyback topology is optimal for low and mid power PSUs. The
selection of a power switch, typically a MOSFET, plays a major role in realizing the product from design to
shipment. For high volume production, the benefit of a good quality MOSFET ensures low field failures.
For example, Infineon´s advanced Super Junction (SJ) principle based CoolMOS offers a significant reduction
in conduction and switching losses, with a low ON resistance and gate charge, key reasons behind this
performance. CoolMOS enables high power density and efficiency for advanced power conversion systems.
Additionally, it covers a wide spectrum of applications from lighting and consumer to telecom and computing.
Different CoolMOS series have been developed to cover a wide range of applications. CoolMOS CE is an
optimized platform for consumer applications; it offers a best-in-class price-to-performance ratio. After
launching the 500 V class in 2012, the CE technology is now also available in 600 V, 650 V, 700V, and 800 V.
The CoolMOS CE portfolio provides all benefits of a fast switching SJ MOSFET while retaining ease-of-use.
The CE series of MOSFETs achieve very low conduction and switching losses, making applications more
efficient, more compact, hence lighter and cooler.
CoolMOS CE is an optimized platform addressing and meeting consumer application needs as outlined in
Table 1.
Click image to enlarge
Table 1 Consumer application needs
Improving ON-state resistance
SJ technology helps to reduce the ON state resistance (RDS(on)) for high voltage MOSFETs through
specialized manufacturing capabilities. In conventional MOSFETs electrons flow through a high resistance N
channel, whereas in SJ technology they flow through a heavily doped n-region which lowers the value of
MOSFET use in low and mid power flyback topologies
2. RDS(on). The high voltage blocking is provided by adjacently placed P-columns which pass through the device
close to the n+ contact (see Figure 1).
Click image to enlarge
Figure 1a & b: Cross section of standard MOSFET and Super Junction MOSFET with typical MOSFET model
Improving switching speed
CoolMOS CE is based on SJ technology where the reduction in input and output capacitance results in lower
switching and driving losses. Because of this capacitance reduction the Eon and Eoff of the CE device is half
that of a standard MOSFET. Furthermore, the reduction of capacitance results in a reduced gate charge (Qg),
which gives the benefit of reduced driving losses and the ability to use lower drive currents.
Capacitance role in switching performance
A fundamental characteristic of SJ devices is that both the output and reverse capacitance show strong non-
linearity. The non-linearity in SJ capacitance characteristics comes from the fact that at a given voltage –
typically in the range of 1/10th of the rated blocking voltage – p- and n-columns deplete each other leading to
a fast expansion of the space charge layer throughout the structure.
This means that at a voltage beyond 50 V, for 500 V rated devices both output and reverse capacitance reach
minimum values of only a few pF. This is resulting in a dv/dt of more than 100 V/ns and di/dt of several
thousand A/μs if the load current is allowed to fully commute into the output capacitance during turn-off.
The voltage rise is therefore proportional to the load current and inversely proportional to the value of the
output capacitance (Coss). As Coss decreases as voltage rises, the highest dv/dt is reached shortly before
reaching the bus voltage. The corresponding di/dt is mainly limited by the inductance of the package and
printed circuit board (PCB). The highest efficiency can now be reached by turning-off the device in this
manner, because the switching losses can be reduced down to the level of the stored energy in the output
capacitance. All these benefits will be clearly visible in the efficiency performance.
CE devices have a smooth characteristic and show dv/dt of less than 70 V/ns and di/dt of less than 900 A/us
as shown in the pictures below. CE has a built in ease-of-use making it optimal for designers facing a short
time to market (see Figure 2)
3. Click image to enlarge
Figure 2: Comparison of CE switching characteristics
Key parameters: Gate charge (Qg)
One of the most important improvements is Qg reduction which brings benefits, especially in light load
conditions, due to reduced driving losses. CoolMOS CE has approximately 40 percent Qg reduction in
comparison to a similar standard MOSFET over the entire RDS(on) range. Figure 3 shows the Qg in
nanocoulombs (nC) of the 600 V CE against a standard MOSFET over the RDS(on) max range from 400 mΩ to
2100 mΩ.
Click image to enlarge
Figure 3: Qg comparison 600 V CE vs. standard MOSFET
Energy stored in output capacitance (Eoss)
The reduced energy stored in the output capacitance brings an important difference in hard switching
topologies and also reduces switching losses in a resonant topology. Normally it is possible to choose between
zero voltage switching (ZVS) or zero current switching (ZCS). In these two cases it is possible to eliminate the
4. turn-on losses (ZVS) or the turn-off losses (ZCS), but it is not possible to work in these two operation modes at
the same time.
Typically for MOSFETs the ZVS operation is preferred due to the usual important contribution of the output
capacitance to the turn-on losses (if hard switching). Therefore, one part of the switching losses is still always
present, and the reduction of Eoss brings a reduction of those switching losses. Figure 4 represents the Eoss
comparison between the 650 V CE and a comparable standard MOSFET of 1500 mΩ devices.
Click image to enlarge
Figure 4: Eoss comparison 650 V CE vs. standard MOSFET
The Eoss loss is in direct proportion to the output capacitance as a function of drain to source voltage (VDS) of
the MOSFET. In this case the effect of a reduction of Coss is very visible. One further benefit is a faster VDS
transition time in resonant topologies, which means that it is possible to reduce the resonant inductance and
circulating current loss, because it is possible to completely discharge the Coss with lower currents.
In order to show the performance results of CoolMOS CE in a flyback application a comparison is made
between CoolMOS CE and other MOSFETs.
In this measurement the 650 V CE is compared to a standard MOSFET in the 1.5 Ω RDS(on) range for a 10.6W
adapter (see Figure 5).
Click image to enlarge
Figure 5: 650 V CE vs. standard MOSFET efficiency difference comparison @ Vin = 90 VAC
Topology: Peak current controlled flyback
Vin = 90 VAC – 264 VAC
Vout = 5.3 VDC
Iout = 0 A to 2 A
Switching Frequency = 50 kHz @ full load
5. Ambient temperature = 25°C
Plug and play scenario between 650 V CoolMOS CE and standard MOSFET
High voltage MOSFET = IPS65R1K5CE
This plug and play measurement shows the benefit of a SJ MOSFET in comparison to a standard MOSFET in
terms of efficiency and thermal performance. Due to the Qg reduction of CoolMOS CE technology, better
average efficiency can be obtained. Thus high efficiency requirements can be easily achieved with this
CoolMOS CE
The thermal behavior of the power devices in an adapter application is very critical because it is difficult to
dissipate the heat generated by components due to very dense construction and high thermal resistance of
the casing. Therefore, power MOSFETs with improved switching losses will help in ensuring the device is
below the temperature limit. As presented in Figure 6, IPS65R1K5CE offers 5°C lower than the nearest
competitive device at low line (worst case). Furthermore, the design meets EMI specifications with sufficient
margin as shown in Figure 7.
Click image to enlarge
Figure 6: 650 V CE vs. standard MOSFET thermal comparison
Click image to enlarge
Figure 7: CoolMOS CE meets EMI QUASI-PEAK requirement
CoolMOS CE has proven to be a cost competitive MOSFET technology which is used to provide the good
efficiency needed for meeting environmental energy standards. Its lowest on resistance and low gate charge
help maintain the low thermal profiles needed for safety compliance. The integrated gate resistor for optimized
switching performance helps mitigate EMI problems arising due to less than optimal PCB layout. CE devices
come with a wide range of package options which enable sleek designs and have many ON resistance choices
to facilitate modular designs. With Infineon´s production capacity and quality record, the CoolMOS CE is
ideally suited for consumer applications.
Infineon Technologies