This document provides a guide to designing high-performance gate drive circuits for high-speed MOSFET switching applications. It discusses MOSFET technology and the gate drive requirements of power MOSFETs. The paper analyzes popular circuit solutions for gate drives and their performance. It describes design procedures for different types of gate drive circuits like ground referenced, high-side, AC coupled, and transformer isolated drives.

1. Design And Application Guide
For High Speed MOSFET Gate Drive Circuits
By Laszlo Balogh
ABSTRACT
The main purpose of this paper is to demonstrate a systematic approach to design high performance
gate drive circuits for high speed switching applications. It is an informative collection of topics offering
a “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest to
power electronics engineers at all levels of experience.
The most popular circuit solutions and their performance are analyzed, including the effect of parasitic
components, transient and extreme operating conditions. The discussion builds from simple to more
complex problems starting with an overview of MOSFET technology and switching operation. Design
procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated
solutions are described in great details. A special chapter deals with the gate drive requirements of the
MOSFETs in synchronous rectifier applications.
Several, step-by-step numerical design examples complement the paper.
INTRODUCTION
MOSFET – is an acronym for Metal Oxide sourcing and sinking sufficient current to provide
Semiconductor Field Effect Transistor and it is for fast insertion and extraction of the controlling
the key component in high frequency, high charge. From this point of view, the MOSFETs
efficiency switching applications across the have to be driven just as “hard” during turn-on
electronics industry. It might be surprising, but and turn-off as a bipolar transistor to achieve
FET technology was invented in 1930, some 20 comparable switching speeds. Theoretically, the
years before the bipolar transistor. The first switching speeds of the bipolar and MOSFET
signal level FET transistors were built in the late devices are close to identical, determined by the
1950’s while power MOSFETs have been time required for the charge carriers to travel
available from the mid 70’s. Today, millions of across the semiconductor region. Typical values
MOSFET transistors are integrated in modern in power devices are approximately 20 to 200
electronic components, from microprocessors, picoseconds depending on the size of the device.
through “discrete” power transistors. The popularity and proliferation of MOSFET
The focus of this topic is the gate drive technology for digital and power applications is
requirements of the power MOSFET in various driven by two of their major advantages over the
switch mode power conversion applications. bipolar junction transistors. One of these benefits
is the ease of use of the MOSFET devices in high
MOSFET TECHNOLOGY frequency switching applications. The MOSFET
The bipolar and the MOSFET transistors exploit transistors are simpler to drive because their
the same operating principle. Fundamentally, control electrode is isolated from the current
both type of transistors are charge controlled conducting silicon, therefore a continuous ON
devices which means that their output current is current is not required. Once the MOSFET
proportional to the charge established in the transistors are turned-on, their drive current is
semiconductor by the control electrode. When practically zero. Also, the controlling charge and
these devices are used as switches, both must be accordingly the storage time in the MOSFET
driven from a low impedance source capable of transistors is greatly reduced. This basically
1

2. eliminates the design trade-off between on state
voltage drop – which is inversely proportional to SOURCE
excess control charge – and turn-off time. As a
result, MOSFET technology promises to use GATE
much simpler and more efficient drive circuits n+ n+
with significant economic benefits compared to
p+ p+
bipolar devices.
Furthermore, it is important to highlight n- EPI layer
especially for power applications, that MOSFETs n+ Substrate DRAIN
have a resistive nature. The voltage drop across (a)
the drain source terminals of a MOSFET is a SOURCE
linear function of the current flowing in the
GATE
semiconductor. This linear relationship is n+ n+
characterized by the RDS(on) of the MOSFET and p p
known as the on-resistance. On-resistance is
constant for a given gate-to-source voltage and n- EPI layer
temperature of the device. As opposed to the n+ Substrate DRAIN
-2.2mV/°C temperature coefficient of a p-n (b)
junction, the MOSFETs exhibit a positive SOURCE
temperature coefficient of approximately
GATE DRAIN
0.7%/°C to 1%/°C. This positive temperature OXIDE
coefficient of the MOSFET makes it an ideal n+ n+
candidate for parallel operation in higher power p
n
applications where using a single device would p
not be practical or possible. Due to the positive Substrate
TC of the channel resistance, parallel connected (c)
MOSFETs tend to share the current evenly
among themselves. This current sharing works Figure 1. Power MOSFET device types
automatically in MOSFETs since the positive TC Double-diffused MOS transistors were
acts as a slow negative feedback system. The introduced in the 1970’s for power applications
device carrying a higher current will heat up and evolved continuously during the years. Using
more – don’t forget that the drain to source polycrystalline silicon gate structures and self-
voltages are equal – and the higher temperature aligning processes, higher density integration and
will increase its RDS(on) value. The increasing rapid reduction in capacitances became possible.
resistance will cause the current to decrease, The next significant advancement was offered by
therefore the temperature to drop. Eventually, an the V-groove or trench technology to further
equilibrium is reached where the parallel increase cell density in power MOSFET devices.
connected devices carry similar current levels. The better performance and denser integration
Initial tolerance in RDS(on) values and different don’t come free however, as trench MOS devices
junction to ambient thermal resistances can cause are more difficult to manufacture.
significant – up to 30% – error in current
distribution. The third device type to be mentioned here is the
lateral power MOSFETs. This device type is
Device types constrained in voltage and current rating due to
Almost all manufacturers have got their unique its inefficient utilization of the chip geometry.
twist on how to manufacture the best power Nevertheless, they can provide significant
MOSFETs, but all of these devices on the market benefits in low voltage applications, like in
can be categorized into three basic device types. microprocessor power supplies or as synchronous
These are illustrated in Figure 1. rectifiers in isolated converters.
2

3. The lateral power MOSFETs have significantly
lower capacitances, therefore they can switch
much faster and they require much less gate drive D
power.
MOSFET Models
There are numerous models available to illustrate G
how the MOSFET works, nevertheless finding
the right representation might be difficult. Most
of the MOSFET manufacturers provide Spice
and/or Saber models for their devices, but these
models say very little about the application traps
designers have to face in practice. They provide
even fewer clues how to solve the most common
S
design challenges. (a)
A really useful MOSFET model which would
describe all important properties of the device
from an application point of view would be very
complicated. On the other hand, very simple and
D
meaningful models can be derived of the
MOSFET transistor if we limit the applicability
of the model to certain problem areas. G
The first model in Figure 2 is based on the actual
structure of the MOSFET device and can be used
mainly for DC analysis. The MOSFET symbol in
Figure 2a represents the channel resistance and
the JFET corresponds to the resistance of the
epitaxial layer. The length, thus the resistance of S
the epi layer is a function of the voltage rating of
the device as high voltage MOSFETs require (b)
thicker epitaxial layer.
Figure 2b can be used very effectively to model
the dv/dt induced breakdown characteristic of a D
MOSFET. It shows both main breakdown
mechanisms, namely the dv/dt induced turn-on of
the parasitic bipolar transistor - present in all
power MOSFETs - and the dv/dt induced turn-on
of the channel as a function of the gate G
terminating impedance. Modern power
MOSFETs are practically immune to dv/dt
triggering of the parasitic npn transistor due to
manufacturing improvements to reduce the
resistance between the base and emitter regions.
It must be mentioned also that the parasitic S
bipolar transistor plays another important role. Its (c)
base – collector junction is the famous body
diode of the MOSFET. Figure 2. Power MOSFET models
3

4. Figure 2c is the switching model of the The CDS capacitor is also non-linear since it is the
MOSFET. The most important parasitic junction capacitance of the body diode. Its
components influencing switching performance voltage dependence can be described as:
are shown in this model. Their respective roles C DS,0
will be discussed in the next chapter which is C DS ≈
dedicated to the switching procedure of the K 2 ⋅ VDS
device. Unfortunately, non of the above mentioned
capacitance values are defined directly in the
MOSFET Critical Parameters
transistor data sheets. Their values are given
When switch mode operation of the MOSFET is indirectly by the CISS, CRSS, and COSS capacitor
considered, the goal is to switch between the values and must be calculated as:
lowest and highest resistance states of the device
in the shortest possible time. Since the practical C GD = C RSS
switching times of the MOSFETs (~10ns to 60ns) C GS = C ISS − C RSS
is at least two to three orders of magnitude longer C DS = C OSS − C RSS
than the theoretical switching time (~50ps to
200ps), it seems important to understand the Further complication is caused by the CGD
discrepancy. Referring back to the MOSFET capacitor in switching applications because it is
models in Figure 2, note that all models include placed in the feedback path between the input
three capacitors connected between the three and output of the device. Accordingly, its
terminals of the device. Ultimately, the switching effective value in switching applications can be
performance of the MOSFET transistor is much larger depending on the drain source
determined by how quickly the voltages can be voltage of the MOSFET. This phenomenon is
changed across these capacitors. called the “Miller” effect and it can be expressed
as:
Therefore, in high speed switching applications,
the most important parameters are the parasitic C GD,eqv = (1 + g fs ⋅ R L ) ⋅ C GD
capacitances of the device. Two of these Since the CGD and CDS capacitors are voltage
capacitors, the CGS and CGD capacitors dependent, the data sheet numbers are valid only
correspond to the actual geometry of the device at the test conditions listed. The relevant average
while the CDS capacitor is the capacitance of the capacitances for a certain application have to be
base collector diode of the parasitic bipolar calculated based on the required charge to
transistor (body diode). establish the actual voltage change across the
The CGS capacitor is formed by the overlap of the capacitors. For most power MOSFETs the
source and channel region by the gate electrode. following approximations can be useful:
Its value is defined by the actual geometry of the
VDS,spec
regions and stays constant (linear) under different C GD,ave = 2 ⋅ C RSS,spec ⋅
operating conditions. VDS,off
The CGD capacitor is the result of two effects. VDS,spec
Part of it is the overlap of the JFET region and C OSS,ave = 2 ⋅ C OSS,spec ⋅
the gate electrode in addition to the capacitance VDS,off
of the depletion region which is non-linear. The The next important parameter to mention is the
equivalent CGD capacitance is a function of the gate mesh resistance, RG,I. This parasitic
drain source voltage of the device approximated resistance describes the resistance associated by
by the following formula: the gate signal distribution within the device. Its
C GD,0 importance is very significant in high speed
C GD ≈ switching applications because it is in between
1 + K 1 ⋅ VDS
the driver and the input capacitor of the device,
directly impeding the switching times and the
4

5. dv/dt immunity of the MOSFET. This effect is Other important parameters like the source
recognized in the industry, where real high speed inductance (LS) and drain inductance (LD) exhibit
devices like RF MOSFET transistors use metal significant restrictions in switching performance.
gate electrodes instead of the higher resistance Typical LS and LD values are listed in the data
polysilicon gate mesh for gate signal distribution. sheets, and they are mainly dependant on the
The RG,I resistance is not specified in the data package type of the transistor. Their effects can
sheets, but in certain applications it can be a very be investigated together with the external
important characteristic of the device. In the back parasitic components usually associated with
of this paper, Appendix A4 shows a typical layout and with accompanying external circuit
measurement setup to determine the internal gate elements like leakage inductance, a current sense
resistor value with an impedance bridge. resistor, etc.
Obviously, the gate threshold voltage is also a For completeness, the external series gate resistor
critical characteristic. It is important to note that and the MOSFET driver’s output impedance
the data sheet VTH value is defined at 25°C and at must be mentioned as determining factors in high
a very low current, typically at 250μA. performance gate drive designs as they have a
Therefore, it is not equal to the Miller plateau profound effect on switching speeds and
region of the commonly known gate switching consequently on switching losses.
waveform. Another rarely mentioned fact about
VTH is its approximately –7mV/°C temperature SWITCHING APPLICATIONS
coefficient. It has particular significance in gate Now, that all the players are identified, let’s
drive circuits designed for logic level MOSFET investigate the actual switching behavior of the
where VTH is already low under the usual test MOSFET transistors. To gain a better
conditions. Since MOSFETs usually operate at understanding of the fundamental procedure, the
elevated temperatures, proper gate drive design parasitic inductances of the circuit will be
must account for the lower VTH when turn-off neglected. Later their respective effects on the
time, and dv/dt immunity is calculated as shown basic operation will be analyzed individually.
in Appendix A and F. Furthermore, the following descriptions relate to
The transconductance of the MOSFET is its clamped inductive switching because most
small signal gain in the linear region of its MOSFET transistors and high speed gate drive
operation. It is important to point out that every circuits used in switch mode power supplies work
time the MOSFET is turned-on or turned-off, it in that operating mode.
must go through its linear operating mode where
the current is determined by the gate-to-source IDC
voltage. The transconductance, gfs, is the small
signal relationship between drain current and
gate-to-source voltage:
dI RGATE
g fs = D
dVGS
Accordingly, the maximum current of the
MOSFET in the linear region is given by:
VOUT
I D = (VGS − Vth ) ⋅ g fs VDRV
Rearranging this equation for VGS yields the
approximate value of the Miller plateau as a
function of the drain current.
I
VGS,Miller = Vth + D Figure 3. Simplified clamped inductive switching
g fs
model
5

6. The simplest model of clamped inductive This period is called the turn-on delay, because
switching is shown in Figure 3, where the DC both the drain current and the drain voltage of the
current source represents the inductor. Its current device remain unchanged.
can be considered constant during the short Once the gate is charged to the threshold level,
switching interval. The diode provides a path for the MOSFET is ready to carry current. In the
the current during the off time of the MOSFET second interval the gate is rising from VTH to the
and clamps the drain terminal of the device to the Miller plateau level, VGS,Miller. This is the linear
output voltage symbolized by the battery. operation of the device when current is
proportional to the gate voltage. On the gate side,
Turn-On procedure
current is flowing into the CGS and CGD
The turn-on event of the MOSFET transistor can capacitors just like in the first time interval and
be divided into four intervals as depicted in the VGS voltage is increasing. On the output side
Figure 4. of the device, the drain current is increasing,
V D RV while the drain-to-source voltage stays at the
ID
D previous level (VDS,OFF). This can be understood
C GD looking at the schematic in Figure 3. Until all the
R HI R G A TE
G
R G ,I
C DS
current is transferred into the MOSFET and the
IG diode is turned-off completely to be able to block
CGS
reverse voltage across its pn junction, the drain
S
voltage must stay at the output voltage level.
Entering into the third period of the turn-on
procedure the gate is already charged to the
VGS
sufficient voltage (VGS,Miller) to carry the entire
load current and the rectifier diode is turned off.
That now allows the drain voltage to fall. While
VTH
the drain voltage falls across the device, the gate-
IG
to-source voltage stays steady. This is the Miller
plateau region in the gate voltage waveform. All
the gate current available from the driver is
diverted to discharge the CGD capacitor to
V DS
facilitate the rapid voltage change across the
drain-to-source terminals. The drain current of
the device stays constant since it is now limited
by the external circuitry, i.e. the DC current
ID source.
The last step of the turn-on is to fully enhance the
conducting channel of the MOSFET by applying
a higher gate drive voltage. The final amplitude
1 2 3 4 of VGS determines the ultimate on-resistance of
the device during its on-time. Therefore, in this
Figure 4. MOSFET turn-on time intervals fourth interval, VGS is increased from VGS,Miller to
In the first step the input capacitance of the its final value, VDRV. This is accomplished by
device is charged from 0V to VTH. During this charging the CGS and CGD capacitors, thus gate
interval most of the gate current is charging the current is now split between the two components.
CGS capacitor. A small current is flowing through While these capacitors are being charged, the
the CGD capacitor too. As the voltage increases at drain current is still constant, and the drain-to-
the gate terminal and the CGD capacitor’s voltage source voltage is slightly decreasing as the on-
has to be slightly reduced. resistance of the device is being reduced.
6

7. Turn-Off procedure
The description of the turn-off procedure for the In the second period, the drain-to-source voltage
MOSFET transistor is basically back tracking the of the MOSFET rises from ID⋅RDS(on) to the final
turn-on steps from the previous section. Start VDS(off) level, where it is clamped to the output
with VGS being equal to VDRV and the current in voltage by the rectifier diode according to the
the device is the full load current represented by simplified schematic of Figure 3. During this
IDC in Figure 3. The drain-to-source voltage is time period – which corresponds to the Miller
being defined by IDC and the RDS(on) of the plateau in the gate voltage waveform - the gate
MOSFET. The four turn-off steps are shown in current is strictly the charging current of the CGD
Figure 5. for completeness. capacitor because the gate-to-source voltage is
V DRV
constant. This current is provided by the bypass
D
ID capacitor of the power stage and it is subtracted
CGD
from the drain current. The total drain current
R LO R G ATE R G,I still equals the load current, i.e. the inductor
current represented by the DC current source in
G C DS
Figure 3.
IG
C GS
S The beginning of the third time interval is
signified by the turn-on of the diode, thus
providing an alternative route to the load current.
The gate voltage resumes falling from VGS,Miller to
V GS
VTH. The majority of the gate current is coming
out of the CGS capacitor, because the CGD
V TH
capacitor is virtually fully charged from the
previous time interval. The MOSFET is in linear
IG
operation and the declining gate-to-source
voltage causes the drain current to decrease and
reach near zero by the end of this interval.
Meanwhile the drain voltage is steady at VDS(off)
V DS due to the forward biased rectifier diode.
The last step of the turn-off procedure is to fully
discharge the input capacitors of the device. VGS
is further reduced until it reaches 0V. The bigger
ID
portion of the gate current, similarly to the third
turn-off time interval, supplied by the CGS
capacitor. The drain current and the drain voltage
in the device are unchanged.
1 2 3 4
Summarizing the results, it can be concluded that
the MOSFET transistor can be switched between
Figure 5. MOSFET turn-off time intervals its highest and lowest impedance states (either
The first time interval is the turn-off delay which turn-on or turn-off) in four time intervals. The
is required to discharge the CISS capacitance from lengths of all four time intervals are a function of
its initial value to the Miller plateau level. the parasitic capacitance values, the required
During this time the gate current is supplied by voltage change across them and the available gate
the CISS capacitor itself and it is flowing through drive current. This emphasizes the importance of
the CGS and CGD capacitors of the MOSFET. The the proper component selection and optimum
drain voltage of the device is slightly increasing gate drive design for high speed, high frequency
as the overdrive voltage is diminishing. The switching applications.
current in the drain is unchanged.
7

8. Characteristic numbers for turn-on, turn-off This graph gives a relatively accurate worst case
delays, rise and fall times of the MOSFET estimate of the gate charge as a function of the
switching waveforms are listed in the transistor gate drive voltage. The parameter used to
data sheets. Unfortunately, these numbers generate the individual curves is the drain-to-
correspond to the specific test conditions and to source off state voltage of the device. VDS(off)
resistive load, making the comparison of different influences the Miller charge – the area below the
manufacturers’ products difficult. Also, flat portion of the curves – thus also, the total
switching performance in practical applications gate charge required in a switching cycle. Once
with clamped inductive load is significantly the total gate charge is obtained from Figure 6,
different from the numbers given in the data the gate charge losses can be calculated as:
sheets. PGATE = VDRV ⋅ Q G ⋅ f DRV
Power losses where VDRV is the amplitude of the gate drive
The switching action in the MOSFET transistor waveform and fDRV is the gate drive frequency –
in power applications will result in some which is in most cases equal to the switching
unavoidable losses, which can be divided into frequency. It is interesting to notice that the
two categories. QG⋅fDRV term in the previous equation gives the
The simpler of the two loss mechanisms is the average bias current required to drive the gate.
gate drive loss of the device. As described before, The power lost to drive the gate of the MOSFET
turning-on or off the MOSFET involves charging transistor is dissipated in the gate drive circuitry.
or discharging the CISS capacitor. When the Referring back to Figures 4 and 5, the dissipating
voltage across a capacitor is changing, a certain components can be identified as the combination
amount of charge has to be transferred. The of the series ohmic impedances in the gate drive
amount of charge required to change the gate path. In every switching cycle the required gate
voltage between 0V and the actual gate drive charge has to pass through the driver output
voltage VDRV, is characterized by the typical gate impedances, the external gate resistor, and the
charge vs. gate-to-source voltage curve in the internal gate mesh resistance. As it turns out, the
MOSFET datasheet. An example is shown in power dissipation is independent of how quickly
Figure 6. the charge is delivered through the resistors.
Using the resistor designators from Figures 4 and
5, the driver power dissipation can be expressed
Vgs, Gate-to-Source Voltage (V)
as:
1 R ⋅V ⋅Q ⋅f
PDRV,ON = ⋅ HI DRV G DRV
2 R HI + R GATE + R G,I
VDRV
1 R LO ⋅ VDRV ⋅ Q G ⋅ f DRV
PDRV,OFF = ⋅
2 R LO + R GATE + R G,I
PDRV = PDRV,ON + PDRV,OFF
In the above equations, the gate drive circuit is
VDS
represented by a resistive output impedance and
this assumption is valid for MOS based gate
QG drivers. When bipolar transistors are utilized in
the gate drive circuit, the output impedance
becomes non-linear and the equations do not
Qg, Total Gate Charge (nC) yield the correct answers. It is safe to assume that
with low value gate resistors (<5Ω) most gate
Figure 6. Typical gate charge vs. gate-to-source drive losses are dissipated in the driver. If RGATE
voltage is sufficiently large to limit IG below the output
8

9. current capability of the bipolar driver, the drain voltage changes from VDS(off) to 0V, the
majority of the gate drive power loss is then approximate switching times are given as:
dissipated in RGATE. V − VTH
In addition to the gate drive power loss, the t2 = C ISS ⋅ GS,Miller
I G2
transistors accrue switching losses in the
traditional sense due to high current and high VDS,off
t3 = C RSS ⋅
voltage being present in the device I G3
simultaneously for a short period. In order to During t2 the drain voltage is VDS(off) and the
ensure the least amount of switching losses, the current is ramping from 0A to the load current, IL
duration of this time interval must be minimized. while in t3 time interval the drain voltage is
Looking at the turn-on and turn-off procedures of falling from VDS(off) to near 0V. Again, using
the MOSFET, this condition is limited to linear approximations of the waveforms, the
intervals 2 and 3 of the switching transitions in power loss components for the respective time
both turn-on and turn-off operation. These time
intervals can be estimated:
intervals correspond to the linear operation of the
device when the gate voltage is between VTH and t2 I
P2 = ⋅ VDS,off ⋅ L
VGS,Miller, causing changes in the current of the T 2
device and to the Miller plateau region when the t3 VDS,off
drain voltage goes through its switching P3 = ⋅ ⋅ IL
T 2
transition.
where T is the switching period. The total
This is a very important realization to properly switching loss is the sum of the two loss
design high speed gate drive circuits. It highlights components, which yields the following
the fact that the most important characteristic of simplifed expression:
the gate driver is its source-sink current
capability around the Miller plateau voltage level. VDS(off) ⋅ I L t2 + t3
PSW = ⋅
Peak current capability, which is measured at full 2 T
VDRV across the driver’s output impedance, has Even though the switching transitions are well
very little relevance to the actual switching understood, calculating the exact switching losses
performance of the MOSFET. What really is almost impossible. The reason is the effect of
determines the switching times of the device is the parasitic inductive components which will
the gate drive current capability when the gate-to- significantly alter the current and voltage
source voltage, i.e. the output of the driver is at waveforms, as well as the switching times during
~5V (~2.5V for logic level MOSFETs). the switching procedures. Taking into account the
A crude estimate of the MOSFET switching effect of the different source and drain
losses can be calculated using simplified linear inductances of a real circuit would result in
approximations of the gate drive current, drain second order differential equations to describe
current and drain voltage waveforms during the actual waveforms of the circuit. Since the
periods 2 and 3 of the switching transitions. First variables, including gate threshold voltage,
the gate drive currents must be determined for the MOSFET capacitor values, driver output
second and third time intervals respectively: impedances, etc. have a very wide tolerance, the
above described linear approximation seems to
V − 0.5 ⋅ (VGS,Miller + VTH ) be a reasonable enough compromise to estimate
I G2 = DRV
R HI + R GATE + R G.I switching losses in the MOSFET.
VDRV − VGS,Miller
I G3 = Effects of parasitic components
R HI + R GATE + R G.I The most profound effect on switching
Assuming that IG2 charges the input capacitor of performance is exhibited by the source
the device from VTH to VGS,Miller and IG3 is the inductance. There are two sources for parasitic
discharge current of the CRSS capacitor while the source inductance in a typical circuit, the source
9

10. bond wire neatly integrated into the MOSFET Smaller resistor values will result an overshoot in
package and the printed circuit board wiring the gate drive voltage waveform, but also result
inductance between the source lead and the in faster turn-on speed. Higher resistor values
common ground. This is usually referenced as the will underdamp the oscillation and extend the
negative electrode of the high frequency filter switching times without offering any benefit for
capacitor around the power stage and the bypass the gate drive design.
capacitor of the gate driver. Current sense The second effect of the source inductance is a
resistors in series with the source can add negative feedback whenever the drain current of
additional inductance to the previous two the device is changing rapidly. This effect is
components. present in the second time interval of the turn-on
There are two mechanisms in the switching and in the third time interval of the turn-off
procedure which involve the source inductor. At procedure. During these periods the gate voltage
the beginning of the switching transitions the gate is between VTH and VGS,Miller, and the gate current
current is increasing very rapidly as illustrated in is defined by the voltage across the drive
Figures 4 and 5. This current must flow through impedance, VDRV-VGS. In order to increase the
the source inductance and will be slowed down drain current quickly, significant voltage has to
based on the inductor value. Consequently, the be applied across the source inductance. This
time required to charge/discharge the input voltage reduces the available voltage across the
capacitance of the MOSFET gets longer, mainly drive impedance, thus reduces the rate of change
influencing the turn-on and turn-off delays (step in the gate drive voltage which will result in a
1). Furthermore, the source inductor and the CISS lower di/dt of the drain current. The lower di/dt
capacitor form a resonant circuit as shown in requires less voltage across the source
Figure 7. inductance. A delicate balance of gate current
and drain di/dt is established through the negative
feedback by the source inductor.
RG LS The other parasitic inductance of the switching
CISS network is the drain inductance which is again
VDRV composed of several components. They are the
packaging inductance inside the transistor
package, all the inductances associated with
interconnection and the leakage inductance of a
transformer in isolated power supplies. Their
Figure 7. Gate drive resonant circuit components effect can be lumped together since they are in
The resonant circuit is exited by the steep edges series with each other. They act as a turn-on
of the gate drive voltage waveform and it is the snubber for the MOSFET. During turn-on they
fundamental reason for the oscillatory spikes limit the di/dt of the drain current and reduce the
observed in most gate drive circuits. Fortunately, drain-to-source voltage across the device by the
the otherwise very high Q resonance between factor of LD⋅di/dt. In fact, LD can reduce the turn-
CISS and LS is damped or can be damped by the on switching losses significantly. While higher
series resistive components of the loop which LD values seem beneficial at turn-on, they cause
include the driver output impedance, the external considerable problems at turn-off when the drain
gate resistor, and the internal gate mesh resistor. current must ramp down quickly. To support the
The only user adjustable value, RGATE, can be rapid reduction in drain current due to the turn-
calculated for optimum performance by: off of the MOSFET, a voltage in the opposite
direction with respect to turn-on must be across
LS
R GATE,OPT = 2 ⋅ − (R DRV + R G,I ) LD. This voltage is above the theoretical VDS(off)
C ISS level, producing an overshoot in the drain-to-
source voltage and an increase in turn-off
switching losses.
10

11. Accurate mathematical analysis of the complete Another limiting factor for MOSFET die size
switching transitions including the effects of with direct gate drive is the power dissipation of
parasitic inductances are available in the the driver within the controller. An external gate
literature but points beyond the scope of this resistor can mitigate this problem as discussed
paper. before. When direct gate drive is absolutely
necessary for space and/or cost savings, special
GROUND REFERENCED GATE considerations are required to provide appropriate
DRIVE bypassing for the controller. The high current
spikes driving the gate of the MOSFET can
PWM Direct drive disrupt the sensitive analog circuitry inside the
In power supply applications, the simplest way of PWM controller. As MOSFET die size increases,
driving the gate of the main switching transistor so too does gate charge required. The selection of
is to utilize the gate drive output of the PWM the proper bypass capacitor calls for a little bit
controller as shown in Figure 8. more scientific approach than picking the usual
0.1μF or 1μF bypass capacitor.
VDRV (VBIAS)
Sizing the bypass capacitor
In this chapter the calculation of the MOSFET
VCC gate driver’s bypass capacitor is demonstrated.
PWM This capacitor is the same as the PWM
controller RGATE controller’s bypass capacitor in direct gate drive
OUT application because that is the capacitor which
provides the gate drive current at turn-on. In case
of a separate driver circuit, whether a gate drive
GND IC or discrete solution, this capacitor must be
distance!
placed close, preferably directly across the bias
and ground connection of the driver.
There are two current components to consider.
Figure 8. Direct gate drive circuit One is the quiescent current which can change by
The most difficult task in direct gate drives is to a 10x factor based on the input state of some
optimize the circuit layout. As indicated in Figure integrated drivers. This itself will cause a duty
8, there might be considerable distance between cycle dependent ripple across the bypass
the PWM controller and the MOSFET. This capacitor which can be calculated as:
distance introduces a parasitic inductance due to I ⋅D
the loop formed by the gate drive and ground ΔVQ = Q,HI MAX
C DRV ⋅ f DRV
return traces which can slow down the switching
speed and can cause ringing in the gate drive where it is assumed that the driver’s quiescent
waveform. Even with a ground plane, the current is higher when its input is driven high.
inductance can not be completely eliminated The other ripple component is the gate current.
since the ground plane provides a low inductance Although the actual current amplitude is not
path for the ground return current only. To reduce know in most cases, the voltage ripple across the
the inductance linked to the gate drive bypass capacitor can be determined based on the
connection, a wider PCB trace is desirable. value of the gate charge. At turn-on, this charge
Another problem in direct gate drive is the is taken out of the bypass capacitor and
limited drive current capability of the PWM transferred to the MOSFET input capacitor.
controllers. Very few integrated circuits offer Accordingly the ripple is given by:
more than 1A peak gate drive capability. This
Q
will limit the maximum die size which can be ΔVQG = G
driven at a reasonable speed by the controller. C DRV
11

12. Using the principle of superposition and solving drop Schottky diodes are generally needed to
the equations for CDRV, the bypass capacitor protect the outputs. The diodes must be placed
value for a tolerable ripple voltage (ΔV) can be very close to the output pin and to the bypass
found: capacitor of the driver. It is important to point out
D also, that the diodes protect the driver only, they
I Q,HI ⋅ MAX + Q G are not clamping the gate-to-source voltage
f DRV against excessive ringing especially with direct
C DRV =
ΔV drive where the control IC might be far away
where IQ,HI is the quiescent current of the driver from the gate-source terminals of the MOSFET.
when its input is driven high, DMAX is the
maximum duty cycle of the driver while the input Bipolar totem-pole driver
can stay high, fDRV is the operating frequency of One of the most popular and cost effective drive
the driver, and QG is the total gate charge based circuit for driving MOSFETs is a bipolar, non-
on the amplitude of the gate drive and drain-to- inverting totem-pole driver as shown in Figure
source off state voltages. 10.
Driver protection VBIAS VDRV
Another must-do with direct drive and with gate R
drive ICs using bipolar output stage is to provide VCC
suitable protection for the output bipolar PWM
transistors against reverse currents. As indicated controller RGATE
in the simplified diagram in Figure 9, the output OUT
stage of the integrated bipolar drivers is built RB
from npn transistors due to their more efficient
area utilization and better performance.
GND
VDRV distance!
PWM or VCC
Driver IC Figure 10. Bipolar totem-pole MOSFET driver
Like all external drivers, this circuit handles the
OUT RGATE current spikes and power losses making the
operating conditions for the PWM controller
more favorable. Of course, they can be and
should be placed right next to the power
MOSFET they are driving. That way the high
GND current transients of driving the gate are localized
in a very small loop area, reducing the value of
Figure 9. Gate drive with integrated bipolar parasitic inductances. Even though the driver is
transistors built from discrete components, it needs its own
bypass capacitor placed across the collectors of
The npn transistors can handle currents in one the upper npn and the lower pnp transistors.
direction only. The high side npn can source but Ideally there is a smoothing resistor or inductor
can not sink current while the low side is exactly between the bypass capacitor of the driver and
the opposite. Unavoidable oscillations between the bypass capacitor of the PWM controller for
the source inductor and the input capacitor of the increased noise immunity. The RGATE resistor of
MOSFET during turn-on and turn-off necessitate Figure 10 is optional and RB can be sized to
that current should be able to flow in both provide the required gate impedance based on the
directions at the output of the driver. To provide large signal beta of the driver transistors.
a path for reverse currents, low forward voltage
12

13. An interesting property of the bipolar totem-pole Speed enhancement circuits
driver that the two base-emitter junctions protect When speed enhancement circuits are mentioned
each other against reverse breakdown. designers exclusively consider circuits which
Furthermore, assuming that the loop area is really speed-up the turn-off process of the MOSFET.
small and RGATE is negligible, they can clamp the The reason is that the turn-on speed is usually
gate voltage between VBIAS+VBE and GND-VBE limited by the turn-off, or reverse recovery speed
using the base-emitter diodes of the transistors. of the rectifier component in the power supply.
Another benefit of this solution, based on the As discussed with respect to the inductive
same clamp mechanism, is that the npn-pnp clamped model in Figure 3, the turn-on of the
totem-pole driver does not require any Schottky MOSFET coincides with the turn-off of the
diode for reverse current protection. rectifier diode. Therefore, the fastest switching
action is determined by the reverse recovery
MOSFET totem-pole driver
characteristic of the diode, not by the strength of
The MOSFET equivalent of the bipolar totem- the gate drive circuit. In an optimum design the
pole driver is pictured in Figure 11. All the gate drive speed at turn-on is matched to the
benefits mentioned about the bipolar totem-pole diode switching characteristic. Considering also
driver are equally applicable to this that the Miller region is closer to GND than to
implementation. the final gate drive voltage VDRV, a higher
VBIAS VDRV
voltage can be applied across the driver output
impedance and the gate resistor. Usually the
R obtained turn-on speed is sufficient to drive the
VCC MOSFET.
PWM The situation is vastly different at turn-off. In
controller RGATE theory, the turn-off speed of the MOSFET
OUT depends only on the gate drive circuit. A higher
current turn-off circuit can discharge the input
capacitors quicker, providing shorter switching
GND times and consequently lower switching losses.
The higher discharge current can be achieved by
distance! a lower output impedance MOSFET driver
and/or a negative turn-off voltage in case of the
Figure 11. MOSFET based totem-pole driver common N-channel device. While faster
Unfortunately, this circuit has several drawbacks switching can potentially lower the switching
compared to the bipolar version which explain losses, the turn-off speed-up circuits increase the
that it is very rarely implemented discretely. The ringing in the waveforms due to the higher turn-
circuit of Figure 11 is an inverting driver, off di/dt and dv/dt of the MOSFET. This is
therefore the PWM output signal must be something to consider in selecting the proper
inverted. In addition, the suitable MOSFET voltage rating and EMI containment for the
transistors are more expensive than the bipolar power device.
ones and they will have a large shoot through Turn-off diode
current when their common gate voltage is in
The following examples of turn-off circuits are
transition. This problem can be circumvented by
demonstrated on simple ground referenced gate
additional logic or timing components which
drive circuits, but are equally applicable to other
technique is extensively used in IC
implementations discussed later in the paper. The
implementations.
simplest technique is the anti-parallel diode, as
shown in Figure 12.
13

14. VDRV VDRV
VCC VCC
DON
Driver Driver
RGATE RGATE
OUT OUT QOFF
DOFF
GND GND
Figure 12. Simple turn-off speed enhancement Figure 13. Local pnp turn-off circuit
circuit
The turn-off current does not go back to the
In this circuit RGATE allows adjustment of the driver, it does not cause ground bounce problems
MOSFET turn-on speed. During turn-off the anti- and the power dissipation of the driver is reduced
parallel diode shunts out the resistor. DOFF works by a factor of two. The turn-off transistor shunts
only when the gate current is higher than: out the gate drive loop inductance, the potential
V current sense resistor, and the output impedance
I G > D,FWD of the driver. Furthermore, QOFF never saturates
R GATE
which is important to be able to turn it on and off
typically around 150mA using a 1N4148 and quickly. Taking a closer look at the circuit
around 300mA with a BAS40 Schottky anti- reveals that this solution is a simplified bipolar
parallel diode. Consequently, as the gate-to- totem-pole driver, where the npn pull-up
source voltage approaches 0V the diode helps transistor is replaced by a diode. Similarly to the
less and less. As a result, this circuit will provide totem-pole driver, the MOSFET gate is clamped
a significant reduction in turn-off delay time, but by the turn-off circuit between GND-0.7V and
only incremental improvement on switching VDRV+0.7V approximately, eliminating the risk
times and dv/dt immunity. Another disadvantage of excessive voltage stress at the gate. The only
is that the gate turn-off current still must flow known shortcoming of the circuit is that it can not
through the driver’s output impedance. pull the gate all the way to 0V because of the
voltage drop across the base-emitter junction of
PNP turn-off circuit QOFF.
Undoubtedly the most popular arrangement for
fast turn-off is the local pnp turn-off circuit of NPN turn-off circuit
Figure 13. With the help of QOFF, the gate and the The next circuit to examine is the local npn turn-
source are shorted locally at the MOSFET off circuit, illustrated in Figure 14. Similarly to
terminals during turn-off. RGATE limits the turn- the pnp solution, the gate discharge current is
on speed, and DON provides the path for the turn- well localized. The npn transistor holds the gate
on current. Also, DON protects the base-emitter closer to GND than its pnp counterpart. Also, this
junction of QOFF against reverse breakdown at the implementation provides a self biasing
beginning of the turn-on procedure. mechanism to keep the MOSFET off during
The most important advantage of this solution is power up.
that the high peak discharge current of the Unfortunately, this circuit has some significant
MOSFET input capacitance is confined in the drawbacks. The npn turn-off transistor, QOFF is an
smallest possible loop between the gate, source inverting stage, it requires an inverted PWM
and collector, emitter connections of the two signal provided by QINV.
transistors.
14

15. to the CISS capacitance of the main power
VDRV MOSFET. This will increase the effective “Total
Gate Charge” the driver has to provide. Also to
VCC DON consider, the gate of the main MOSFET is
floating before the outputs of the driver IC
Driver becomes intelligent during power up.
RGATE
OUT QOFF dv/dt protection
There are two situations when the MOSFET has
QINV
to be protected against dv/dt triggered turn-on.
GND One is during power up where protection can
usually be provided by a resistor between the
gate and source terminals of the device. The pull
Figure 14. Local npn self biasing turn-off circuit down resistor value depends on the worst case
dv/dt of the power rail during power up
The inverter draws current from the driver during
according to:
the on time of the MOSFET, lowering the
efficiency of the circuit. Furthermore, QINV VTH ⎛ dt ⎞
RGS < ⋅⎜ ⎟
saturates during the on-time which can prolong CGD ⎝ dv ⎠TURN −ON
turn-off delay in the gate drive. In this calculation the biggest challenge is to find
NMOS turn-off circuit the highest dv/dt which can occur during power
up and provide sufficient protection for that
An improved, lower parts count implementation
particular dv/dt.
of this principle is offered in Figure 15, using a
dual driver to provide the inverted PWM signal The second situation is in normal operation when
for a small N-channel discharge transistor. turn-off dv/dt is forced across the drain-to-source
terminals of the power switch while it is off. This
VDRV situation is more common than one may
originally anticipate. All synchronous rectifier
switches are operated in this mode as will be
VCC discussed later. Most resonant and soft switching
RGATE
converters can force a dv/dt across the main
OUT
switch right after its turn-off instance, driven by
Driver the resonant components of the power stage.
OUT QOFF Since these dv/dt’s are significantly higher than
during power up and VTH is usually lower due to
GND the higher operating junction temperature,
protection must be provided by the low output
impedance of the gate drive circuit.
Figure 15. Improved N-channel MOS based turn- The first task is to determine the maximum dv/dt
off circuit which can occur under worst case conditions.
The next step in evaluating the suitability of a
This circuit offers very fast switching and particular device to the application is to calculate
complete discharge of the MOSFET gate to 0V. its natural dv/dt limit, imposed by the internal
RGATE sets the turn-on speed like before, but is gate resistance and the CGD capacitance of the
also utilized to prevent any shoot through MOSFET. Assuming ideal (zero Ohm) external
currents between the two outputs of the driver in drive impedance the natural dv/dt limit is:
case of imperfect timing of the drive signals.
Another important fact to consider is that the dv V − 0.007 ⋅ (TJ − 25)
= TH
COSS capacitance of QOFF is connected in parallel dt LIMIT R G,I ⋅ C GD
15

16. where VTH is the gate threshold at 25°C, -0.007 is voltage outputs of the power supplies instead of
the temperature coefficient of VTH, RG,I is the rectifier diodes. They usually work with a very
internal gate mesh resistance and CGD is the gate- limited drain-to-source voltage swing, therefore,
to-drain capacitor. If the natural dv/dt limit of the their CDS and CGD capacitors exhibit relatively
MOSFET is lower than the maximum dv/dt of large capacitance values. Moreover, their
the resonant circuit, either a different MOSFET application is unique because these devices are
or a negative gate bias voltage must be operated in the fourth quadrant of their V-I plane.
considered. If the result is favorable for the The current is flowing from the source toward the
device, the maximum gate drive impedance can drain terminal. That makes the gate drive signal
be calculated by rearranging and solving the kind of irrelevant. If the circumstances, other
previous equation according to: components around the synchronous switch
VTH − 0.007 ⋅ (TJ − 25) ⎛ dt ⎞ require, current will flow in the device, either
R MAX = ⋅⎜ ⎟ through the resistive channel or through the
C GD ⎝ dv ⎠ MAX parasitic body diode of the MOSFET. The easiest
where RMAX=RLO+RGATE+RG,I. model to examine the switching behavior of the
Once the maximum pull down resistor value is MOSFET synchronous rectifier is a simplified
given, the gate drive design can be executed. It buck power stage where the rectifier diode is
should be taken into account that the driver’s pull replaced by the QSR transistor as shown in Figure
down impedance is also temperature dependent. 16.
At elevated junction temperature the MOSFET
based gate drive ICs exhibit higher output
resistance than at 25°C where they are usually
QFW
characterized. V IL
QSR
Turn-off speed enhancement circuits can also be
used to meet dv/dt immunity for the MOSFET
since they can shunt out RGATE at turn-off and
during the off state of the device. For instance,
the simple pnp turn-off circuit of Figure 13 can
boost the maximum dv/dt of the MOSFET. The Figure 16. Simplified synchronous rectification
equation modified by the effect of the beta of the model
pnp transistor yields the increased dv/dt rating of: The first thing to recognize in this circuit is that
dv VTH − 0.007 ⋅ (TJ − 25) the operation of the synchronous rectifier
= MOSFET depends on the operation of another
dt ⎛ R + R LO ⎞
⎜ R G,I + GATE
⎜ ⎟ ⋅ C GD
⎟ controlled switch in the circuit, namely the
⎝ β ⎠ forward switch, QFW. The two gate drive
In the dv/dt calculations a returning factor is the waveforms are not independent and specific
internal gate resistance of the MOSFET, which is timing criteria must be met. Overlapping gate
not defined in any data sheet. As pointed out drive signals would be fatal because the two
earlier, this resistance depends on the material MOSFETs would short circuit the voltage source
properties used to distribute the gate signal, the without any significant current limiting
cell density, and the cell design within the component in the loop. Ideally, the two switches
semiconductor. would turn-on and off simultaneously to prevent
the body diode of the QSR MOSFET to turn-on.
SYNCHRONOUS RECTIFIER DRIVE Unfortunately, the window of opportunity to
The MOSFET synchronous rectifier is a special avoid body diode conduction is very narrow.
case of ground referenced switches. These Very accurate, adaptive timing and fast switching
devices are the same N-channel MOSFETs used speeds are required, which are usually out of
in traditional applications, but applied in low reach with traditional design techniques.
16

17. Consequently, in most cases a brief period – from through the driver output impedance. Before
20ns to 80ns – of body diode conduction turn-on, while the drain-to-source voltage
precedes the turn-on and follows the turn-off of changes across the device, the Miller charge
the synchronous MOSFET switch. provided by the power stage must flow through
the driver of the synchronous MOSFET causing
Gate charge additional power dissipation. This phenomenon
During the body diode conduction period the full can be seen in Figure 17, which is part of the next
load current is established in the device and the discussion on dv/dt considerations.
drain-to-source voltage equals the body diode The turn-off procedure of the synchronous
forward voltage drop. Under these conditions the MOSFET obeys the same rules as the turn-on
required gate charge to turn the device on or off procedure, therefore all the previous
is different from the gate charge needed in considerations with respect to gate charge are
traditional first quadrant operation. When the applicable.
gate is turned-on, the drain-to-source voltage is
practically zero and the CGD and CDS capacitors dv/dt considerations
are discharged. Also, the Miller effect is not Figure 17 shows the most important circuit and
present, there is no feedback between the drain current components during the turn-on and turn-
and gate terminals. Therefore, the required gate off procedures of QSR. Actually, it is more
charge equals the charge needed to raise the accurate to say that the switching actions taking
voltage across the gate-to-source and gate-to- place in QFW forces QSR to turn-on or off
drain capacitors from 0V to the final VDRV level. independently of its own gate drive signal.
For an accurate estimate, the low voltage average
value of the CGD capacitor between 0V and VDRV
has to be determined according to:
QFW
VDS,SPEC IL
C GD,SR = 2 ⋅ C RSS.SPEC ⋅ QSR
0.5 ⋅ VDRV V -
RLO,SR
The following equation can then be used to +
estimate the total gate charge of the synchronous
MOSFET rectifier:
Q Q,SR = (C GS + C GD,SR )⋅ VDRV
This value is appreciably lower than the total gate QFW
charge listed in the MOSFET data sheets. The QSR IL
same MOSFET with an identical driver circuit V RLO,SR +
used for synchronous rectification can be turned -
on or off quicker than if it would be driven in its
first quadrant operation. Unfortunately, this
advantage can not be realized since the low Figure 17. Synchronous switching model
RDS(on) devices, applicable for synchronous
rectification, usually have pretty large input and The turn-on of QSR starts with the turn-off of
output capacitances due to their large die size. QFW. When the gate drive signal of QFW
transitions from high to low, the switching node
Another important note from driver power
transitions from the input voltage level to GND.
dissipation point of view is that the total gate
The current stays in the forward switch until the
charge value from the data sheet should be
CRSS capacitor is discharged and the body diode
considered. Although the gate charge delivered
of QSR is forward biased. At that instant the
by the driver during turn-on is less than the
synchronous MOSFET takes over the current
typical number listed in the data sheet, that
flow and QFW turns off completely. After a short
covers a portion of the total charge passing
17

18. delay dominated by the capabilities of the A typical example with logic level MOSFETs
controller, the gate drive signal of QSR is applied driven by a 10V drive signal would yield a ratio
and the MOSFET is turned on. At that time the of 0.417, which means that the pull down drive
current transfers from the body diode to the impedance of QSR must be less than 42% of the
channel of the device. pull up drive impedance of QFW. When carrying
At the end of the conduction period of QSR the out these calculations, remember that every
MOSFET must be turned off. This procedure is parameter except VDRV is temperature dependent
initiated by removing the drive signal from the and their values might have to be adjusted to
gate of the synchronous switch. This event itself reflect the worst case operating conditions of the
will not cause the turn-off of the device. Instead, design.
it will force the current to flow in the body diode
instead of the channel. The operation of the HIGH SIDE NON-ISOLATED GATE
circuit is indifferent to this change. Current starts DRIVES
to shift from QSR to QFW when the gate of the High side non-isolated gate drive circuits can be
forward switch transitions from low to high. classified by the device type they are driving or
Once the full load current is taken over by QFW by the type of drive circuit involved.
and the body diode is fully recovered, the Accordingly, they are differentiated whether
switching node transitions from GND to the input P-channel or N-channel devices are used or
voltage level. During this transition the CRSS whether they implement direct drive, level shifted
capacitor of QSR is charged and the synchronous drive, or bootstrap technique. Which ever way,
MOSFET is susceptible to dv/dt induced turn-on. the design of high side drivers need more
Summarizing this unique operation of the attention and the following checklist might be
synchronous MOSFET and its gate drive, the useful to cover all aspects of the design:
most important conclusion is to recognize that • Efficiency
both turn-on and turn-off dv/dt of the
• Bias / power requirements
synchronous MOSFET is forced on the device by
the gate drive characteristics (i.e. the switching • Speed limitations
speed) of the forward switch. Therefore, the two • Maximum duty-cycle limit
gate drive circuits should be designed together to • dv/dt implications
ensure that their respective speed and dv/dt limit
matches under all operating conditions. This can • Start-up conditions
be ensured by adhering to the steps of the • Transient operation
following simple calculations: • Bypass capacitor size
dv VDRV − VGS,PLATEAU(FW ) • Layout, grounding considerations
=
dt TURN−ON(FW) (R HI(FW) + R GATE(FW) + R G,I(FW)) ⋅ CRSS(FW)
High side drivers for P-channel devices
dv VTH(SR) In this group of circuits the source terminal of the
=
dt MAX(SR) (R LO(SR) + R GATE(SR) + R G,I(SR) ) ⋅ CRSS(SR) P-channel MOSFET switch is connected to the
positive input rail. The driver applies a negative
dv dv
< amplitude turn-on signal to the gate with respect
dt TURN−ON(FW) dt MAX(SR) to the source of the device. This means that the
Assuming the same devices for QSR and QFW, no output of the PWM controller has to be inverted
external gate resistors, and that the internal gate and referenced to the positive input rail. Because
resistance is negligible compared to the drivers the input voltage can be considered as a DC
output impedance, the ratio of the driver output voltage source, high side P-channel drivers do
impedances can be approximated by: not have to swing between large potential
R LO(SR) VTH(SR) differences on the switching frequency basis, but
≤ they must work over the entire input voltage
R HI(FW) VDRV − VGS,PLATEAU(FW )
18

19. range. Moreover, the driver is referenced to an
AC ground potential due to the low AC VDRV VIN
impedance of the input voltage source.
VCC
P-channel direct drive ROFF
Driver
The easiest case of P-channel high side drivers is RGATE
direct drive, which can be implemented if the OUT
maximum input voltage is less then the gate-to- OC
source breakdown voltage of the device. A
typical application area is 12V input DC/DC GND
converters using a P-channel MOSFET, similar
to the schematic in Figure 18. Note the inverted
PWM output signal is readily available in some Figure 19. Open collector drive for PMOS device
dedicated controllers for P-channel devices. Problems are numerous with this implementation
starting with the limited input voltage range due
VDRV=VIN to the voltage rating of the open collector
transistor. But the most inhibiting obstacle is the
VCC high drive impedance. Both resistors, ROFF and
PWM RGATE must be a high value resistor to limit the
controller continuous current in the driver during the
RGATE
conduction period of the switch. Furthermore, the
OUT
gate drive amplitude depends on the resistor
divider ratio and the input voltage level.
Switching speed and dv/dt immunity are severely
GND limited which excludes this circuit from
switching applications. Nevertheless, this very
simple level shift interface can be used for
Figure 18. Direct drive for P-channel MOSFET driving switches in inrush current limiters or
The operation of the circuit is similar to the similar applications where speed is not an
ground referenced direct driver for N-channel important consideration.
devices. The significant difference is the path of Figure 20 shows a level shifted gate drive circuit
the gate drive current, which never flows in the which is suitable for high speed applications and
ground connections. Instead, the high charge and works seamlessly with regular PWM controllers.
discharge currents of the gate are conducted by The open collector level shift principle can be
the positive rail interconnection. Consequently, to easily recognized at the input of a bipolar totem-
minimize the loop inductance in the gate drive, pole driver stage. The level shifter serves two
wide traces or a plane is desirable for the positive purposes in this implementation; it inverts the
input. PWM output and references the PWM signal to
the input rail.
P-channel level shifted drive
The turn-on speed is fast, defined by RGATE and
For input voltages exceeding the gate-to-source R2. During the on-time of the switch a small DC
voltage limit of the MOSFET, level shifted gate current flows in the level shifter keeping the
drive circuits are necessary. The simplest level driver biased in the right state. Both the gate
shift technique is using an open collector driver drive power and the level shift current are
as shown in Figure 19. Unfortunately, open provided by the positive input of the power stage
collector level shifters are not suitable for driving which is usually well bypassed.
MOSFETs directly in a high speed application.
19

20. dv/dt induced turn-on during the off state of the
VIN P-channel MOSFET transistor.
VBIAS In general, the DC level shift drivers have
relatively low efficiency and are power
R1
VCC dissipation limited above a certain input voltage
RGATE
PWM level. The fundamental trade-off is to balance the
R2
controller switching speed and the power consumption of
OUT QINV the level shifter to meet all requirements under
RB the entire input voltage range.
High side direct drivers for N-channel devices
GND
The majority of power supply applications utilize
N-channel MOSFETs as the main power switch
Figure 20. Level shifted P-channel MOSFET because of their lower price, higher speed and
driver lower on-resistance. Using N-channel devices as
a high side switch necessitates a gate drive circuit
The power consumption of the driver has a
which is referenced to the source of the
frequency dependent portion based on the gate
MOSFET. The driver must tolerate the violent
charge of the main switch and a duty-cycle and
voltage swings occurring during the switching
input voltage dependent portion due to the
transitions and drive the gate of the MOSFET
current flowing in the level shifter.
above the positive supply rail of the power
V ⋅D supply. In most cases, the gate drive voltage must
PDRIVE = Q G ⋅ VDRV ⋅ f DRV + IN MAX
R1 + R2 be above the highest DC potential available in the
One of the drawbacks of this circuit is that VDRV circuit. All these difficulties make the high side
is still a function of the input voltage due to the driver design a challenging task.
R1, R2 divider. In most cases protection circuits High side direct drive for N-channel MOSFET
might be needed to prevent excessive voltage
across the gate-to-source terminals. Another In the easiest high side applications the MOSFET
potential difficulty is the saturation of the npn can be driven directly by the PWM controller or
level shift transistor, which can extend the turn- by a ground referenced driver. Two conditions
off time otherwise defined by R1 and RGATE. must be met for this application:
Fortunately both of these shortcomings can be VDRV < VGS,MAX
addressed by moving R2 between the emitter of VIN < VDRV − VGS,Miller
QINV and GND. The resulting circuit provides
constant gate drive amplitude and fast, A typical application schematic is illustrated in
symmetrical switching speed during turn-on and Figure 21 with an optional pnp turn-off circuit.
turn-off. The dv/dt immunity of the driver
VDRV VIN
scheme is primarily set by the R1 resistor. A
Optional
lower value resistor will improve the immunity
against dv/dt induced turn-on but also increases VCC
PWM
the power losses of the level shifter. Also, notice
controller RGATE
that this solution has a built in self-biasing
OUT
mechanism during power up. While the PWM
controller is still inactive, QINV is off and the gate
of the main MOSFET is held below its threshold GND
by R1 and the upper npn transistor of the totem-
pole driver. Pay specific attention to rapid input
voltage transients though as they could cause Figure 21. Direct drive of N-channel MOSFET
20

21. Looking at the basic operation of the circuit – The source falls together with the gate, and while
neglect the pnp turn-off transistor for now – there the voltage across the drain-to-source increases,
are two major differences with this configuration the gate-to-source voltage remains constant at the
compared to the ground referenced drive scheme. VGS,Miller level. The dv/dt is limited by the gate
Since the drain is connected to the positive DC drive impedance and the CGD capacitor of the
input rail, the switching action takes place at the device. Once the source falls 0.7V or so below
source terminal of the device. It is still the same ground, the rectifier diode is supposed to clamp
clamped inductive switching with identical turn- the switching node to ground.
on and turn-off intervals. But from gate drive
design point of view this is a completely different VIN
circuit. Notice that the gate drive current can not
return to ground at the source terminal. Instead it RGATE 2
must go through the load, connected to the source 1
of the device. In discontinuous inductor current
mode the gate charge current must go through the LS
output inductor and the load. In continuous
inductor current mode, however, the loop can be 3 VOUT
closed through the conducting pn junction of the
rectifier diode. At turn-off, the gate discharge LD
current comes through the rectifier diode
connected between ground and the source of the
MOSFET. In all operating modes, both the
charge and discharge currents of the CGD
capacitor flow through the high frequency bypass
capacitor of the power stage.
The net result of all these differences is the VDRV
increased parasitic source inductance due to more
components and larger loop area involved in the 1
gate drive circuitry. As presented earlier, the
source inductance has a negative feedback effect
on the gate drive and slows down the switching
actions in the circuit.
The other significant difference in high side VIN+VGS,Miller
direct drive is the behavior of the source – the
switching node of the circuit. Paying close 2
attention to the source waveform of the MOSFET
during turn-off, a large negative voltage can be VIN
observed. Figure 22 illustrates this rather 3
complex switching action.
As the turn-off is initiated by pulling the gate FWD recovery &
terminal toward ground, the input capacitances of VGS= Current transfer
the MOSFET are quickly discharged to the Miller
plateau voltage. The device is still fully on, the 2 - 3
entire load current is flowing through the drain to
the source and the voltage drop is small. Next, in
the Miller region, the MOSFET works as a Figure 22. Turn-off of high side N-channel
source follower. MOSFET
21

22. Actually, the source can fall way below ground together with the source of the device. However,
for a short period of time until the rectifier diode the driver and its floating bias can be
gets through its forward recovery process and the implemented by low voltage circuit elements
current overcomes the effect of the parasitic since the input voltage is never applied across
inductances. After the load current is completely their components. The driver and the ground
transferred from the MOSFET to the diode, the referenced control signal are linked by a level
switching node can return to its final voltage, a shift circuit which must tolerate the high voltage
diode drop below ground. difference and considerable capacitive switching
This negative excursion of the source voltage currents between the floating high side and
represents a significant problem for the gate drive ground referenced low side circuits.
circuit. Slow diodes, high parasitic inductance
Discrete high performance floating driver
values can cause excessive negative voltage at
the source of the MOSFET, and can pull the A typical implementation representing the
output pin of the driver below ground. To protect bootstrap principle is displayed in Figure 23. The
the driver, a low forward voltage drop Schottky ground referenced PWM controller or MOSFET
diode might be connected between the output pin driver is represented by its local bypass capacitor
and ground as indicated in Figure 21. Another and the output pin. The basic building blocks of
aspect to consider is when the gate terminal the bootstrap gate drive circuit can be easily
reaches 0V, the gate discharge current would recognized. The level-shift circuit is comprised of
become zero. Further negative pull on the gate the bootstrap diode QBST, R1, R2 and the level
terminal and the MOSFET starts turning back on. shift transistor, QLS. The bootstrap capacitor,
Ultimately the system finds a very delicate CBST, a totem-pole bipolar driver and the usual
equilibrium where the gate discharge current and gate resistor are the floating, source referenced
the voltage drop across the parasitic inductances part of the bootstrap solution.
result the same di/dt in the device current. This particular implementation can be used very
Even the optional turn-off speed-up circuit shown effectively in 12V to approximately 24V systems
in Figure 21 can not help during the negative with simple low cost PWM controllers which
voltage spike of the switching junction. The pnp have no floating driver on board. It is beneficial
transistor will turn-off when the gate falls to a that the IC voltage rating does not limit the input
VBE above ground and the MOSFET is left on its voltage level. Furthermore, the level shift circuit
own during the negative voltage transient. Also, is a source switched small NMOS transistor
pay attention to the reduced noise tolerance which does not draw any current during the on
during the off state of the main switch. The time of the main MOSFET from the bootstrap
source is several hundred millivolts below capacitor. It is an important feature to maintain
ground and the gate is held at approximately high efficiency in the level shifter, and to extend
0.7V above ground. This positive voltage across the maximum on-time of the main switch. The
the gate with respect to the source is dangerously operation can be summarized as follows: when
close to the threshold voltage especially for logic the PWM output goes high to turn on the main
level devices and at elevated temperatures. MOSFET, the level shift transistor turns off. R1
supports the base current to the upper npn
Bootstrap gate drive technique transistor in the totem-pole driver and the main
Where input voltage levels prohibit the use of MOSFET turns on. The gate charge is taken from
direct gate drive circuits for high side N-channel the bootstrap capacitor, CBST. As the switch turns
MOSFETs, the principle of bootstrap gate drive on, its source swings to the positive input rail.
technique can be considered. This method utilizes The bootstrap diode and transistor block the input
a gate drive and accompanying bias circuit, both voltage and power to the driver is provided from
referenced to the source of the main MOSFET the bootstrap capacitor. At turn-off, the PWM
transistor. Both the driver and the bias circuit output goes low turning on the level shift
swing between the two input voltage rails transistor.
22

23. VDRV VIN
DBST
VCC
PWM RGATE
controller
OUT CBST
QLS VOUT
GND
Figure 23. Integrated bootstrap driver
Current starts to flow in R1 and R2 towards For even higher voltages, dedicated driver ICs
ground and the lower pnp transistor of the totem- are available to ease the design of bootstrap gate
pole driver turns on. As the gate of the main drive with up to 600V rating. These high voltage
MOSFET discharges, the drain-to-source voltage ICs are differentiated by their unique level shift
increases and the source transitions to ground, design. In order to maintain high efficiency and
allowing the rectifier to turn-on. During the off manageable power dissipation, the level shifters
time of the main switch, the bootstrap capacitor is should not draw any current during the on-time
recharged to the VDRV level through the bootstrap of the main switch. Even a modest 1mA current
diode. This current is supplied by the CDRV in the level shift transistors might result in close
bypass capacitor of the ground referenced to 0.5W worst case power dissipation in the
circuitry and it goes through DBST, CBST, and the driver IC.
conducting rectifier component. This is the basic A widely used technique for these applications is
operating principle of the bootstrap technique. called pulsed latch level translators and they are
revealed in Figure 25.
Integrated bootstrap drivers
In medium input voltage applications, mainly VBST
24V or 48V telecom systems, most of the R Q
Pulse
bootstrap components can be integrated into the Filter S Q
PWM controller as illustrated in Figure 24. PWM OUTH
VDRV VIN
SRC
PWM controller
VCC DBST Figure 25. Typical level shifter in high voltage
driver IC
VBST CBST
Level-Shift
As indicated in the drawing, the PWM input
OUT RGATE signal is translated to ON/OFF commands. The
SRC short pulses generated at the rising and falling
edges drive the level shift transistor pair which
GND
interfaces with the high side circuitry.
Accordingly, the floating portion of the driver is
Figure 24. Integrated bootstrap driver modified as well, the level shifted command
signals have to be differentiated from noise and
23

24. must be latched for proper action. This operation The biggest difficulty with this circuit is the
results in lower power dissipation because of the negative voltage present at the source of the
short duration of the current in the level shifter device during turn-off. As shown previously, the
but lowers noise immunity since the command amplitude of the negative voltage is proportional
signal is not present at the input of the driver to the parasitic inductance connecting the source
continuously. The typical pulse width in a 600V of the main MOSFET to ground (including the
rated pulsed latch level translator is around 120 parasitic inductance associated with the rectifier)
nanoseconds. This time interval adds to natural and the turn-off speed (di/dt) of the device as
delays in the driver and shows up as turn-on and determined primarily by the gate drive resistor,
turn-off delays in the operation and is indicated RGATE and input capacitor, CISS. This negative
in the data sheet of the drivers. Due to the longer voltage can be serious trouble for the driver’s
than optimum delays, the operating frequency output stage since it directly affects the source
range of the high voltage gate driver ICs is pin – often called SRC or VS pin – of the driver
limited below a couple of hundreds of kHz. or PWM IC and might pull some of the internal
Some lower voltage high side driver ICs (up to circuitry significantly below ground.
100V) use continuous current DC level shift The other problem caused by the negative voltage
circuits to eliminate the delay of the pulse transient is the possibility to develop an over
discriminator, therefore they support higher voltage across the bootstrap capacitor. Capacitor
operating frequency. CBST will be peak charged by DBST from CDRV.
Since CDRV is referenced to ground, the
Bootstrap switching action maximum voltage which can build on the
Bootstrap gate drive circuits are used with high bootstrap capacitor is the sum of VDRV and the
side N-channel MOSFET transistors as shown in amplitude of the negative voltage at the source
Figure 26. The switching transitions of the high terminal. A small resistor in series with the
side switch were explored previously with bootstrap diode can mitigate the problem.
respect to the high side N-channel direct drive Unfortunately, the series resistor does not provide
scheme and are equally applicable with bootstrap a foolproof solution against an over voltage and it
drivers. also slows down the recharge process of the
bootstrap capacitor.
VDRV VIN
DBST
CBST
VCC VCC VB
PWM CDRV RGATE
Level-Shift
OUT
controller
IN VS
OUT
High Side Negative
voltage
GND Driver
transient
GND
Figure 26. High voltage driver IC for bootstrap gate drive
24

25. A circuit to deliver very effective protection for The only potential hazard presented by this
the SRC pin is given in Figure 27. It involves circuit is that the charge current of the bootstrap
relocating the gate resistor from the gate to the capacitor must go through RGATE. The time
source lead between the driver and the main constant of CBST and RGATE slows the recharge
MOSFET and adding a small, low forward process which might be a limiting factor as the
voltage drop Schottky diode from ground to the PWM duty ratio approaches unity.
SRC pin of the driver.
Bootstrap biasing, transient issues and start-up
VDRV VIN Figure 28 shows a typical application diagram of
PWM controller the bootstrap gate drive technique. There are four
or driver output important bypass capacitors marked on the
DBST schematic.
VCC
The bootstrap capacitor, CBST is the most
VBST CBST
important component from the design point of
Level-Shift
OUT RGATE view, since it has to filter the high peak current
charging the gate of the main MOSFET while
SRC providing bias for the source referenced floating
circuitry. In every switching cycle during normal
GND
operation, the bootstrap capacitor provides the
total gate charge (QG) to turn-on the MOSFET,
Figure 27. Protecting the SRC pin the reverse recovery charge (QRR) and leakage
current of the bootstrap diode (ILK,D), the
In this circuit, RGATE has a double purpose; it sets
quiescent current of the level shifter (IQ,LS) and
the turn-on and turn-off speed in the MOSFET
the gate driver (IQ,DRV), and the leakage current
and also provides current limiting for the
between the gate-source terminals (IGS),
Schottky diode during the negative voltage
including the current drawn by a potential gate-
transient of the source terminal of the main
to-source pull down resistor. Some of these
switch. Now, the switching node can swing
currents flow only during the on-time of the main
several volts below ground without disturbing the
switch and some of them might be zero
operation of the driver. In addition, the bootstrap
depending on the actual implementation of the
capacitor is protected against over voltage by the
driver and level shifter.
two diodes connected to the two ends of CBST.
VBIAS VDRV VIN
DBST
VCC VCC VB CBST
PWM CDRV
OUT CIN
controller CBIAS RGATE
OUT IN VS
VOUT
High Side
GND COUT
Driver
GND
Figure 28. Bootstrap bypassing example
25

26. Assuming steady state operation, the following under voltage lockout threshold of the driver.
general equation can be used to calculate the With a discrete floating driver implementation,
bootstrap capacitor value to achieve the targeted VUVLO could be substituted by the minimum safe
ripple voltage, ΔVBST: gate drive voltage.
D Any load transient in the other direction will
Q G + Q RR + I BST ⋅ MAX require pulse skipping when the MOSFET stays
f DRV
C BST = off for several switching cycles. When the output
ΔVBST inductor current reaches zero, the source of the
where main switch will settle at the output voltage level.
I BST = I LK,D + I Q,LS + I Q,DRV + I GS The bootstrap capacitor must supply all the usual
discharge current components and store enough
To finalize the bootstrap capacitor value, two energy to be able to turn-on the switch at the end
extreme operating conditions must be checked as of the idle period. Similar to the previous
well. During load transients it might be necessary transient mode, a minimum capacitor value can
to keep the main switch on or off for several be calculated as:
switching cycles. In order to ensure uninterrupted
operation under these circumstances, the CBST Q + (I LK,D + I Q,LS + I Q,DRV )⋅ t OFF,MAX
C BST,MIN = G
capacitor must store enough energy to hold the VBST − VUVLO
floating bias voltage above the under voltage In certain applications, like in battery chargers,
lockout threshold of the high side driver IC for an the output voltage might be present before input
extended period of time. power is applied to the converter. In these cases,
Going from light load to heavy load, certain the source of the main MOSFET and the negative
controllers can keep the main switch on node of CBST are sitting at the output voltage and
continuously until the output inductor current the bootstrap diode might be reverse biased at
reaches the load current value. The maximum on start-up. Delivering the initial charge to the
time (tON,MAX) is usually defined by the value and bootstrap capacitor might not be possible
the voltage differential across the output inductor. depending on the potential difference between
For these cases, a minimum bootstrap capacitor the bias and output voltage levels. Assuming
value can be established as: there is enough voltage differential between the
Q + Q RR + I BST ⋅ t ON,MAX input and output voltages, a simple circuit
C BST,MIN = G comprised of RSTART resistor, DSTART diode, and
VBST − VUVLO
DZ zener diode can solve the start-up problem as
where VBST is the initial value of the bootstrap shown in Figure 29.
bias voltage across CBST and VUVLO is the
VBIAS VIN
DBST DSTART RSTART
VCC CBST
VCC VB DZ R
PWM GATE
controller OUT Battery
OUT IN VS
High Side
GND
Driver
GND
Figure 29. Bootstrap start-up circuit
26

27. In this start-up circuit, DSTART serves as a second recharge happens in a short time interval and
bootstrap diode used for charging the bootstrap involves high peak current. Therefore, the high
capacitor at power up. CBST will be charged to the side driver must be bypassed locally on its input
zener voltage of DZ which is supposed to be side as well. According to the rule-of-thumb,
higher than the driver’s bias voltage during CDRV should be an order of magnitude larger than
normal operation. The charge current of the CBST. Minimizing this loop area on the printed
bootstrap capacitor and the zener current are circuit board is equally important to ensure
limited by the start-up resistor. For best reliable operation.
efficiency the value of RSTART should be selected The third issue with the circuit is to contain the
to limit the current to a low value since the parasitic capacitive currents flowing between
second bootstrap path through the start-up diode power ground and the floating circuitry in a low
is permanently in the circuit. impedance loop. The goal is to steer these
currents away from the ground of the sensitive
Grounding considerations
analog control parts. Figure 30 reveals the
There are three important grounding issues which parasitic capacitive current paths in two
have to be addressed with respect to the optimum representative applications with high side driver
layout design of the bootstrap gate drivers with ICs.
high side N-channel MOSFETs. Figure 28 can be
used to identify the most critical high current VBIAS VIN
loops in a typical application.
The first focus is to confine the high peak PWM
VCC VCC VB
RGATE
Level-Shift
OUT
currents of the gate in a minimal physical area. controller
IN VS
Considering the path the gate current must pass OUT
High Side
through, it might be a challenging task. At turn- GND Driver
on, the path involves the bootstrap capacitor, the
turn-on transistor of the driver, the gate resistor,
GND
the gate terminal, and finally, the loop is closed at
the source of the main MOSFET where CBST is VBIAS VIN
referenced. The turn-off procedure is more
complicated as the gate current has two separate VCC VCC VB
components. The discharge current of the CGS PWM RGATE
Level-Shift
HO
controller
capacitor is well localized, it flows through the OUT1
HI VS
gate resistor, the turn-off transistor of the driver Half Bridge
Driver
and from the source to the gate of the power OUT2
LI LO
MOSFET. On the other hand, the CGD capacitor’s
current must go through RGATE, the turn-off GND
GND COM
transistor of the driver, the output filter, and
finally the input capacitor of the power stage
(CIN). All three loops carrying the gate drive Figure 30. Capacitive currents in high side
currents have to be minimized on the printed applications
circuit board. Single high side driver ICs usually have only one
The second high current path includes the GND connection. Since the capacitive currents
bootstrap capacitor, the bootstrap diode, the local must return to the ground potential of the power
ground referenced bypass capacitor of the driver, stage, the low side portion of the IC should be
and the rectifier diode or transistor of the power referenced to power ground. This is
stage. CBST is recharged on the cycle-by-cycle counterintuitive, since the control signal of the
basis through the bootstrap diode from the driver is referenced to signal ground.
ground referenced driver capacitor, CDRV, Nevertheless, eliminating the high capacitive
connected from the anode of DBST to ground. The current component between analog and power
27

28. ground will also ensure that the potential
difference between the two grounds are VDRV
minimized.
The situation is greatly improved with general VCC
purpose half bridge driver ICs which contain one PWM +VDRV VDRV-VCL
low side and one high side driver in the same controller -VCL
0V
package. These circuits have two ground OUT
connections usually labeled as GND and COM, CC
IC,AVE=0
providing more flexibility in layout. To return the -VCL RGS
capacitive currents to power ground in the
GND
shortest possible route, the COM pin is connected
to power ground. The GND pin can be utilized to
provide connection to the signal ground of the
controller to achieve maximum noise immunity. Figure 31. Capacitively coupled MOSFET gate
drive
For completeness, the bypass capacitor of the
PWM controller should be mentioned as well, The resistor plays a crucial role during power up,
which is placed near to the VCC and GND pins pulling the gate low. This is the only mechanism
of the IC. Referring to Figure 28 again, CBIAS is a keeping the MOSFET off at start up due to the
relatively small capacitor with respect to CBST blocking effect of the coupling capacitor between
and CDRV since it provides only high frequency the output of the driver and the gate of the device.
bypassing and it is not involved in the gate drive In addition, RGS provides a path for a current
process. across the coupling capacitor. Without this
current component the voltage would not be
AC COUPLED GATE DRIVE allowed to build across CC. Theoretically, in
CIRCUITS every switching cycle the same amount of total
AC coupling in the gate drive path provides a gate charge would be delivered then removed
simple level shift for the gate drive signal. The through the capacitor and the net charge passing
primary purpose of AC coupling is to modify the through CC would be zero.
turn-on and turn-off gate voltages of the main The same concept can be applied for steady state
MOSFET as opposed to high side gate drives operation to determine the DC voltage across the
where the key interest is to bridge large potential coupling capacitor with RGS in the circuit.
differences. In a ground referenced example like Assuming no clamp circuitry, a constant VC
the one in Figure 31, the gate is driven between voltage across the capacitor, and a constant duty
-VCL and VDRV-VCL levels instead of the original cycle D, the current of RGS can be represented as
output voltage levels of the driver, 0V and VDRV. an additional charge component passing through
The voltage, VCL is determined by the diode CC. Accordingly, the total charge delivered
clamp network and it is developed across the through the coupling capacitor during turn-on
coupling capacitor. The benefit of this technique and consecutive on-time of the MOSFET is:
is a simple way to provide negative bias for the V − VC D
gate at turn-off and during the off state of the Q C,ON = Q G + DRV ⋅
R GS f DRV
switch to improve the turn-off speed and the
dv/dt immunity of the MOSFET. The trade-off is Following the same considerations for the turn-
slightly reduced turn-on speed and potentially off and successive off-time of the switch, the
higher RDS(on) resistance because of the lower total charge can be calculated as:
positive drive voltage. V 1− D
Q C,OFF = Q G + C ⋅
The fundamental components of AC coupling are R GS f DRV
the coupling capacitor CC and the gate-to-source For steady state operation, the two charges must
load resistor RGS. be equal.
28

29. Solving the equations for VC determines the The ripple voltage can be calculated based on the
voltage across the coupling capacitor: charge defined previously as:
VC = VDRV ⋅ D Q
ΔVC = G + DRV
(V − VC ) ⋅ D
This well know relationship highlights the duty C C C C ⋅ R GS ⋅ f DRV
ratio dependency of the coupling capacitor Taking into account that Vc=D⋅VDRV, the
voltage. As duty cycle varies, VC is changing and equation can be rearranged to yield the desired
the turn-on and turn-off voltages of the MOSFET capacitor value as well:
adjust accordingly. As Figure 32 exemplifies, at
Q V ⋅ (1 − D ) ⋅ D
low duty cycles the negative bias during turn-off C C = G + DRV
is reduced, while at large duty ratios the turn-on ΔVC ΔVC ⋅ R GS ⋅ f DRV
voltage becomes insufficient. The expression reveals a maximum at D=0.5. A
good rule of thumb is to limit the worst case AC
1
ripple amplitude (ΔVc) to approximately 10% of
VDRV.
Normalized Steady State DC
Voltage (VC/VDRV) Across CC
0.8
Start up transient of the coupling capacitor
0.6 Before the desired minimum coupling capacitor
value could be calculated, one more parameter
must be defined. The value of RGS has to be
0.4 VCL selected. In order to make an intelligent decision
VDRV Zener Clamp the start up transient of the AC coupling circuit
0.2 must be examined.
At power up, the initial voltage across CC is zero.
0 As the output of the driver start switching the DC
0 0.2 0.4 0.6 0.8 1 voltage across the coupling capacitor builds up
Duty Ratio gradually until it reaches its steady state value,
VC. The duration to develop VC across CC
Figure 32. Normalized coupling capacitor depends on the time constant defined by CC and
voltage as a function of duty ratio RGS. Therefore, to achieve a target start-up
The inadequate turn-on voltage at large duty transient time and a certain ripple voltage of the
ratios can be resolved by using a clamp circuit coupling capacitor at the same time, the two
connected in parallel to RGS as shown in Figure parameters must be calculated together.
31. Its effect on the coupling capacitor voltage is Fortunately, there are two equations for two
also shown in Figure 32. As the coupling unknowns:
capacitor voltage is limited by the clamp, the Q V ⋅ (1 − D ) ⋅ D
maximum negative bias voltage of the gate is C C = G + DRV
ΔVC ΔVC ⋅ R GS ⋅ f DRV
determined. Since the gate drive amplitude is not
effected by the AC coupling circuit, a minimum τ
turn-on voltage can be guaranteed for the entire τ=R GS ⋅ C C → R GS =
CC
duty cycle range.
which will yield a single solution. Substituting
Calculating the coupling capacitor the expression for RGS from the second equation,
The amount of charge going through CC in every D=0.5 for worst case condition and targeting
switching cycle causes an AC ripple across the ΔVc=0.1⋅VDRV, the first equation can be solved
coupling capacitor on the switching frequency and simplified for a minimum capacitor value:
basis. Obviously, this voltage change should be 20 ⋅ Q G ⋅ τ ⋅ f DRV
kept relatively small compared to the amplitude C C,MIN =
VDRV ⋅ (2 ⋅ τ ⋅ f DRV − 5)
of the drive voltage.
29

30. Once CC,MIN is calculated, its value and the storage thus to maintain high efficiency. The
desired start-up time constant (τ) defines the gate drive transformer handles very low
required pull down resistance. A typical design average power, but it delivers high peak
trade-off for AC coupled drives is to balance currents at turn-on and turn-off. To avoid
efficiency and transient time constant. For time delays in the gate drive path, low
quicker adjustment of the coupling capacitor leakage inductance is still imperative.
voltage under varying duty ratios, higher current • Faraday’s law requires that the average
must be allowed in the gate-to-source resistor. voltage across the transformer winding must
be zero over a period of time. Even a small
TRANSFORMER COUPLED GATE DC component can cause flux “walk” and
DRIVES eventual core saturation. This rule will have a
Before the appearance of high voltage gate drive substantial impact on the design of
ICs, using a gate drive transformer was the only transformer coupled gate drives controlled
viable solution to drive high side switches in off- by single ended PWM circuits.
line or similar high voltage circuits. The two • Core saturation limits the applied volt-second
solutions coexist today, both have their pros and product across the windings. The transformer
cons serving different applications. The design must anticipate the maximum volt-
integrated high side drivers are convenient, use second product under all operating conditions
smaller circuit board area but have significant which must include worst case transients with
turn-on and turn-off delays. The properly maximum duty ratio and maximum input
designed transformer coupled solution has voltage at the same time. The only relaxation
negligible delays and it can operate across higher for gate drive transformer design is their
potential differences. Usually it takes more regulated supply voltage.
components and requires the design of a • A significant portion of the switching period
transformer or at least the understanding of its might be reserved to reset the core of the
operation and specification. main power transformer in single ended
Before concentrating on the gate drive circuits, applications, (working only in the first
some common issues pertinent to all transformer quadrant of the B-H plane) such as the
designs and their correlation to gate drive forward converter. The reset time interval
transformers will be reviewed. limits the operating duty ratio of the
• Transformers have at least two windings. The transformer. This is rarely an issue even in
use of separate primary and secondary single ended gate drive transformer designs
windings facilitates isolation. The turns ratio because they must be AC coupled thus they
between primary and secondary allows operate with bi-directional magnetization.
voltage scaling. In the gate drive transformer,
Single ended transformer coupled gate drive
voltage scaling is usually not required, but
circuits
isolation is an important feature.
These gate drive circuits are used in conjunction
• Ideally the transformer stores no energy, there
with a single output PWM controller to drive a
is no exemption. The so called flyback
high side switch. Figure 33 shows the basic
“transformer” really is coupled inductors.
circuit.
Nevertheless, small amounts of energy are
stored in real transformers in the non- The coupling capacitor must be placed in series
magnetic regions between the windings and with the primary winding of the gate drive
in small air gaps where the core halves come transformer to provide the reset voltage for the
together. This energy storage is represented magnetizing inductance. Without the capacitor
by the leakage and magnetizing inductance. there would be a duty ratio dependent DC voltage
In power transformers, reducing the leakage across the winding and the transformer would
inductance is important to minimize energy saturate.
30

31. VDRV
connected between the gate and the source of the
main MOSFET. Accordingly, the start-up and
+VDRV-VC transient time constant governing the adjust
VCC
+VDRV -VC speed of the coupling capacitor voltage reflects
PWM
controller 0V
the effect of the magnetizing inductance of the
VC
OUT
+ - gate drive transformer and can be estimated by:
RC CC 2 ⋅ π ⋅ f DRV ⋅ L M ⋅ R GS ⋅ C C
RGS τ=
2 ⋅ π ⋅ f DRV ⋅ L M + R GS
GND
The magnetizing inductance has another
significant effect on the net current of the driver,
Figure 33. Single ended transformer coupled and on its direction. Figure 34 highlights the
gate drive different current components flowing in the
circuit and the sum of the current components,
The DC voltage (VC) of CC develops the same
IOUT, which has to be provided by the driver.
way as shown in AC coupled direct drives. The
steady state value of the coupling capacitor
voltage is:
V OUT
VC = D ⋅ VDRV
Similar to AC coupled direct drives, the actual VT
gate drive voltage, VC, changes with duty ratio.
In addition, sudden changes in duty ratio will
excite the L-C resonant tank formed by the IM
magnetizing inductance of the gate drive
transformer and the coupling capacitor. In most IR
cases this L-C resonance can be damped by
inserting a low value resistor (RC) in series with
CC. The value of RC is determined by the
IG
characteristic impedance of the resonant circuit
and given as:
LM
IOUT
RC ≥ 2⋅
CC
Keep in mind that the RC value defined in the Figure 34. Driver output current with
equation above is the equivalent series resistance transformer coupled gate drive
which includes the output impedance of the
PWM driver. Additionally, consider that a Note the gray shaded area in the output current
critically damped response in the coupling waveform. The output driver is in its low state
capacitor voltage might require unreasonable which means it is supposed to sink current. But
high resistor value. This would limit the gate because of the magnetizing current component,
current, consequently the switching speed of the the driver actually sources current. Therefore, the
main switch. On the other hand, underdamped output must handle bi-directional current with
response may result in unacceptable voltage transformer coupled gate drives. This might
stress across the gate source terminals during the require additional diodes if the driver is not
resonance. capable of carrying current in both directions.
Bipolar MOSFET drivers are a typical example
The current building VC has two components; the where a Schottky diode has to be connected
magnetizing current of the transformer and the between the ground and the output pin. Similar
current flowing in the pull down resistor situation can occur during the high state of the
31

32. driver at different duty cycle or current the total gate charge of the main MOSFET and a
component values. One easy remedy to solve this second component due to the current flowing in
problem and avoid the diodes on the driver’s the gate pull down resistor:
output is to increase the resistive current Q
C C2 = G + DRV
(V − VDC2,FW )⋅ D MAX
component to offset the effect of the magnetizing
ΔVC2 ΔVC2 ⋅ R GS ⋅ f DRV
current.
At wide duty cycles, like in the buck converter, This expression has a maximum at the maximum
the circuit of Figure 33 does not provide adequate on-time of the switch, i.e. at maximum duty ratio.
gate drive voltage. The coupling capacitor In the primary side coupling capacitor the
voltage increases proportionally to the duty ratio. magnetizing current of the gate drive transformer
Accordingly, the negative bias during off-time generates an additional ripple component. Its
increases as well and the turn-on voltage effect is reflected in the following equation which
decreases. Adding two small components on the can be used to calculate the primary side
secondary side of the gate drive transformer can coupling capacitor value:
prevent this situation. Figure 35 shows a Q
C C1 = G + DRV
(V − VDC2,FW )⋅ D + VDRV ⋅ (D 2 − D 3 )
commonly used technique to restore the original
voltage levels of the gate drive pulse. ΔVC1 ΔVC1 ⋅ R GS ⋅ f DRV ΔVC1 ⋅ 4 ⋅ L M ⋅ f DRV
2
The minimum capacitance to guarantee to stay
VDRV below the targeted ripple voltage under all
+VDRV-VC
operating conditions can be found by determining
VCC
+VDRV -VC +VDRV-VD the maximum of the above expression.
PWM
controller 0V VC VC-VD -VD Unfortunately the maximum occurs at different
OUT
+ -
+ -
duty ratios depending on the actual design
RC CC1 CC2 parameters and component values. In the
DC2 RGS
majority of practical solutions it falls between
GND D=0.6 and D=0.8 range.
Also note that the sum of the ripple voltages,
Figure 35. DC restore circuit in transformer ΔVC1+ΔVC2 appears at the gate terminal of the
coupled gate drive main MOSFET transistor. When aiming for a
particular ripple voltage or droop at the gate
Here, a second coupling capacitor (CC2) and a terminal, it has to be split between the two
simple diode clamp (DC2) are used to restore the coupling capacitors.
original gate drive amplitude on the secondary
side of the transformer. If a larger negative bias is Gate drive transformer design
desired during the off time of the main switch, a The function of the gate drive transformer is to
Zener diode can be added in series with the diode transmit the ground referenced gate drive pulse
in a similar fashion as it is shown in Figure 31, across large potential differences to
with respect to the AC coupled direct drive accommodate floating drive implementations.
solution. Like all transformers, it can be used to
Calculating the coupling capacitors incorporate voltage scaling, although it is rarely
required. It handles low power but high peak
The method to calculate the coupling capacitor currents to drive the gate of a power MOSFET.
values is based on the maximum allowable ripple The gate drive transformer is driven by a variable
voltage and the amount of charge passing through pulse width as a function of the PWM duty ratio
the capacitor in steady state operation was and either constant or variable amplitude
described in the previous AC coupled circuits. depending on the circuit configuration. In the
The equation for CC2 is similar to the one single ended circuits the gate drive transformer is
identified for direct coupled gate drive circuit. AC coupled and the magnetizing inductance sees
The ripple has two components; one is related to a variable amplitude pulse. The double ended
32

33. arrangements, such as half-bridge applications, For an AC coupled circuit, the worst case is at
drive the gate drive transformer with a constant D=0.5 while direct coupling reaches the peak
amplitude signal. In all cases, the gate drive volt-second value at the maximum operating duty
transformers are operated in both, the first and ratio. Interestingly, the AC coupling reduces the
third quadrant of the B-H plane. maximum steady state volt-second product by a
The gate drive transformer design is very similar factor of four because at large duty ratios the
to a power transformer design. The turns ratio is transformer voltage is proportionally reduced due
usually one, and the temperature rise due to to the voltage developing across the coupling
power dissipation is usually negligible. capacitor.
Accordingly, the design can be started with the It is much more difficult to figure out ΔB in the
core selection. Typical core shapes for gate drive Np equation. The reason is flux walking during
transformer include toroidal , RM, P or similar transient operation. When the input voltage or the
cores. The core material is high permeability load are changing rapidly, the duty ratio is
ferrite to maximize the magnetizing inductance adjusted accordingly by the PWM controller.
value, consequently lower the magnetizing Deducing exact quantitative result for the flux
current. Seasoned designers can pick the core walk is rather difficult. It depends on the control
size from experience or it can be determined loop response and the time constant of the
based on the area product estimation in the same coupling network when it is present. Generally,
way as it is required in power transformer design. slower loop response and a faster time constant
Once the core is selected, the number of turns of have a tendency to reduce flux walking. A three
the primary winding can be calculated by the to one margin between saturation flux density
following equation: and peak flux value under worst case steady state
V ⋅t operation is desirable for most designs to cover
N P = TR transient operation.
ΔB ⋅ A e
The next step is to arrange the windings in the
where VTR is the voltage across the primary available window area of the core. As mentioned
winding, t is the duration of the pulse, ΔB is the before, the leakage inductance should be
peak-to-peak flux change during t, and Ae is the minimized to avoid time delay across the
equivalent cross section of the selected core. transformer, and the AC wire resistance must be
The first task is to find the maximum volt-second kept under control. On toroidal cores, the
product in the numerator. Figure 36 shows the windings should be wound bifilar or trifilar
normalized volt-second product for both single depending on the number of windings in the gate
ended and double ended gate drive transformers drive transformer. With pot cores, each winding
as the function of the converter duty cycle. should be kept in a single layer. The primary
1
should be the closest to the center post, followed
by the low side winding, if used, and the high
VDRV·TDRV
VTR· t
0.8 side winding should be the farthest from the
DC coupled center post. This arrangement in pot cores
0.6 (double ended) provides an acceptable leakage inductance and
Normalized V·s Product
the lowest AC winding resistance. Furthermore,
AC coupled
0.4 (single ended) natural shielding of the control (primary) winding
against capacitive currents flowing between the
0.2 floating components and power ground is
provided by the low side winding which is
0
0 0.2 0.4 0.6 0.8 1 usually connected to the power ground directly.
Duty Ratio
Dual duty transformer coupled circuits
Figure 36. Gate drive transformer volt-second There are high side switching applications where
product vs. duty ratio the low output impedance and short propagation
33

34. delays of a high speed gate drive IC are essential. VDRV
Figure 37 and Figure 38 show two fundamentally Low Side IC
+VDRV-2 VD
VCC
different solutions to provide power as well as PWM
High Side IC
control to regular low voltage gate drive ICs in a AM
floating application using only one transformer.
OSC
VDRV
+VDRV-VC
VCC
PWM +VDRV
-VC +VDRV-2 VD Figure 38. Power and control transmission with
controller
0V
one transformer
OUT
Another similar solution to transfer power and
+ -
+ -
VC VC-VD
control signal with the same transformer is shown
GND in Figure 38. The difference between the two
circuits in Figures 37 and 38 is the operating
frequency of the transformer. This
Figure 37. Power and control transmission with implementation utilizes a dedicated chip pair.
one transformer The high frequency carrier signal
The circuit of Figure 37 uses the switching (fCARRIER>>fDRV) is used to power transfer, while
frequency to carry the control signal and the amplitude modulation transmits the control
power for the driver. The operation is rather command. The basic blocks of the gate drive
simple. During the on-time of the main switch, schematic in Figure 38 can be integrated into two
the positive voltage on the secondary side of the integrated circuits allowing efficient utilization of
transformer is peak rectified to generate the circuit board area. Because of the high frequency
supply voltage for the gate drive IC. Since the operation, the transformer size can be reduced
power is generated from the gate drive pulses, the compared to traditional gate drive transformers.
first few drive pulses must charge the bias Another benefit of this solution is that the bias
capacitor. Therefore, it is desirable that the driver voltage of the floating driver can be established
IC chosen for this application has an under independently of the gate drive commands, thus
voltage lock out feature to avoid operation with the driver can react without the start-up delay
insufficient gate voltage. As it is shown in the discussed in the previous solution.
circuit diagram, the DC restoration circuit (CC2
Double ended transformer coupled gate drives
and DC2) must be used to generate a bias voltage
for the driver which is independent of the In high power half-bridge and full-bridge
operating duty ratio. DC2 also protects the input converters, the need arises to drive two or more
of the driver against the negative reset voltage of MOSFETs usually controlled by a push-pull or
the transformer secondary winding. The also called double-ended PWM controller. A
transformer design for this circuit is basically simplified schematic of such gate drive circuit is
identical to any other gate drive transformer illustrated in Figure 39.
design. The power level is just slightly increased In these applications a dual polarity symmetrical
by the power consumption of the driver IC, gate drive voltage is readily available. In the first
which is relatively small compared to the power clock cycle, OUTA is on, forcing a positive
loss associated by the total gate charge of the voltage across the primary winding of the gate
MOSFET. The transformer carries a high peak drive transformer. In the next clock cycle, OUTB
current but this current charges the bypass is on for the same amount of time (steady state
capacitor, not the input capacitance of the operation) providing an opposite polarity voltage
MOSFET. All gate current is contained locally across the magnetizing inductance. Averaging the
between the main transistor, driver IC and bypass voltage across the primary for any two
capacitor. consecutive switching period results zero volts.
34

35. A unique application of the push-pull type gate
VIN drive circuits is given in Figure 40 to control four
VDRV power transistors in a phase shift modulated full-
RGATE bridge converter.
VCC VIN
VDRV
OUTA
VCC
RGATE
Driver OUTA
OUTB OUTB
Phase Shift
PWM controller
GND
OUTC
OUTD
Figure 39. Push-pull type half-bridge gate drive GND
Therefore, AC coupling is not needed in push-
pull type gate drive circuits.
Figure 40. Push-pull type half-bridge gate drive
Designers are often worried about any small
amount of asymmetry that could be caused by Due to the phase shift modulation technique, this
component tolerances and offsets in the power stage uses four approximately 50% duty
controller. These small deviations are easily cycle gate drive signals. The two MOSFETs in
compensated by the output impedance of the each leg requires a complementary drive
driver or by a small resistor in series with the waveform which can be generated by the two
primary winding of the transformer. The uneven output windings of the same gate drive
duty cycle will cause a small DC current in the transformer. Although, steady state duty ratios
transformer which generates a balancing voltage are always 0.5, changing the phase relationship
across the equivalent resistance of the drive between the two complementary pulse trains
circuit. Assuming two different duty ratios, DA necessitates to have an asymmetry in the duty
and DB for the PWM outputs, the DC current cycles. Therefore, during transient operation the
level of the magnetizing inductance is defined as: PWM outputs are not producing the normal 50%
duty cycle signals for the gate drive transformers.
VDRV
I DC = ⋅ (D A − D B ) Accordingly, a safety margin must be built in the
2 ⋅ R EQV transformer to cover uneven duty ratios during
To demonstrate the triviality of this problem, transients.
let’s assume that DA=0.33, DB=0.31 (6% relative Another interesting fact to point out is that local
duty ratio difference!), VDRV=12V, and REQV=5Ω turn-off circuits can be easily incorporated and
which is the sum of one low side and one high are very often needed on the secondary side of
side driver output impedance. The resulting DC the transformer. The gate drive transformer, more
current is 24mA and the excess power dissipation precisely the leakage inductance of the
is only 3mW. transformer exhibits a relatively high impedance
The design of the gate drive transformer follows for fast changing signals. The turn-off speed and
the same rules and procedures as already dv/dt immunity of the power circuit can be
described in this chapter. The maximum volt- severely impacted if the driver’s pull down
second product is defined by VDRV and the capability is not optimized for high speed
switching period, because push-pull circuits are switching applications.
usually not duty ratio limited.
FINAL COMMENTS, SUMMARY
Appropriate margin (~3:1) between worst case
peak flux density and saturation flux density must Like all books, this article should be read from
be provided. the beginning to the end to get the whole story.
35

36. Every consideration described earlier regarding • Design (or select) the gate drive transformer
switching speeds, dv/dt immunity, bypassing if needed.
rules etc. are equally applicable for all circuits • Calculate the coupling capacitor values in
including transformer coupled gate drives. As the case of AC coupling.
topics build upon each other, only the unique and
new properties of the particular circuit have been • Check start-up and transient operating
highlighted. conditions, especially in AC coupled gate
drive circuits.
This paper demonstrated a systematic approach
to design high performance gate drive circuits for • Evaluate the dv/dt and di/dt capabilities of the
high speed switching applications. The procedure driver and compare it to the values
can be summarized by the following step-by-step determined by the power stage.
checklist: • Add one of the turn-off circuits if needed, and
• The gate drive design process begins AFTER calculate its component values to meet dv/dt
the power stage is designed and the power and di/dt requirements.
components are selected. • Check the power dissipation of all
• Collect all relevant operating parameters. components in the driver circuitry.
Specifically the voltage and current stresses • Calculate the bypass capacitor values.
of the power MOSFET based on the • Optimize the printed circuit board LAYOUT
application requirements, operating junction to minimize parasitic inductances.
temperature, dv/dt and di/dt limits related to
• Always check the gate drive waveform on the
external circuits around the power MOSFET
final printed circuit board for excessive
which are often determined by the different
ringing at the gate-source terminals and at the
snubber or resonant circuitry in the power
output of the driver IC.
stage.
• Add protection or tune the resonant circuits
• Estimate all device parameters which
by changing the gate drive resistor as needed.
describe the parasitic component values of
the power semiconductor in the actual In a reliable design, these steps should be
application circuit. Data sheet values are evaluated for worst case conditions as elevated
often listed for unrealistic test conditions at temperatures, transient voltage and current
room temperature and they must be corrected stresses can significantly change the operation of
accordingly. These parameters include the the driver, consequently the switching
device capacitances, total gate charge, RDS(on), performance of the power MOSFET.
threshold voltage, Miller plateau voltage, Of course, there are many more gate drive
internal gate mesh resistance, etc. implementations which are not discussed in this
• Prioritize the requirements: performance, paper. Hopefully, the principles and methods
printed circuit board size, cost target, etc. presented here can help the reader’s
Then choose the appropriate gate drive circuit understanding and analyzing of other solutions.
to match the power stage topology. For those who are looking for quick answers in
the rather complex field of high speed gate drive
• Establish the bias voltage level which will be design, Appendix A through E offer typical,
used to power the gate drive circuit and check numerical examples of the different calculations.
for sufficient voltage to minimize the RDS(on) Appendix F provides a complete, step-by-step
of the MOSFET. gate drive design example for an active clamp
• Select a driver IC, gate-to-source resistor forward converter with a ground referenced and a
value, and the series gate resistance RGATE floating gate drive circuits.
according to the targeted power-up dv/dt, and
desired turn-on and turn-off switching speeds.
36

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37