Design and analysis of ultra low power vlsi circuit in sub and near threshold region (2016)

-A Project by
Tushit Banerjee
under the guidance of
Prof. Manash Chanda
DESIGN AND ANALYSIS OF ULTRA
LOW POWER VLSI CIRCUIT IN SUB
AND NEAR THRESHOLD REGION

CONTENTS
 INTRODUCTION
 CMOS LOGIC IN NEAR-
THRESHOLD REGIME
 DESIGN AND ANALYSIS OF COMPLEX
CIRCUIT IN NEAR-THRESHOLD REGIME
 ANALYSIS OF REVERSIBLE COMPUTING
IN SUB-THRESHOLD REGIME
 CONCLUSION
 FUTURE SCOPES
 REFERENCES

NEED FOR LOW POWER VLSI
DESIGN
 Power Constraint
 Portability
 Battery life
 Sleeker devices
 Reduction in
Packaging and
Cooling costs.
 Better Digital noise
immunity,
 Environmental
concerns.

SOURCES OF POWER
DISSIPATION
Dynamic
power
consumption
Leakage
current
Short-
circuit
current

OUR PROPOSED
APROACHES
 VOLTAGE SCALING
 SUB-THRESHOLD
OPERATION
 NEAR-THRESHOLD
OPERATION
 REVERSIBLE COMPUTING

SUB-THRESHOLD OPERATION
 In sub-threshold regime,
Gate-to-Source Voltage is
less than Threshold Voltage
(Vgs < Vth)
 In digital circuits, sub-
threshold conduction is
generally viewed as a
parasitic leakage in a state
that would ideally have no
current.
 In micro-power analog
circuits, on the other hand,
weak inversion is an
efficient operating region,
and sub-threshold is a
useful transistor mode
around which circuit
functions are designed.

NEAR THRESHOLD
OPERATION
 In near-threshold operation, devices are operated at
or near their threshold voltage (Vth).
 Reduction in supply voltage (Vdd) from 1.1V to
400-500mV.
Vdd should remain as close to threshold
voltage(Vth) as possible.
 Near Threshold Computing’s
 Advantages: 10X energy efficiency gains, more
favorable performance
Disadvantages : prone to performance variation
, logic failures

REVERSIBLE LOGIC
COMPUTING
 Reversible logic supports the process of running the
system both forward and backward.
 No information about the computational states can
ever be lost, so we can recover any earlier stage by
computing backwards or un-computing the results.
 logical reversibility.
 Ability to reduce the power dissipation

CMOS LOGIC
 CMOS stands for
Complementary Metal
Oxide
 The figure on the right
shows a basic inverter
circuit using CMOS
Logic
 CMOS logic
incorporates a
combination of PMOS
and NMOS
 Pull-up network
 Pull-down network

BASIC MODEL OF MOSFET IN
NEAR-THRESHOLD REGIME
21
[( | |)] ]
2
P P SG T SD SD
P
WI K V V V V
L
 
   
 

The I–V characteristics of the near-threshold
PMOS device can be expressed by:
Where,KP is transconductance ,W/L is
the aspect ratio of PMOS and VSG,
VSD, and VT are source to gate, source
to drain, and threshold voltage of
pMOS, respectively.
P
V
R
I


1
[ | |]P DD T
P
R
WK V V
L
 
 
 
 


The exoression of resistance is given by,
Substituting the value of Ip from equation ,we get

ENERGY DISSIPATION OF CMOS
INVERTER IN NEAR-THRESHOLD
REGIME
2
0
T
V
E dt
R

 
DD OHV V V  
and
The energy dissipation in the above-mentioned near-threshold CMOS
based inverter during the charging process can be calculated as
Where
,
1 L
T
RC
OH DDV V e
 
 
 
 
  
 
 
L
T
RC
DDV V e
 
 
 
 
Therefore,
22
L
T
RCDDV
E T e
R
 
 
 
 
 
 
 

VOLTAGE SWING OF CMOS
INVERTER
swing OH OLV V V 
The equation of voltage swing for CMOS inverter can be given as,
swing DDV V V V  
2
1 2 L
T
RC
swing DDV V e
 
 
 
 
  
 
 
Where VOH is high output voltage and VOL is low output voltage

DESIGN AND ANALYSIS OF
COMPLEX CIRCUIT IN NEAR-
THRESHOLD REGIME
 The figure on the right
shows the basic
building block of 1-bit
CLA adder
 We have cascaded this
basic circuit to make 4-
bit, 8-bit and 16-bit
adders.
 We have analyzed
those circuits’ Voltage
swing and Power
dissipation with respect
to various metrics, like
variation in supply
voltage, load, temp.,
freq. and aspect ratio.

STRUCTURE AND WORKING OF A
4-BIT CARRY LOOK AHEAD
ADDER
Structure Simulation

EFFECT OF TEMPERATURE
VARIATION ON
Voltage Swing Power Dissipation

EFFECT OF VOLTAGE SUPPLY
VARIATION ON

EFFECT OF LOAD VARIATION
ON

EFFECT OF FREQUENCY
VARIATION ON

EFFECT OF ASPECT RATIO
VARIATION ON

REVERSIBLE COMPUTING
Time invertible
One to one mapping
Physical reversibility
Logical reversibility
Applications
REVERSIBLE
PHYSICAL LOGICAL

FREDKIN GATE
Universal
Reversible
Ex-conservation of
mass
Precision

SIMULATION RESULT
INPUTS:A=00001111; B=00110011;
C=01010101

WORKING ON THE FREDKIN GATE
 FOR INPUT WHERE A=1; FOR INPUT WHERE
A=0;
TRANSISTOR LEVEL IMPLEMENTATION OF FREDKIN GATE

MODELLING OF FREDKIN
GATE
Equivalent Resistances Of Each Branch
Current In Each Branch:
Output High And Low Voltage:

GATE
Voltage Swing (Maximum)
< 0

GATE
Power Consumed (Minimum)
Power in left branch: Power =
Power in right branch: Power =
P =
VDD=50mV
+
-

AVERAGE POWER Vs SUPPLY
VOLTAGE
Similar trend
Follows a
decrease then
increase
Error % =
1.91e01% at
200mv

AVERAGE POWER Vs
TEMPERATURE AT FIXED
SUPPLY VOLTAGE
Voltage 250 mv.
Similar trend
Increasing
Error % = 1.64e01%
at -20 degree
celsius

AVERAGE POWER VS
LOAD
Load increase from
10ff to 50ff
Trend nearly
increasing
Similar trend
Error %=7.37% at
10ff

AVERAGE POWER VS
FREQUENCY
Frequency increase
from 1khz to 1 mhz
Similar trend
Increasing
Error % = 3.38% at
1 mhz

CONCLUSION
In this project, the EKV model of MOSFET is used
as standard. The power consumption of near-
threshold CMOS logic CLA and Fredkin gate
structures in the sub-threshold region is calculated
for a 22nm MOSFET and a comparative analysis of
the power consumption and voltage swing is also
presented. The analysis is based on the result of the
simulation and the modeling of the respective
structures. Also, voltage swings have been
calculated on various kinds of inputs. And finally the
resulting noise margin is calculated in the aforesaid
sub-threshold condition.

FUTURE SCOPE
Building Automation
Ubiquitous
Environmental
Monitoring
Biomedical
Implants

REFERENCES
[1] A 65 nm Sub- Microcontroller With Integrated SRAM and Switched Capacitor
DC-DC Converter Joyce Kwong, Student Member, IEEE, Yogesh K. Ramadass,
Student Member, IEEE, Naveen Verma, Student Member, IEEE, and Anantha P.
Chandrakasan, Fellow, IEEE
[2] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using
a minimum energy design methodology,” IEEE J. SolidState Circuits, vol. 40,
no. 1, pp. 310–319, Jan. 2005.
[3] B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D.
Blaauw, and T. Austin, “A 2.60 pJ/Instsubthreshold sensor processor for optimal
energy efficiency,” in Symp. VLSI Circuits Dig., Jun. 2006, pp. 154–155.
[4] S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J.
Olson, L. Nazhandali, T. Austin, D. Sylvester, and D. S. Blaauw, “Performance
and variability optimization strategies in a sub-200 mV, 3.5 pJ/inst, 11
nWsubthreshold processor,” in Symp. VLSI Circuits Dig., Jun. 2007, pp. 152–
153.
[5] Power Reduction in CMOS Sub-threshold Dual Mode logic circuits by Power
Gating Celine Elsa Jose1 , B Kousalya2 1 (ME VLSI Design, Department of
ECE, HIT, Anna University, India) 2 (Department of ECE, HIT, Anna University,
India)
[6]Introduction to Reversible Logic Gates & its Application Prashant .R.Yelekar
(M.Tech) YCCE, Nagpur Prof. Sujata S. Chiwande Lecturer YCCE, Nagpur
published at 2nd National Conference on Information and Communication

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