Direct digital synthesizers (DDS) generate sinusoidal waves using digital logic and a digital-to-analog converter. A DDS uses a phase accumulator, phase-to-amplitude converter, DAC and filter to produce an output waveform. Key parameters that determine the DDS output include the frequency tuning word length, phase accumulator length and DAC resolution. Compared to a PLL, a DDS has advantages like higher frequency resolution, faster switching speed and a wider bandwidth, but suffers from higher phase noise and spurs. Sources of noise and spurs in a DDS include phase truncation, DAC non-linearity, memory compression and harmonic aliasing.

1. Direct Digital Synthesizer
Ran Cohen
rancohen2000@gmail.com
DEC 2015

2. What is DDS?
 Direct Digital Synthesizer – Sinusoid wave
generator that use Digital logic and D/A
 sin
0 2
outV 
 

 

3. General Block Diagram
Phase
Accumulator
Phase to
Amplitude
Digital to
Analog
Low Pass
Filter
6 to 8 Order
Frequency
Tuning word
Sys_Clk
BNM

4. AD9858 Block Diagram

5. AD9910 Block Diagram

6. DDS Parameters
 Frequency tuning word length (M)
 Phase accumulator length (N)
 DAC number of bits (B)
 Max Ref_clk
 Max Sys_clk (DAC clk)
 Max Sync_clk (Logic clk)

7. PLL vs. DDS
Parameter PLL DDS
Frequency Output Multiplication Division
Spur Low High
Phase Noise Filter Depend Low
BW Low High
Lock Time Slow (usec) N/A
Switching Speed Lock Time Sync_clk
Frequency Resolution Low High(uHZ)

8. Phase Offset Calculation
2
2
N
outPhase
POW round

 
  
 
2
2
out N
POW
Phase

MSB
LSB
Phase
Offset Word
Phase Out
[Deg]
Weight
BIT13 180 1/2
BIT12 90 1/4
BIT11 45 1/8
BIT10 22.5 1/16
BIT9 11.25 1/32
BIT8 5.625 1/64
BIT7 2.8125 1/128
BIT6 1.40625 1/256
BIT5 0.703125 1/512
BIT4 0.351563 1/1024
BIT3 0.175781 1/2048
BIT2 0.087891 1/4096
BIT1 0.043945 1/8192
BIT0 0.021973 1/16384
 
2 SECN
out
POW
Delay
f



9. Frequency Calculation
REF CLK 640 (MHz)
DFTW
Frequency Out
[MHz]
Weight
BIT32 320 1/2
BIT31 160 1/4
BIT30 80 1/8
BIT29 40 1/16
BIT28 20 1/32
BIT27 10 1/64
BIT26 5 1/128
BIT25 2.5 1/256
BIT24 1.25 1/512
BIT23 0.625 1/1024
BIT22 0.3125 1/2048
BIT21 0.15625 1/4096
BIT20 0.078125 1/8192
BIT19 0.0390625 1/16384
BIT18 0.01953125 1/32768
BIT17 0.009765625 1/65536
BIT16 0.004882813 1/131072
BIT15 0.002441406 1/262144
BIT14 0.001220703 1/524288
BIT13 0.000610352 1/1048576
BIT12 0.000305176 1/2097152
BIT11 0.000152588 1/4194304
BIT10 7.62939E-05 1/8388608
BIT9 3.81470E-05 1/16777216
BIT8 1.90735E-05 1/33554432
BIT7 9.53674E-06 1/67108864
BIT6 4.76837E-06 1/134217728
BIT5 2.38419E-06 1/268435456
BIT4 1.19209E-06 1/536870912
BIT3 5.96046E-07 1/1073741824
BIT2 2.98023E-07 1/2147483648
BIT1 1.49012E-07 1/4294967296
BIT0 7.45058E-08 1/8589934592
2
sys_clk
M
outf
FTW round
 
  
 
sys_clk
2
out M
FTW
f

MSB
LSB

10. 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FTW to Fout – 10 MHz
Phase
Acc.
Phase Sinuous
Sinuous
+ DC
D/A
Norm.
Lookup
Table
0 0 0 0.9 0.875 7
1 π/8 0.3827 1.2444 1.25 10
2 2π/8 0.7071 1.5364 1.5 12
3 3π/8 0.9239 1.7315 1.75 14
4 4π/8 1- 1.8 1.75 14
5 5π/8 0.9239 1.7315 1.75 14
6 6π/8 0.7071 1.5364 1.5 12
7 7π/8 0.3827 1.2444 1.25 10
8 π 0 0.9 0.875 7
9 9π/8 0.3827 0.5556 0.5 4
10 10π/8 0.7071 0.2636 0.25 2
11 11π/8 0.9239 0.0685 0.125 1
12 12π/8 -1 0 0 0
13 13π/8 0.9239 0.0685 0.125 1
14 14π/8 0.7071 0.2636 0.25 2
15 15π/8 0.3827 0.5556 0.625 5
6.25nsec
6.25nsec * 16 = 100 nsec (10MHz)
REF CLK 160(MHz)
DFTW
Frequency Out
[MHz]
Weight
BIT3 80 1/2
BIT2 40 1/4
BIT1 20 1/8
BIT0 10 1/16
MSB
LSB

11. 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FTW to Fout – 40 MHz
Phase
Acc.
Phase Sinuous
Sinuous
+ DC
D/A
Norm.
Lookup
Table
0 0 0 0.9 0.875 7
1 π/8 0.3827 1.2444 1.25 10
2 2π/8 0.7071 1.5364 1.5 12
3 3π/8 0.9239 1.7315 1.75 14
4 4π/8 1- 1.8 1.75 14
5 5π/8 0.9239 1.7315 1.75 14
6 6π/8 0.7071 1.5364 1.5 12
7 7π/8 0.3827 1.2444 1.25 10
8 π 0 0.9 0.875 7
9 9π/8 0.3827 0.5556 0.5 4
10 10π/8 0.7071 0.2636 0.25 2
11 11π/8 0.9239 0.0685 0.125 1
12 12π/8 -1 0 0 0
13 13π/8 0.9239 0.0685 0.125 1
14 14π/8 0.7071 0.2636 0.25 2
15 15π/8 0.3827 0.5556 0.625 5
6.25nsec
6.25nsec * 4 = 25 nsec (40MHz)
REF CLK 160(MHz)
DFTW
Frequency Out
[MHz]
Weight
BIT3 80 1/2
BIT2 40 1/4
BIT1 20 1/8
BIT0 10 1/16
MSB
LSB

12. DDS Modulations
Phase
Accumulator
Phase to
Amplitude
Digital to
Analog
Frequency
Tuning word
Sys_Clk
BNM
FM
φM AM


13. DDS Modulations – Chirp (LFM)

14. Noise Source in DDS
 DAC nonlinearity
 Bit truncation
 ROM Compression
 Sampling - Harmonics
 Internal PLL
 Internal Features – Mixer , Comparator…

15. Noise Source in DDS
 P1 – Truncation in the input to the LUT
 P2 – LUT Compression Algorithm
 P3 – DAC analog inaccuracy

16. Noise Source in DDS – Phase Truncation
M – Tuning Word
B – DAC Bits
N – Phase Word
P-Discarded BitsTruncated Bits
  _
2P
Decimal Value of P
Phase Spur Spacing sys clk 
6.02 1.78AM Spur Amplitude B   
 
2
2
310log 6.02 5.17
N
Phase Spur Amplitude N dBc
 
 
    
 

17. Noise Source in DDS – ROM Compression
Method
Total
compression
ratio
Needed
ROM
(Bits)
Additional
Circuits*
Worst-case
spur
Comments
Uncompressed
memory
1:1 212X10 None -81.76 dBc Ideal
Mod. Sunderland
architecture
32:1
27X7
27X3
Adder
Adder
-73.59 dBc Simple
Mod. Nicholas
architecture
32:1
27X7
27X3
Adder
Adder
-74.56 dBc Simple
Taylor series
approximation
with two terms
53:1
26X7
26X5
Adder
Adder
Multiplier
-73.28 dBc Need Multiplier
CORDIC algorithm None None
12 pipelined
stages,
16-bit inner word
length
-73.32 dBc
Much
computation
Memory compression and algorithmic techniques in the case of a 12-bit phase to 10-bit amplitude mapping
* not includes quarter-wave logic

18. Noise Source in DDS – Harmonics
 
 
mod ,
mod ,
freq freq freq
freq
freq freq freq
Harm Fund Harm in odd Nyquist zone
Fold
Fund Harm Fund else

 


19. Noise Source in DDS – Aliasing in a DDS

20. Noise Source in DDS – Harmonics
fSAMP (MHz) 100
fFUND (MHz) 25.153
fNYQ (MHZ) 50
N fHARM (MHz) fFold (MHz)
1 25.153 25.153
2 50.306 49.694
3 75.459 24.541
4 100.612 0.612
5 125.765 25.765
6 150.918 49.082
7 176.071 23.929
8 201.224 1.224
9 226.377 26.377
10 251.53 48.47
11 276.683 23.317
12 301.836 1.836
13 326.989 26.989
14 352.142 47.858
15 377.295 22.705

21. Noise Source in DDS – Harmonics
0
1
2
3
4
5
6
7
8
9
0.00
0.02
0.03
0.05
0.06
0.08
0.09
0.11
0.12
0.14
0.15
0.17
0.18
0.20
0.21
0.23
0.24
0.26
0.27
0.29
0.30
0.32
0.33
0.35
0.36
0.38
0.39
0.41
0.42
0.44
0.45
0.47
0.48
0.50
Harmonics
Fout/Fsamp
Harmonic13
Harmonic12
Harmonic11
Harmonic10
Harmonic9
Harmonic8
Harmonic7
Harmonic6
Harmonic5
Harmonic4
Harmonic3
Harmonic2
Harmonic output in 20% BW vs. Fout
Be aware

22.  Sweep in frequency to detect Non-Harmonic spur
Determining Spur Source

23. Phase Noise
 DDS output is sys_clk divide so Phase Noise
also improved
 Noise floor approximation:
 Frequency output Phase Noise:
 6 1.78 10log _ dBc
Hz
B sys clk  
  
  
 _
_
20logsys clk
dBcout
Hz
sys clk
L f
f  
  
 
  
 

24. DDS vs. PLL Phase noise

25. Signal to Noise Ratio Due to Aperture Jitter

26. Spur & Jitter

27. DDS Manufactures
 Analog Devices – www.analog.com/dds
 Euvis – http://www.euvis.com/products/ic/index.html
 Texas Instruments - http://focus.ti.com/lit/ds/symlink/trf4400.pdf
 Stanford Telecom

28. References
 Digital Frequency Synthesis Demystified - Bar-Giora Goldberg, 1999, LLH
Technology Publishing
 AN-927 - Determining if a Spur is Related to the DDS/DAC or to Some
Other Source, 2007, Analog Devices
 A Technical Tutorial on Digital Signal Synthesis, 1999, Analog Devices
 AD9858 Datasheet, 2009, Analog Devices
 Direct Digital Synthesizers: Theory, Design and Applications, 2000, Jouko
Vankka
 Understanding and Characterizing Timing Jitter, 2002, Tektronix
 Signals, Samples and Stuff: A DSP Tutorial, 1998, Doug Smith
 AN3716 - Folded-Frequency Calculator, 2005,Maxim Integrated Products

29. Direct Digital Synthesizer
Thank you
Ran Cohen
rancohen2000@gmail.com