IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Total Harmonic Distortion Alleviation by using Shunt Active FilterIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Comparators are basic building elements for designing modern analog and mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents a design for an on chip high-speed dynamic latched comparator for high frequency signal digitization. The dynamic latched comparator consists of two cross coupled inverters comprising a total of 9 MOS transistors. The measured and simulation results show that the dynamic latched comparator design has higher speed, low power dissipation and occupying less active area compared to double tail latched and preamplifier based clocked comparators. A new fully dynamic latched comparator which shows lower offset voltage and higher load drivability than the conventional dynamic latched comparators has been designed. With two additional inverters inserted between the input-stage and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented.
Total Harmonic Distortion Alleviation by using Shunt Active FilterIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
This paper proposed a new sparce matrix converter with Z-source network to provide unity voltage transfer ratio. It is an ac-to-ac converter with diode-IGBT bidirectional switches. The limitations of existing matrix converter like higher current THD and less voltage transfer ratio issues are overcome by this proposed matrix converter by inserting a Z-source. Due to this Z-source current harmonics are totally removed. The simulation is performed for different frequencies. The simulation results are presented to verify the THD and voltage transfer ratio and compared with the existing virtual AC/DC/AC matrix converter. The experimental output voltage amplitude can be varied with the variable frequencies.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Comparators are basic building elements for designing modern analog and mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents a design for an on chip high-speed dynamic latched comparator for high frequency signal digitization. The dynamic latched comparator consists of two cross coupled inverters comprising a total of 9 MOS transistors. The measured and simulation results show that the dynamic latched comparator design has higher speed, low power dissipation and occupying less active area compared to double tail latched and preamplifier based clocked comparators. A new fully dynamic latched comparator which shows lower offset voltage and higher load drivability than the conventional dynamic latched comparators has been designed. With two additional inverters inserted between the input-stage and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
In this paper the multicarrier pulse width modulation (MCPWM) with multi value DC voltage source multilevel inverter is presented. These MLI’s are suitable in high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum. Seven level inverter is simulated using MATLAB/Simulink. The use of Photovoltaic Cell as a DC source for the multilevel Inverter is proposed here.
A novel voltage reference without the operational amplifier and resistorsIJRES Journal
novel voltage reference has been proposed and simulated using a 0.18μm CMOS process in
this paper. A near-zero temperature coefficient voltage is achieved in virtue of the bias voltage subcirciut which
consists of two MOSFETs operating in the saturation region. The kind of bias voltage subcirciut is used to
adjust the output voltage and compensate the curvature. The output voltage is equal to the extrapolated
threshold voltage of a MOSFET at absolute zero temperature, which was about 591.5 mV for the MOSFETs we
used. The power supply rejection ratio (PSRR) is improved with three feedback loops. Although the output
voltage fluctuates with process variation, the circuit can monitor the process variation in MOSFET threshold
voltage. The simulation results show that the line regulation is 0.75 mV/V in a supply voltage range from 1.6 V
to 3.1 V and the temperature coefficient is around 10.8 ppm/℃ to 28.5 ppm/℃ at 9 different corners in a
temperature range from -20℃ to 120 ℃.
The PSRR is -70 dB at 100Hz with a supply voltage at 1.8 V, and the
layout size is 0.012mm2. The results of simulation and post layout simulation are almost the same.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
Enhancing phase margin of ota using self biasingelelijjournal
In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 μm CMOS technology confirm the theoretical analysis and exhibits 478μA linear input/output current swing and a
phase-margin enhancement of 12o for the proposed current mirror and amplifier compared to the conventional circuits, respectively
A New Configuration of Asymmetric Multilevel Converter to Maximize the Number...IJMTST Journal
The multilevel converters are increasingly becoming popular because of its high power applications. This research paper describes about the new structure that can produce increased number of output voltage waveform using a single source and reduced number of power electronic components. In designing a multilevel converter, the power electronic switches play a very imperative role as it describes the installation area, cost, configuration complexity and may more things that play a significant role while designing. The prime function of multilevel converter is to abolish total harmonic distortion and to incorporate desired ac voltage from several separate dc sources. Each level consists of H-Bridge converter units. High efficiency, high voltage capability, lower switching losses are its prime advantages. A multilevel power converter structure can be introduced as an alternative in medium voltage and high power situations. This structure not only achieves high power ratings but also empower the use of renewable energy sources. It finds its basic application in adjustable speed drives, Static Compensator (STATCOM).
SIMULATION ANALYSIS OF CLOSED LOOP DUAL INDUCTOR CURRENT-FED PUSH-PULL CONVER...Journal For Research
The current electronic devices require DC power source, which is taken from a battery or DC power supply. DC-DC converter is utilized to get regulated dc voltage from unregulated one. Switched mode power supply (SMPS) are commonly used in industrial applications, because of more advantages compared to linear power supply. In SMPS we have isolated and non-isolated converters, where isolated converters are frequently used, in order to get more voltage with multiple outputs. So among different isolated converters, push-pull converter is chosen for micro converter applications to obtain high voltage conversion ratio by using HF transformer, due to their better utilization of transformer. New methodology of control is implemented for making ZVS and ZCS at same time and to reduce the number of switches in the secondary side of dual inductor CFPP converter, which is a voltage doubler circuit. This becomes the solution for problem identification. Thus this converter with soft-switching reduces the switching losses.The current-fed push-pull converters are used in many applications like photo-voltaic (PV) power converters for boosting the output voltage. Push-pull converter is chosen for micro converter applications, to obtain high voltage conversion ratio by using high frequency (HF) transformer, due to their better utilization of transformer. This deals with the design of dual inductor CFPP converter, where zero voltage switching (ZVS) and zero current switching (ZCS) is achieved for the primary side of the converter by using secondary switches. Primary side switches are controlled by closed loop control topology. The secondary side is made with voltage doubler to obtain high voltage. Open loop and closed loop control of dual inductor current fed push pull converter simulation is finished by MATLAB/SIMULINK and their outcomes are analyzed.
This paper deals with the design of cascaded 11 level H- bridge inverter. It includes a comparison between the 11 level H-bridge and T-bridge multilevel inverter. The cascaded inverter of higher level is a very effective and practical solution for reduction of total harmonic distortion (THD).These cascaded multilevel inverter can be used for higher voltage applications with more stability. As the level is increased the output waveform becomes more sinusoidal in nature. The inverter is designed using multicarrier sinusoidal pulse width modulation technique for generating triggering pulses for the semiconductor switches used in the device. Through this paper it will be proved that a cascaded multilevel H-bridge topology has higher efficiency than a T-bridge inverter, as whichever source input voltage is provided since input is equal to the output voltage. In T-bridge inverter, the output obtained is half of the applied input, so efficiency is just half as compared to H-bridge. The output waveform is distorted and has higher THD. The simulation is performed using MATLAB /Simulink 2013 software.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study of flooding based d do s attacks and their effect using deter testbedeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
In this paper the multicarrier pulse width modulation (MCPWM) with multi value DC voltage source multilevel inverter is presented. These MLI’s are suitable in high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum. Seven level inverter is simulated using MATLAB/Simulink. The use of Photovoltaic Cell as a DC source for the multilevel Inverter is proposed here.
A novel voltage reference without the operational amplifier and resistorsIJRES Journal
novel voltage reference has been proposed and simulated using a 0.18μm CMOS process in
this paper. A near-zero temperature coefficient voltage is achieved in virtue of the bias voltage subcirciut which
consists of two MOSFETs operating in the saturation region. The kind of bias voltage subcirciut is used to
adjust the output voltage and compensate the curvature. The output voltage is equal to the extrapolated
threshold voltage of a MOSFET at absolute zero temperature, which was about 591.5 mV for the MOSFETs we
used. The power supply rejection ratio (PSRR) is improved with three feedback loops. Although the output
voltage fluctuates with process variation, the circuit can monitor the process variation in MOSFET threshold
voltage. The simulation results show that the line regulation is 0.75 mV/V in a supply voltage range from 1.6 V
to 3.1 V and the temperature coefficient is around 10.8 ppm/℃ to 28.5 ppm/℃ at 9 different corners in a
temperature range from -20℃ to 120 ℃.
The PSRR is -70 dB at 100Hz with a supply voltage at 1.8 V, and the
layout size is 0.012mm2. The results of simulation and post layout simulation are almost the same.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
Enhancing phase margin of ota using self biasingelelijjournal
In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 μm CMOS technology confirm the theoretical analysis and exhibits 478μA linear input/output current swing and a
phase-margin enhancement of 12o for the proposed current mirror and amplifier compared to the conventional circuits, respectively
A New Configuration of Asymmetric Multilevel Converter to Maximize the Number...IJMTST Journal
The multilevel converters are increasingly becoming popular because of its high power applications. This research paper describes about the new structure that can produce increased number of output voltage waveform using a single source and reduced number of power electronic components. In designing a multilevel converter, the power electronic switches play a very imperative role as it describes the installation area, cost, configuration complexity and may more things that play a significant role while designing. The prime function of multilevel converter is to abolish total harmonic distortion and to incorporate desired ac voltage from several separate dc sources. Each level consists of H-Bridge converter units. High efficiency, high voltage capability, lower switching losses are its prime advantages. A multilevel power converter structure can be introduced as an alternative in medium voltage and high power situations. This structure not only achieves high power ratings but also empower the use of renewable energy sources. It finds its basic application in adjustable speed drives, Static Compensator (STATCOM).
SIMULATION ANALYSIS OF CLOSED LOOP DUAL INDUCTOR CURRENT-FED PUSH-PULL CONVER...Journal For Research
The current electronic devices require DC power source, which is taken from a battery or DC power supply. DC-DC converter is utilized to get regulated dc voltage from unregulated one. Switched mode power supply (SMPS) are commonly used in industrial applications, because of more advantages compared to linear power supply. In SMPS we have isolated and non-isolated converters, where isolated converters are frequently used, in order to get more voltage with multiple outputs. So among different isolated converters, push-pull converter is chosen for micro converter applications to obtain high voltage conversion ratio by using HF transformer, due to their better utilization of transformer. New methodology of control is implemented for making ZVS and ZCS at same time and to reduce the number of switches in the secondary side of dual inductor CFPP converter, which is a voltage doubler circuit. This becomes the solution for problem identification. Thus this converter with soft-switching reduces the switching losses.The current-fed push-pull converters are used in many applications like photo-voltaic (PV) power converters for boosting the output voltage. Push-pull converter is chosen for micro converter applications, to obtain high voltage conversion ratio by using high frequency (HF) transformer, due to their better utilization of transformer. This deals with the design of dual inductor CFPP converter, where zero voltage switching (ZVS) and zero current switching (ZCS) is achieved for the primary side of the converter by using secondary switches. Primary side switches are controlled by closed loop control topology. The secondary side is made with voltage doubler to obtain high voltage. Open loop and closed loop control of dual inductor current fed push pull converter simulation is finished by MATLAB/SIMULINK and their outcomes are analyzed.
This paper deals with the design of cascaded 11 level H- bridge inverter. It includes a comparison between the 11 level H-bridge and T-bridge multilevel inverter. The cascaded inverter of higher level is a very effective and practical solution for reduction of total harmonic distortion (THD).These cascaded multilevel inverter can be used for higher voltage applications with more stability. As the level is increased the output waveform becomes more sinusoidal in nature. The inverter is designed using multicarrier sinusoidal pulse width modulation technique for generating triggering pulses for the semiconductor switches used in the device. Through this paper it will be proved that a cascaded multilevel H-bridge topology has higher efficiency than a T-bridge inverter, as whichever source input voltage is provided since input is equal to the output voltage. In T-bridge inverter, the output obtained is half of the applied input, so efficiency is just half as compared to H-bridge. The output waveform is distorted and has higher THD. The simulation is performed using MATLAB /Simulink 2013 software.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study of flooding based d do s attacks and their effect using deter testbedeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Study of permeation of gases through ceramic supported polymeric and zeolite ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A novel single phase cascaded h-bridge inverter with new cell configuration a...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Hci and its effective use in design and development of good user interfaceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of digital video watermarking scheme using matlab simulinkeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
Design of up converter at 2.4GHz using Analog VLSI with 22nm Technologyijsrd.com
Up converter has been designed in 0.18μm technology at 2.4GHz Frequency. I am trying to design up converter with 22nm technology. The problems related to Up converter is often difficult to solve, and may allow different solutions, so the choice is not always simple for those engineers and professionals who are not trained in Analog VLSI. The optimal solution of Problem of Power dissipation is usually a mix of solutions for a specific situation. In such a situation, it is necessary to identify that problem and propose different solutions. Initially the thesis gives a basic idea of up converter and also about CMOS. Later on it tries to simulate the basic gates. And a detailed insight is provided with the help of a simulation using Tspice Simulator. Power Dissipation in 0.18μm Technology using current mirror gilbert mixer is 4.5 mW and in 0.25μm Technology using current mirror gilbert mixer is 3.5mW and Power Dissipation in 0.18μm Technology is 8.1mW using Gilbert mixer. Now I am trying to design mixer with low power dissipation with 22nm technology which is recent technology.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Analysis and Improved Operation of PEBB Based 5-Level Voltage Source Convert...IJMER
The paper presents the power-electronic devices are increasing in several applications, and
power-electronic building blocks (PEBBs) are a strategic concept to increase the reliability of the
power-electronic converters and to minimize their cost. Magnetic elements, such as zigzag
transformers, phase-shifted transformers (PST), or zero-sequence blocking transformers (ZSBT), are
used to interconnect the PEBBs. In this paper, by using 5-level voltage source converter the operation
of multi-pulse converters will be analyzed, describing the harmonic cancellation and minimization
techniques that could be used in these multi-pulse converters, focusing on the power-electronics flexible
ac transmission systems devices installed at the NYPA Marcy substation. In order to improve the
dynamic response of this system, the use of selective harmonic elimination modulation is proposed and
implemented
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study and implementation of comparator in cmos 50 nm technologyeSAT Journals
Abstract This paper describes the comparator circuits used in FLASH Analog to digital converter (ADC). The performance of FLASH ADC is greatly influenced by the choice of comparator. In this paper, first a single ended “Threshold Inverter Quantizer” (TIQ) is presented. The TIQ comparator is based on a CMOS inverter cell, in which voltage transfer characteristics (VTC) are changed by systematic transistor sizing. However, TIQ comparator is very sensitive to power supply noise. Another comparator circuit presented in this paper is “Two stage open loop comparator”. It is implemented in 50 nm CMOS Technology. Pre-simulation of comparator is done in LT-Spice and post layout simulation is done in Microwind 3.1. Keywords: CMOS, Comparator, TIQ (Threshold Inverter Quantizer), LT-Spice.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Multi Carrier based Multilevel Inverter with Minimal Harmonic DistortionIJPEDS-IAES
This paper presents performance features of Asymmetric Cascaded
Multilevel inverter. Multilevel inverters are commonly modulated by using
multicarrier pulse width modulation (MCPWM) techniques such as phaseshifted
multicarrier modulation and level-shifted multicarrier modulation.
Amongst these, level-shifted multicarrier modulation technique produces the
best harmonic performance. This work studies about multilevel inverter with
unequal DC sources using level shifting MCPWM technique. The
Performances indices like Total Harmonic Distortion (THD), number of
switches and DC Sources are considered. A procedure to achieve an
appropriate level shifting is also presented is this paper.
Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter. This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load. Simulation is performed using MATLAB/SIMULINK. Experimental results are presented to validate the effectiveness of the operation of the diode clamped multilevel inverter using field programmable gate array.
Design of A Low Power Low Voltage CMOS OpampVLSICS Design
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 um
technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2 ) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.
Techniques for the Improvement in the Transconductance of a Bulk Driven Ampli...IJERA Editor
This paper proposed methods for the improvement of transconductance in the bulk driven operation amplifier.
Here we are using four technologies for the enhancement of transconductance. First modifies the
transconductance with the help of active load; second uses a differential pair for the modification
transconductance, while third is the proposed bulk-driven input stages with modified low voltage cascode
biasing scheme whereas last is the bulk driven input stage with enhanced effective transconductance. All the
above methods are used to enhance the transconductance which gets decreased.
Analysis and Design of CMOS Source Followers and Super Source FollowerIDES Editor
The source follower circuit is used as a voltage
buffer and level shifter. It is more flexible level shifter as the
dc value of voltage level can be adjusted by changing aspect
ratio of MOSFETs. It is desired to have low output resistance
for such applications. Source follower can give minimum
output resistance 1/(gm+gmb) with load resistance and channel
resistance tending to infinity. The super source follower is a
circuit formed using negative feedback through another
MOSFET. This offers even reduced output resistance but with
reduced voltage gain as that of source follower.
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1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 03 Special Issue: 12 | ICAESA - 2014 | Jun-2014, Available @ http://www.ijret.org 1
COMPARISON OF PARALLEL SUMMATION AND WEAK INVERSION BASED LOGARITHMIC AMPLIFIER Amrutha Paul1, N.Kayalvizhi2 1ECE Department, Amrita VishwaVidyapeetham, Coimbatore, India 2ECE Department, Amrita VishwaVidyapeetham, Coimbatore, India Abstract Logarithmic amplifier is used for reducing the dynamic range of the input signal. Logarithmic amplifier is implemented using two different techniques. One of the methods is a parallel summation based method and the other one is a weak inversion based method. In parallel summation based method the transistors are maintained in saturation whereas in weak inversion based method the transistors are maintained in weak inversion. Both methods are simulated in 50nm CMOS technology using HSPICE. Considering power, area and dynamic range weak inversion method is more efficient compared to parallel summation method. Keywords: Logarithmic amplifier, Parallel SummationLogarithmic amplifier;WeakInversion;Saturation;MOSFET;
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1. INTRODUCTION A Logarithmic amplifier will convert a nonlinear transducer characteristics into linear characteristics.[1]-[2].A good example of a nonlinear sensor is a thermistor. The exponential Resistance-Temperature characteristics of a thermistor can be linearized with the help of a Logarithmic network. The theory behind this is that when the resistance of a thermistor varies exponentially with change in temperature. This causes the voltage across the thermistor probe to vary exponentially with temperature. So by applying this to a Logarithmic network, the variation of resistance of the thermistor will be linear with the temperature[3]. Logarithmic amplifiers can be realized using different methods. Opamp based Logarithmic amplifiers[4]uses diodes or bipolar transistors in their feedback path to get logarithmic relationship between input voltage and output voltage by exploiting their exponential dependence between current and voltage. Most of the methods have their own advantages and disadvantages. We can use weak inversion MOSFET’s to realize a Logarithmic relationship between input voltage or current and output voltage or current respectively. This method is less power consuming as MOSFET’s are scaled down and also the power supply is also scaled down. Logarithmic amplifiers are used in radio receivers [5],radar signal receivers for reducing the dynamic range of the input signal due to compressive nature of the log function. This paper aims at the comparative study of two important Logarithmic amplifier techniques which can be used to linearize a nonlinear transducer characteristic. This paper is organized into sections as follows. In Section II, Logarithmic amplifiers are discussed in detail; the theory behind parallel summation Logarithmic amplifier and weak inversion Logarithmic amplifiers are also explained. In Section III, some important design considerations are discussed and in Section IV the results and analysis is discussed. Finally the paper is concluded in Section V.
2. LOGARITHMIC AMPLIFIERS
Logarithmic amplifiers are usually constructed with diode or bipolar transistors in the feedback path of an inverting opamp. However its operation is limited to low frequencies. Logarithmic amplifiers are used to linearize a nonlinear input signal or to reduce the range of a signal with large dynamic range. Usually a MOSFET based ASIC design has many advantages like low power consumption, small area, etc. A basic Logarithmic amplifier module consists of a clipping amplifier and a voltage to current converter. So if we cascade this stage repeatedly then we will obtain a more linearized output voltage which will be proportional to the sensed temperature. This output voltage will be given to a dual slope digital converter[6]. The dual slope digital converter is a complex module which provides a digital output corresponding to the temperature sensed. Logarithmic amplifier can be realized using various methods. Here a comparative study of two important methods is done. 1. Parallel Summation based Logarithmic amplifier[6] 2. Weak Inversion based Logarithmic amplifier Both of these methods are discussed in this paper and their transfer functions are plotted. 2.1 Parallel Summation based Logarithmic Amplifiers Parallel Summation method uses MOSFET in saturation. In this region of operation. MOSFET uses square law of Current whereas in Weak Inversion, a MOSFET uses exponential relationship between drain current and gate to source voltage. Usually we use saturated MOSFETs for realization of different circuits. But this will result in high power consumption due to a large supply voltage. So in order to reduce the power consumption weak inversion biased MOSFET’s are a good alternative.
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 03 Special Issue: 12 | ICAESA - 2014 | Jun-2014, Available @ http://www.ijret.org 2
Parallel summation method uses MOSFET’s linear region to
get a linear response. This method is achieved by cascading
n number of gain stages. So by increasing the number of gain
stages we can increase the dynamic range upto which the
response of a signal can be linearized. Parallel summation
based method is realized with a single block consisting of a
gain stage A and a unity gain stage repeated n times to get a
linear characteristics between output and the input.
The Figure1 shows the Parallel Summation based method
Parallel summation method is one of the good methods for
implementing the Logarithmic amplifier using MOSFET’S
biased in saturation. We can reduce the power consumption of
the saturated MOS transistors by using the MOS transistors in
weak inversion.
Vin+
Vin-
Vout+
Vout-
Vdd
Stage1 Stage2 Stage3 Stage4………………Stage N-1 StageN
Fig 1. Parallel Summation Method
MOS transistors in saturation region will satisfy the following
equations
DS GS TH V V -V (1)
2
D n GS TH V V
L
W
I K
(2)
n OX K = C
n (3)
V V GS TH (4)
These equations satisfies the condition for saturation even
though a subthreshold current flows through the MOSFET,
when VGS≥VTH.
2.2 Weak Inversion based Logarithmic Amplifier
The core of the proposed design is an extended translinear
principle proposed by Hart[7].Weak inversion based method
uses MOS biased in weak inversion. Weak inversion biasing
is a new concept introduced in the field of MOSFET’s where
usual biasing is carried out in saturation region. Weak
inversion is realized by making MOSFET’s GS V very much
less than the threshold voltage VTH. The threshold voltage is
obtained by plotting D I vs GS V characteristics and then
extrapolating the curve to x-axis. The intersection of the
curve to the x-axis is the threshold voltage. Also we have to
ensure that DS V 4 T V . When these conditions are met, a
sub-micrometer current will flow through the channel.
This particular situation can be analyzed by the majority
carriers being depleted away from the surface of the substrate.
Thus a region of fixed charges will be created. The density of
minority carriers also increases over time. Thus there is a
current called subthreshold current which was neglected for
years since it was at the submicrometer level. MOS transistors
are usually used with strongly inverted channel where drain
current is at micrometer level whereas in weak inversion we
will use MOS transistors with lightly inverted channel with a
subthreshold current flow, due to diffusion of the charge
carriers. The most important application of MOS in weak
inversion is the reduction in power consumption due to the
scaling of the supply voltage.
As the voltages are scaled down with that of the transistor
size, the subthreshold conduction has become an important.
The reason for this is that the supply voltage was scaled down
continuously for power reduction. But as a result leakage has
been increased very much. The amount of subthreshold
conduction is determined by the threshold voltage. The
threshold voltage also has to be scaled down with the scaling
of supply voltage. This tells us the need of the biasing of
transistors in weak inversion. In MOSFET’s the weak
inversion characteristics is exponential in nature. So to build a
Logarithmic amplifier using MOSFET to linearize the
nonlinear characteristics is quiet easy. After taking
Logarithmic of the exponential characteristics we will get a
linearized curve.
MOSFET’s biased in weak inversion region will satisfy the
equations
e {1- e }
L
W
I = I (V /V )
)
nV
V -V )
(
D S
TH DS T
GS T
(5)
V V
V 3V
V V -V
GS TH
DS
DS GS TH
T (7)
IS is the subthreshold leakage current
Here D I is exponentially related to GS V and
DS V ,where DS V is directly proportional to the gate source
voltage, GS V . Also D I depends on temperature directly in
weak inversion. So at weak inversion also, which is a region
fully avoided has some importance when linearization of the
output of transducers is important. To be specific in case of a
trasducer for e.g. a thermistor, which has an exponential
resistance temperature characteristics, can be linearized by
using a Logarithmic amplifier. The temperature dependence
can be easily compensated by applying translinear
principle[10].
A translinear circuit carries out its function using the
translinear principle. The translinear principle states that in a
closed loop containing an even number of translinear elements
3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Special Issue: 12 | ICAESA - 2014 | Jun-2014, Available @ http://www.ijret.org 3
with the same number of them arranged in clockwise and in
anti-clockwise direction , the product of the currents through
the clockwise translinear elements will be equal to the product
of the currents through the anti-clockwise translinear
elements. The transconductance of the collector current of a
MOS transistor is linearly related to the collector current of
the device. Traditionally translinear circuits have been
realized using bipolar transistors. MOS transistor can also be
used as translinear element when operated in the subthreshold
region.
3. DESIGN AND IMPLEMENTATION
Parallel Summation based circuit and Translinear based
Weak Inversion circuit is implemented in HSPICE tool in
50μm CMOS technology. Parallel Summation based circuit
is given in Figure3 and Weak inversion based circuit is given
in Figure4. The aspect ratios of the transistors for both the
parallel summation based as well as weak inversion based
method is given in table2.
0
M18
VOUT1
M13
M19
M3
VBIAS3
M21
M7
VBIAS4
M21
M4
M15
M6
M1
VOFF
M17
M11
M2
M22
M8
M5
0
VDD
1Vdc
M14
M10
M18
M16
VIN
FREQ = 1M
VAMPL = 500MV
M22
M9
VOUT2
M20
Fig2 Parallel Summation Method
Fig 3 Weak Inversion Method
Simulation of both the circuits are done and the output
transfer characteristics are plotted for both the circuits. Also
transient analysis is done using HSPICE
Table 1 Transistors and their aspect ratios
Methods Transistors W/LRatios
PMOS
μm
NMOS
μm
Parallel
Summation
Based
M9,M10,M21,M22 100/2 _
M1,M2,M3,M4,M5,M6,M7
,M8,M9,M10,M11,M12,M1
3,M14,M15,M16,M17,M18
,M19,M20
_ 50/2
Weak
Inversion
Based
M1
186/1
_
M2,M3,M4 _ 186/1
M6,M7
1.268/1
00
_
M8 _ 50/2
4. RESULTS AND DISCUSSION
Comparison of both the methods is done and the graphical
analysis of the two methods are done using HSPICE
simulator. The comparison results are placed in Table3. Slew
rate of the circuit is measured with and without a current
amplifier at the output of the weakinversion based log
amplifier. It is found that slew rate increases after cascading a
current amplifier. Slew rate before cascading was 0.5v/μs and
after the cascading of the current amplifier was
2.079v/μs.Also a plot of output current vs input current was
plotted with different bias currents as in Figure 6.
Fig 4 Parallel Summation Transfer Characteristics
We can see from Figure6 that when the bias currents are
increased the graph becomes more linear . The bias current is
varied from 1nA to 5nA. Table2and Table3 has the
tabulation for Figure4 and Figure5. In Table2 Vout1 is the
output of stage1 and Vout2 is the output of stage2. In Table3
tabulation for output current vs input current is given. Input
current is varied from 0μA to 100μA.
vdd2
0.7Vdc
R1
vdd1
1Vdc
M7
M5
M2
Iin M3
Ib1
M6 V1
M4
Ib2
V2
0
M8
V1
M1
0
0
0
4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 03 Special Issue: 12 | ICAESA - 2014 | Jun-2014, Available @ http://www.ijret.org 4
Table 2 Parallel Summation based method
VIN (V)
VOUT1 (V)
VOUT2 (V)
10E-3
1.39
1.3946
100E-3
1.38
1.4220
200E-3
1.28
1.4235
300E-3
1.19
1.3453
400E-3
1.13
1.2451
500E-3
1.11
1.1683
600E-3
1.10
1.1249
700E-3
1.10
1.1131
800E-3
1.10
1.1103
900E-3
1.10
1.1183
1000E-3
1.10
1.1065
In Figure5 we can see that the output current vs input current graph is almost a straight line which concludes that the output vs input relation is more linear. Also upto 100μA range the output is linear. Fig 5 Weak Inversion Transfer Characteristic Table 3 Weak Inversion based method
IIN (V)
IOUT (V)
IIN (V)
IOUT (V)
100E-9
73.0409E-9
6E-6
98.3925E-9
200E-9
75.0338E-9
7E-6
99.6842E-9
300E-9
76.7042E-9
8E-6
100.8035E-9
400E-9
78.1372E-9
9E-6
101.7909E-9
500E-9
79.3888E-9
10E-6
102.6744E-9
600E-9
80.4978E-9
20E-6
108.4995E-9
700E-9
81.4919E-9
30E-6
111.9358E-9
800E-9
82.3919E-9
40E-6
114.3959E-9
900E-9
83.2134E-9
50E-6
116.3163E-9
1E-6
83.9685E-9
60E-6
117.8893E-9
2E-6
89.3036E-9
70E-6
119.2163E-9
3E-6
92.6138E-9
80E-6
120.3568E-9
4E-6
95.0022E-9
90E-6
121.3479E-9
5E-6
96.8661E-9
100E-6
122.2138E-9
Fig 6 Iout vs Iin for different biasing currents AC analysis of the weak inversion circuit is also done with and without a current amplifier at the output. Gain was increased while taking the output with the current amplifier. The gain vs frequency plot before cascading a current amplifier is given in Figure7 and after cascading is given in Figure8. Fig 7 Gain vs frequency plot before cascading Fig 8 Gain vs frequency plot after cascading
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 03 Special Issue: 12 | ICAESA - 2014 | Jun-2014, Available @ http://www.ijret.org 5
5. CONCLUSIONS In this paper, a comparison between two Logarithmic amplifier methods is done. It was found that the Logarithmic amplifier in Weak Inversion region has achieved more linearization than the parallel summation Logarithmic amplifier technique which uses MOSFET biased in saturation. By using weak inversion based method the dynamic range of a Logarithmic amplifier can be improved. Also power reduction is achieved using this technique. ACKNOWLEDGEMENTS I convey my sincere regards to my guide Ms.NKayalvizhi who helped me throughout this project.
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