Akram Malak is an Egyptian analog IC designer currently living in Grenoble, France, with over 10 years of experience designing analog and mixed-signal circuits. His experience includes work at ON Semi, Freescale, CEA-LETI, and LIP6 on power management systems for mobile devices, automotive systems, and RF applications. He has a Master's degree from University Paris 6 and engineering degree from University Ain Chams in Egypt.

1. Akram Malak
Analog IC Designer
Address: 9 rue Clément, GRENOBLE, 38000 FRANCE Date of Birth: 01/01/1987
Email: akram.malak.86@gmail.com Marital status: Single
Telephone: +337 62 415834 Nationality: Egyptian
PROFILE:
A motivated analog designer (working on transistor level, cadence environement), having the experience
to work in driver for power transistors, ADC and High frequencies PLL. Strong experience in design
and Layout and chips Test benches. 4 operating chips fabricated and Tested CEA-LETI, Grenoble.
Having also the potential to suggest projects and working on it.
EMPLOYEMENT HISTORY:
-Personal current research:
A) Circuit + System level idea for a DC/DC current mode boost converter. (better efficiency, better cost
and temperature stability), journal article in progress.
B) Ripple free DC to DC inverting voltage converter (charge pump) using normally on transistors (this
product would help any company interested in this subject to open a startup)
1) August 2015- May 2016: Analog IC-Designer, ON Semi, Limerick – Irlande, Application of
power management systems for Mobile systems.
• Design of most of the analog blocs for the part ncp63516t, techno TowerJazz.
A) Design of a ramp oscillator generating the frequencies 3 MHz, 6 MHz … 12 MHz.
B) Design of pre- low pass filter preventing glitches for the ADC of the part.
C) Design of the Capacitor Trim bloc to measure the capacitance of the PID of the part.
D) Design of the Amplifier of the PID of the part.
E) Provide the parameters and the c/cs of the HS and LS switches.
F) Test Benches for the Band Gap, POR ….
• Simulation after Test, Define the error after test for the chip ncd9812.
A) Transient response of a 15 V Power amplifier.
B) Gain / Offset Error for a non-inverting amplifier (15 V).

2. • Design and Simulation of a Fast-Current Comparator for the part NCP69820 with a rising
falling time process / temperature variation less than 1 ns.
• Providing Design Technics, Test Suggestion and Layout advices for Design, Test and Layout
teams for all kind of design projects.
2) June 2014- October 2014: Analog IC-Designer, Freescale Semi conductor, Toulouse –
France, Application of power management systems for car systems.
• Verification of linear regulators.
• Design of a charge pump generating negative voltage. (circuit Design – Transistor level –
Frequency = 10 MHz)
(vision to generate negative voltage equals to the CP supply without using Level Shifter)
• Evaluation of electrical simulator tool detecting the floating nodes.
• Techno: Smart MOS 10 (min length for Nmos: 500 nm).
3) November 2013- April 2014: Analog IC-Designer, LIP6, Paris-France, Application power of
management systems for car systems.
• Design of a DC/DC buck converter. Starting by modeling the system level in
MATLAB/SIMULINK. A macro Model using Cadence is done setting the specifications for each
Analog bloc.
• Circuit design of the analog blocs has been done in transistor level. (Oscillator (Frequency = 2
MHz), Bande Gap, programmable comparator, PWM and amplifiers etc…)
• Techno : AMS 0.35µm HV
4) May 2012- October 2013: Analog IC-Designer, CEA-LETI, Grenoble-France, Application of
power management systems for car systems.
• Driver for power transistors, design of DRIVER analog circuit blocs. Design of Oscillator
frequency (1 MHz), Bande Gap, programmable comparator, Galvanique decoder, buffer,
amplifiers and Temperature detector (Test Bench after fabrication + functional circuit after
TEST). (Design Transistor Level and Layout)
• Techno : AMS CMOS 0.35 µm HV – HOTMOS SOI Fraunhofer 1 µm (Techno Haute
Temperature) - HOTMOS SOI Fraunhofer 350 nm (Techno High Temperature).
• Testing Chips and fabricated ASICS and comparison with the simulation.
• New ideas for a charge pump and a driver for power transistor with the minimum possible
integrated circuits.
• Trials to evaluate high temperature technology by designing an oscillator of hundreds of MHz
with stable performance within Temperature (0° C to 250° C).

3. 5) October 2011-April 2012: Research Engineer for CAD and analog design, LIP6, Paris –
France
• Optimizer for automatic sizing of analog circuits. Using CHAMS tools (possessed by LIP6), we
can compute the transistors widths given the lengths and the currents of transistors as input
parameters and through ELDO we can extract the circuits performances. The optimizer uses an
intelligent global search followed by a Simplex of type Nelder-Mead. The optimization loop is
tested by a MILLER amplifier having linear specifications (Gain, Unity gain frequency…) and
non linear (input noise@ 1 Hz, input noise @ unity gain frequency ….) in collaboration with
CEA DAM.
• Journal article : http://www.sciencedirect.com/science/article/pii/S01679260140001827
• Techno: AMS 0.35µm – AMS CMOS 130 nm – CMOS 65 nm
6) 2009: Designer for ∑-Δ modulator for PLL high frequency, Application (SATA) for radio
frequency
• Project supported by Si-Ware Systems, SWS Egypt. My work concerned the design of the bloc Σ-Δ.
The bloc Σ-Δ is of 3rd order, realized with a single loop topology to reduce spurs at low frequency
taking into account the stability problem. The used simulation tools: MATLAB, Modelsim and
Cadence. The system output frequency is 3 GHz. (Design Transistor Level and Layout)
• Conference article : http://www.thinkmind.org/index.php?
view=article&articleid=spacomm_2014_1_30_20045
• Techno: tsmc CMOS 130 nm radio frequency
Techincal Summary :
1) SYSTEM LEVEL LANGUAGE
C, C++, MATLAB, SIMULINK, SYSTEM-C.
2) TOOLS AND ANALOG/DIGITAL DESIGN
Cadence, VHDL, VHDL AMS, Questa, ELDO, PSPICE.
3) ENVIRONEMENT
Linux, Windows.
Education :
2011 Getting Master II SESI : Systèmes Electroniques et Systèmes Informatiques- (degree
very good) - Laboratory LIP 6, University Paris 6 – Pierre et Marie Curie.
2009-2010 Getting du Master I: Electronic and Telecommunication - (degree very good), University
Aïn Chams, Cairo.

4. 2004-2009 Getting the diploma of Engineering in Electronics and Telecommunications (degree
Excellent) – Faculty of Engineering, University Aïn Chams, Cairo.
1991-2004 Primary and Secondary at « collège Saint Jean Baptiste de La Salle », Cairo. Egyptian
Bachelor – Series S (degree Excellent).
Languages:
English fluent, TOEFL 84/120.
French fluent.
Personnel:
Sport Tennis and Football
Others Reading in the history of Science, Classic music.