The document explains the interrupt structure of Intel microprocessors, detailing both hardware and software interrupt types and their operations. Key aspects include how interrupts temporarily halt program execution, the significance of flags such as the interrupt enable flag and trap flag, and the function of interrupt vectors and tables. It also discusses various types of interrupts and dedicated interrupt types specific to Intel processors, including error handling and external hardware interactions.

1. Interrupts
1
April,2023
By
GetnetT(MSc).

2.  To explain the interrupt structure of the Intel Microprocessor family
 To explain the operation of software interrupt instructions INT, INTO,
INT3, and BOUND
 To explain how the interrupt enable flag bit (IF) modifies the interrupt
structure
 To describe the function of the trap interrupt flag bit (TF)
 To describe source of interrupts (types of interrupts)
2
Objectives
Interrupts

3.  An interrupt is either a hardware generated call (externally derived
from hardware signal ) or a software generated call (internally derived
from the execution of an instruction or by some other internal event)
 An interrupt is used to cause a temporary halt in the execution of the
program
 The meaning of the interrupt is to break the sequence of the operation
3
Introduction
Interrupts
 While the microprocessor is executing a program,
an interrupt breaks the normal sequence of
execution of instructions, diverts its execution to
some other program called Interrupt Service
Soutine (ISR).
 After executing ISR, IRET returns the control
back a gain to the main program.
 Interrupt processing is an alternative to polling

4.  Interrupts are useful when interfacing I/O devices at relatively
low data transfer rates, such as keyboard inputs.
 Interrupt processing allows the processor to execute other
software while the keyboard operator is thinking about what to
type next.
 When a key is pressed, the keyboard encoder debounces the
switch and puts out one pulse that interrupts the microprocessor
4
The Purpose of Interrupts
Interrupts

5.  a time line shows typing on a keyboard, a printer removing data
from memory, and a program executing
 the keyboard interrupt service procedure, called by the
keyboard interrupt, and the printer interrupt service procedure
each take little time to execute
5
The Purpose of Interrupts … cont’d
Interrupts
Fig. A time line that indicates interrupt usage in a typical system

6. Intel processors include two hardware pins (INTR and
NMI) that request interrupts and one hardware pin
(INTA) to acknowledge the interrupt requested through
INTR.
The processor also has software interrupts INT, INTO,
INT 3, and BOUND.
 Flag bits IF (interrupt flag) andTF (trap flag), are also used with
the interrupt structure and special return instruction IRET (or
IRETD in the 80386, 80486, or Pentium)
6
Interrupts

7. Interrupt vectors and the vector table are crucial to an
understanding of hardware and software interrupts.
The interrupt vector table is located in the first
1024 bytes of memory at addresses 000000H -
0003FFH.
o contains 256 different four-byte interrupt vectors
An interrupt vector contains the address (segment and
offset) of the interrupt service procedure
7
Interrupt Vector
Interrupts

8. 8
Interrupt Vector Cont’d
Interrupts

9. The first five interrupt vectors are identical in all Intel
processors (from 8086 to Pentium)
Intel reserves the first 32 interrupt vectors
The last 224 vectors are user-available
Each is four bytes long in real mode and contains the
starting address of the interrupt service procedure.
The first two bytes contain the offset address
The last two contain the segment address
9
Interrupt Vectors
interrupts Cont’d

10.  Type 0: The divide error whenever the result from a division overflows or an
attempt is made to divide by zero.
 Type 1: Single-step or trap occurs after execution of each instruction if the trap
(TF) flag bit is set.
o upon accepting this interrupt,TF bit is cleared
so the interrupt service procedure executes at
full speed
 Type 2:The non-maskable interrupt occurs when a logic 1 is placed on the
NMI input pin to the microprocessor.
o non-maskable: it cannot be disabled
 Type 3: A special one-byte instruction (INT 3) that uses this vector to access its
interrupt-service procedure.
o often used to store a breakpoint in a program
for debugging
10
Intel Dedicated Interrupts
interrupts

11.  Type 4: Overflow is a special vector used with the INTO instruction.The
INTO instruction interrupts the program if an overflow
condition exists.
o as reflected by the overflow flag (OF)
 Type 5:The BOUND instruction compares a register with boundaries
stored in the memory.
If the contents of the register are greater than or equal to the first word in
memory and less than or equal to the second word, no interrupt occurs
because the contents of the register are within bounds.
o if the contents of the register are out of bounds, a type 5 interrupt ensues
 Type 6: an invalid opcode interrupt occurs when an undefined opcode is
encountered in a program.
11
Intel Dedicated Interrupts Cont’d
interrupts

12.  Type 7:The coprocessor not available interrupt occurs when a coprocessor
is not found, as dictated by the machine status word (MSW or CR0) coprocessor
control bits.
o if an ESC orWAIT instruction executes and no coprocessor is found, a type 7
exception or interrupt occurs
 Type 8:A double fault interrupt is activated when two separate interrupts
occur during the same instruction.
 Type 9:The coprocessor segment overrun occurs
if the ESC instruction (coprocessor opcode) memory operand extends beyond offset
address FFFFH in real mode.
 Type 10: An invalid task state segment interrupt occurs in the protected
mode if theTSS is invalid because the segment limit field is not 002BH or higher.
o usually because theTSS is not initialized
o When invalid segment sector is referenced
12
Intel Dedicated Interrupts Cont’d
interrupts

13.  Type 11:The segment not present interrupt occurs when the protected mode P
bit (P = 0) in a descriptor indicates that the segment is not present or not valid.
 Type 12:A stack segment overrun occurs if the stack segment is not present
(P = 0) in the protected mode or if the limit of the stack segment is exceeded.
 Type 13:The general protection fault occurs for most protection
violations in 80286–Core2 in protected mode system.
These errors occur inWindows as general protection faults.
A list of these protection violations follows.
(a) Descriptor table limit exceeded
(b) Privilege rules violated
(c) Invalid descriptor segment type loaded
(d)Write to code segment that is protected
(e) Read from execute-only code segment
(f)Write to read-only data segment
(g) Segment limit exceeded
13
Intel Dedicated Interrupts Cont’d
interrupts

14.  Type 14: Page fault interrupts occur for any page
 When attempts to access a memory block not currently stored in the system's
RAM
 fault memory or code access in 80386, 80486, and Pentium–Core2 processors.
 Type 16: Coprocessor error takes effect when a coprocessor error (ERROR
= 0) occurs for ESC orWAIT instructions for 80386, 80486, and Pentium–
Core2 only.
 Type 17:Alignment checks indicate word and double word data are addressed
at an odd memory location (or incorrect location, in the case of a double word).
o interrupt is active in 80486 and Pentium–Core2
 Type 18: A machine check activates a system memory management mode
interrupt in Pentium–Core2.
14
Intel Dedicated Interrupts Cont’d
interrupts

15. 15
Interrupt Instructions: BOUND, INTO, INT,
INT 3, and IRET
interrupts

16. 16
Interrupt Instructions: BOUND, INTO, INT,
INT 3, and IRET Cont’d
interrupts

17. 17
Interrupt flag bits
interrupts

18. 18
8086 interrupt can come from 3 sources
interrupts
8086 interrupt can come from 3 sources:
1. Hardware interrupt: An external signal – applied
 To the non-maskable interrupt (NMI) input pin, or
 To the interrupt (INTR) input pin
2. Software interrupt: Execution of the Interrupt instruction, INT
3. Error condition: If some error condition occur by the execution
of an instruction.
e.g. Divide-by-zero interrupt: If we attempt to divide an operand by zero,
the 8086 will automatically interrupt the currently executing program

19. 19
Types of interrupts
interrupts

20. 20
Hardware Interrupts
interrupts
 The interrupts initiated by external hardware by
sending an appropriate signal to the interrupt pin
of the processor is called hardware interrupt.
 The 8086 microprocessor has two interrupt pins
INTR and NMI.
 The interrupt initiated by applying appropriate
signal to these pins are called hardware interrupts
of 8086

21. 21
Hardware Interrupts Cont’d
interrupts

22. 22
Hardware Interrupts Cont’d
interrupts

23.  The processor has the facility for accepting or rejecting hardware
interrupts.
 Programming the processor to reject an interrupt is referred to as masking
or disabling and programming the processor to accept an interrupt is
referred to as unmasking or enabling.
 In 8086 the interrupt flag (IF) can be set to 1 to unmask or enable all
hardware interrupts except NMI.
 The interrupt whose request can be either accepted or rejected by the
processor are called maskable interrupts
23
Maskable and Non-Maskable Interrupts
interrupts

24. 24
Maskable and Non-Maskable Interrupts
interrupts

25. 25
Maskable and Non-Maskable Interrupts
interrupts

26. 26
Maskable and Non-Maskable Interrupts
interrupts

27. The software interrupts are program instructions. These
instructions are inserted at desired locations in a
program.
While running a program, if software interrupt
instruction is encountered then the processor initiates
an interrupt.
The 8086 processor has 256 types of software
interrupts. The software interrupt instruction is INT n,
where n is the type number in the range 0 to 255.
27
Software Interrupts
interrupts

28. 28
Software Interrupts
interrupts

29. 29
The End!