The document discusses bipolar junction transistors and junction field effect transistors. It describes: 1) The construction and working of NPN and PNP bipolar junction transistors, including the roles of the emitter, base, and collector. Current flows from the emitter to the collector when the base is forward biased. 2) The common base, common collector, and common emitter configurations of transistors and their input, output, and current transfer characteristics. 3) Transistor DC load line analysis which determines the operating point where variations in collector current and voltage occur when a signal is applied.

1. E1 CBCS UNIT-3
BIPOLAR JUNCTION AND JUNCTION FIELD EFFECT TRANSISTORS

2. BIPOLAR JUNCTION TRANSISTOR: It is a three terminal , two
Junctions semiconductor swithing device. It transfers signal
from low resistance input to high resistance output achieves
amplification. Electrical symbols:

3. Construction: For a p or n - type semiconductor layer , an
opposite layer is doped at the Centre. The resulting two
junctions, three layers ,three terminals device is a transistor.
In former case it is PNP and in later case it is NPN.
Emitter: It supplies charge carriers to the junction. Emitter
Junction is always forward bias. It is heavily doped and wide.

4. Base: The middle layer between two pn jns JE and JC. Emitter
Jn JE is FB and Collector Jn JC RB. It is very thin and lightly
doped.
Collector: It is always RB Its function is to remove charge
Carriers from the jn with the base. It is wider than base and
Emitter. It is moderately doped.
Working of NPN Transistor: The circuit diagram of the NPN
transistor is shown in the figure below. The forward biased is
applied across the emitter-base junction, and the reversed
biased is applied across the collector-base junction. The
forward biased voltage VEB is small as compared to the
reverse bias voltage VCB.

5. The emitter of the NPN transistor is heavily doped. When the
forward bias is applied across the emitter, the majority
charge carriers move towards the base. This causes the
emitter current IE. The electrons enter into the P-type
material and combine with the holes.

6. The base of the NPN transistor is lightly doped. Due to which
only a few electrons are combined and remaining constitutes
the base current IB. This base current enters into the collector
region. The reversed bias potential of the collector region
applies the high attractive force on the electrons reaching
collector junction. Thus attract or collect the electrons at the
collector.
The whole of the emitter current is entered into the base.
Thus, we can say that the emitter current is the sum of the
collector or the base current.
There fore Ie=Ib + Ic but Ib is small negligible
Ie =Ic

7. Working of PNP Transistor:
The positive terminal of a voltage source (VEB) is connected
with Emitter (P-type) and the negative terminal is connected
with the Base terminal (N-type). Therefore, the Emitter-Base
junction is connected in forward bias.
And the positive terminal of a voltage source (VCB) is
connected with the Base terminal (N-type) and the negative
terminal is connected with the Collector terminal (P-type).
Hence, the Collector-Base junction is connected in reverse
bias.

8. There fore Ie=Ib + Ic but Ib is small negligible
Ie =Ic

9. Due to this type of bias, the depletion region at Emitter-Base
junction is narrow, because it is connected in forward bias.
While the Collector-Base junction is in reverse bias and hence
the depletion region at Collector-Base junction is wide.
The Emitter-base junction is in forward bias. Therefore, a very
large number of holes from emitter cross the depletion region
and enter the Base. Simultaneously, very few electrons enter
in Emitter from the base and recombine with the holes.
The loss of holes in the emitter is equal to the number of
electrons present in the Base layer. But The number of
electrons in the Base is very small because it is a very lightly
doped and thin region. Therefore, almost all holes of Emitter

10. will cross the depletion region and enter into the Base layer.
Because of the movement of holes, the current will flow
through the Emitter-Base junction. This current is known as
Emitter current (IE). The holes are majority charge carriers to
flow the Emitter current.
The remaining holes which do not recombine with electrons in
Base, that holes will further travel to the Collector. The
Collector current (IC) flows through the Collector-Base region
due to holes.

11. Transistor Characteristics:
Common Base (CB) Configuration of Transistor
In CB Configuration, the base terminal of the transistor will be common between
the input and the output terminals as shown by Figure 1. This configuration
offers low input impedance, high output impedance, high resistance gain and
high voltage gain.

12. Input Characteristics for CB Configuration of Transistor :
Figure 2 below shows the input characteristics of a CB
configuration circuit which describes the variation of emitter
current, IE with Base-Emitter voltage, VBE keeping Collector-
Base voltage, VCB constant.

13. This leads to the expression for the input resistance as
Output Characteristics for CB Configuration of Transistor
The output characteristics of CB configuration (Figure 3) show
the variation of collector current, IC with VCB when the
emitter current, IE is held constant. From the graph shown,
the output resistance can be obtained as:

14. Current Transfer Characteristics for CB Configuration of Transistor
Figure 4 below shows the current transfer characteristics for CB configuration
which illustrates the variation of IC with the IE keeping VCB as a constant. The
resulting current gain has a value less than 1 and can be mathematically
expressed as:

16. Common Collector (CC) Configuration of Transistor:
This transistor configuration has the collector terminal of the transistor common
between the input and the output terminals (Figure 5) and is also referred to as
emitter follower configuration. This offers high input impedance, low output
impedance, voltage gain less than one and a large current gain.

17. Input Characteristics for CC Configuration of Transistor
Figure 6 shows the input characteristics for CC configuration which describes the
variation in IB in accordance with VCB, for a constant value of Collector-Emitter
voltage, VCE.
Output Characteristics for CC Configuration of Transistor
Figure 7 below shows the output characteristics for the CC configuration which
exhibit the variations in IE against the changes in VCE for constant values of IB.

18. Current Transfer Characteristics for CC Configuration of Transistor
This characteristic of CC configuration (Figure 8) shows the variation of IE with
IB keeping VCE as a constant.

19. Common Emitter (CE) Configuration of Transistor
In this configuration, the emitter terminal is common between the
input and the output terminals as shown by Figure 9. This
configuration offers medium input impedance, medium output
impedance, medium current gain and voltage gain.

20. Figure 10 shows the input characteristics for the CE
configuration of transistor which illustrates the variation in IB
in accordance with VBE when VCE is kept constant.

21. From the graph shown in Figure 10 above, the input resistance
of the transistor can be obtained as

22. Output Characteristics for CE Configuration of Transistor
The output characteristics of CE configuration (Figure
11) are also referred to as collector characteristics. This
plot shows the variation in IC with the changes in VCE
when IB is held constant. From the graph shown, the
output resistance can be obtained as:

24. The out put characteristics of transistor in CE mode is divided in to three
regions
cut-off, saturation and active regions.
Cut-off region: It is the region between IB=0 and VCE(sat)=Vknee.In this region
Collector current is IC=ICEO=Io. Both Jns are RB and no collector current.
Saturation region: It is the region between VCE(sat) and IC (sat) in which both
Jns are FB called ohmic region obeys ohms law. IC is exponential with VCE.
Active region: It is the region between IC=IC(sat) and IB=0 in which Jn JE
sufficiently FB and JC sufficiently RB.The IC is constant with VCE.In this region
transistor works as an Amplifier.
Current gain (α): It is the ratio of change in collector current dIC to change in
emitter current dIE. α= dIC / dIE
Current gain (β): It is the ratio of change in collector current dIC to change in
base Current dIB. β = dIC/dIB

25. Current Transfer Characteristics for CE Configuration of Transistor.This
characteristic of CE configuration shows the variation of IC with IB
keeping VCE as a constant. This can be mathematically given by

26. This ratio is referred to as common-emitter current gain and is
always greater than 1.

27. Transistor DC Load Line Analysis: It is a straight line on out
put charecteristics of transistor and determines the locus of
VCE verses IC graph points for any given value of collector
Load resistance Rc .
Construction of DC load line:
Consider a CE NPN transistor circuit shown in the figure below
where no signal is applied to the input side. For this circuit,
DC condition will obtain, and the output characteristic of such
a circuit is shown in the figure below.

28. The DC load line curve of the above circuit is shown in the
figure below.

29. By applying Kirchhoff’s voltage law to the collector circuit, we
get,

30. The above equation shows that the VCC and RC are the constant
value, and it is the first-degree equation which is represented by the
straight line on the output characteristic. This load line is known as a
DC load line. The input characteristic is used to determine the locus
of VCE and IC point for the given value of RC. The end point of the line
are located as
1. The collector-emitter voltage VCE is maximum when the collector
current IC = 0 then from the equation (1) we get,
The first point A (OA = VCC) on the collector-emitter voltage axis
shown in the figure above.

31. 2. The collector current IC becomes maximum when the collector-
emitter voltage VCE = 0 then from the equation (1) we get.
This gives the second point on the collector current axis as shown in
the figure above.
By adding the points A and B, the DC load line is drawn. With the
help of load line, any value of collector current can be determined.

32. Operating Point in Transistor : It is a point on the DC-load line,
On out put charecteristics of transistor, which gives zero signal
values of IC and VCE graph. It is called as op-point ,since the
Variations of IC and VCE takes place about this point when
Signal is applied. It is also called as Q-point or Silent point.

33. According to the load line condition, the OA = VCE = VCC and OB = IC
= VCC/RC
The point Q is the operating point where the DC load line intersects
the base current IB at the output characteristic curves in the absence
of input signal.
Where IC= OD mA
VCE = OC volts.
The position of the Q-point depends on the applications of the
transistor. If the transistor is used as a switch then for open switch
the Q-point is in the cutoff region, and for the close switch, the Q-
point is in the saturation region. The Q-point lies in the middle of the
line for the transistor which operates as an amplifier.

34. Transistor Biasing
The proper flow of zero signal collector current and the maintenance
of proper collector emitter voltage during the passage of signal is
known as Transistor Biasing. The circuit which provides transistor
biasing is called as Biasing Circuit.
Need for DC biasing
If a signal of very small voltage is given to the input of BJT, it cannot be
amplified. Because, for a BJT, to amplify a signal, two conditions have
to be met.
The input voltage should exceed cut-in voltage for the transistor to be
ON.
The BJT should be in the active region, to be operated as an amplifier.

35. Factors affecting the operating point:
The main factor that affect the operating point is the temperature. The
operating point shifts due to change in temperature.
As temperature increases, the values of ICE, β, VBE gets affected.
ICBO gets doubled (for every 10o rise)
VBE decreases by 2.5mv (for every 1o rise)
So the main problem which affects the operating point is temperature. Hence
operating point should be made independent of the temperature so as to
achieve stability. To achieve this, biasing circuits are introduced.
Stabilization:
The process of making the operating point independent of temperature
changes or variations in transistor parameters is known as Stabilization.
Once the stabilization is achieved, the values of IC and VCE become
independent of temperature variations or replacement of transistor. A good
biasing circuit helps in the stabilization of operating point.

36. Need for Stabilization
Stabilization of the operating point has to be achieved due to the
following reasons.
Temperature dependence of IC
Individual variations
Thermal runaway
Temperature Dependence of IC
As the expression for collector current IC is
IC=βIB+ICEO
=βIB+(β+1)ICBO
The collector leakage current ICBO is greatly influenced by temperature
variations. To come out of this, the biasing conditions are set so that zero signal
collector current IC = 1 mA. Therefore, the operating point needs to be
stabilized i.e. it is necessary to keep IC constant.

37. Individual Variations
As the value of β and the value of VBE are not same for every transistor,
whenever a transistor is replaced, the operating point tends to change. Hence it
is necessary to stabilize the operating point.
Thermal Runaway
As the expression for collector current IC is
IC=βIB+ICEO
=βIB+(β+1)ICBO
The flow of collector current and also the collector leakage current causes heat
dissipation. If the operating point is not stabilized, there occurs a cumulative
effect which increases this heat dissipation.
The self-destruction of such an un stabilized transistor is known as Thermal run
away.
In order to avoid thermal runaway and the destruction of transistor, it is
necessary to stabilize the operating point, i.e., to keep IC constant.

38. Stability Factor
It is understood that IC should be kept constant in spite of variations of ICBO or
ICO. The extent to which a biasing circuit is successful in maintaining this is
measured by Stability factor. It denoted by S.
By definition, the rate of change of collector current IC with respect to the
collector leakage current ICO at constant β and IB is called Stability factor.
S=dIC/dICO at constant IB and β
Hence we can understand that any change in collector leakage current changes
the collector current to a great extent. The stability factor should be as low as
possible so that the collector current doesn’t get affected. S=1 is the ideal
value. The general expression of stability factor for a CE configuration can be
obtained as under. IC=βIB+(β+1)ICO
Differentiating above expression with respect to IC, we get
1=βdIB/dIC+(β+1)dICO/dIC Or 1=βdIB/dIC+(β+1)/S Since dICO/dIC=1/S
Or S=β+1/1−β(dIB/dIC) Hence the stability factor S depends on β, IB and IC.

39. Transistor Biasing Circuits:
•Fixed Bias or Base Resistor method
•Voltage-divider bias
•Fixed Bias or Base Resistor method :
In this method, a resistor RB of high resistance is connected in base, as
the name implies. The required zero signal base current is provided by
VCC which flows through RB. The base emitter junction is forward
biased, as base is positive with respect to emitter.
The required value of zero signal base current and hence the collector
current (as IC = βIB) can be made to flow by selecting the proper value
of base resistor RB. Hence the value of RB is to be known. The figure
below shows how a base resistor method of biasing circuit looks like.

40. Let IC be the required zero signal collector current. Therefore, IB=IC/β
Considering the closed circuit from VCC, base, emitter and ground, while
applying the Kirchhoff’s voltage law, we get,
VCC=IBRB+VBE Or IBRB=VCC−VBE Therefore RB=(VCC−VBE)/IB
Since VBE is generally quite small as compared to VCC, the former
can be neglected with little error. Then, RB=VCC/IB
Since VCC is fixed known quantity, called fixed bias circuit.

41. Stability factor: S=β+1/1−β(dIB/dIC)
In fixed-bias method of biasing, IB is independent of IC so that, dIB/dIC=0
Substituting the above value in the previous equation, Stability factor, S=β+1
Thus the stability factor in a fixed bias is (β+1) which means that IC changes
(β+1) times as much as any change in ICO.
Advantages:
The circuit is simple.
Only one resistor RE is required.
Biasing conditions are set easily.
No loading effect as no resistor is present at base-emitter junction.
Disadvantages:
The stabilization is poor as heat development can’t be stopped.
The stability factor is very high. So, there are strong chances of thermal run
away.
Hence, this method is rarely employed.

42. Voltage Divider Bias Method
Among all the methods of providing biasing and stabilization,
the voltage divider bias method is the most prominent one.
Here, two resistors R1 and R2 are employed, which are
connected to VCC and provide biasing. The resistor RE
employed in the emitter provides stabilization.
The name voltage divider comes from the voltage divider
formed by R1 and R2. The voltage drop across R2 forward
biases the base-emitter junction. This causes the base current
and hence collector current flow in the zero signal conditions.
The figure below shows the circuit of voltage divider bias
method.

43. Suppose that the current flowing through resistance R1 is I1. As base current IB
is very small, therefore, it can be assumed with reasonable accuracy that
current flowing through R2 is also I1.
Now try to derive the expressions for collector current and collector voltage.

44. Collector Current, IC
From the circuit, it is evident that,
I1=VCC/(R1+R2)
Therefore, the voltage across resistance R2 is
V2=[VCC/(R1+R2)]R2
Applying Kirchhoff’s voltage law to the base circuit,
V2=VBE+VE
V2=VBE+IERE
IE=(V2−VBE)/RE
Since IE ≈ IC,
IC=(V2−VBE)/RE
From the above expression, it is evident that IC doesn’t depend upon β. VBE is
very small that IC doesn’t get affected by VBE at all. Thus IC in this circuit is
almost independent of transistor parameters and hence good stabilization is
achieved.

45. Collector-Emitter Voltage, VCE:
Applying Kirchhoff’s voltage law to the collector side,
VCC=ICRC+VCE+IERE
Since IE ≅ IC
=ICRC+VCE+ICRE
=IC(RC+RE)+VCE
Therefore,
VCE=VCC−IC(RC+RE)
RE provides excellent stabilization in this circuit.
V2=VBE+ICRE
Suppose there is a rise in temperature, then the collector current IC decreases,
which causes the voltage drop across RE to increase. As the voltage drop across
R2 is V2, which is independent of IC, the value of VBE decreases. The reduced
value of IB tends to restore IC to the original value.

46. Stability Factor
The equation for Stability factor of this circuit is obtained as
Stability Factor = S={(β+1)(R0+R3)}/(R0+RE+βRE)
=(β+1)×(1+R0/RE)/(β+1+R0/RE)
Where
R0=R1R2/(R1+R2)
If the ratio R0/RE is very small, then R0/RE can be neglected
as compared to 1 and the stability factor becomes
Stability Factor = S=(β+1)×1/(β+1)=1
This is the smallest possible value of S and leads to the
maximum possible thermal stability.

47. The hybrid model has four h-parameters. The "h" stands for
hybrid because the parameters are a mix of impedance, admittance
and dimensionless units. In common emitter the parameters are:
hie input impedance (Ω)
hre reverse voltage ratio (dimensionless)
hfe forward current transfer ratio (dimensionless)
hoe output admittance (Siemen)
Note that lower case suffixes indicate small signal values and the last
suffix indicates the mode so hie is input impedance in common
emitter, hfb would be forward current transfer ration in common
base mode, etc.
The hybrid model: for the BJT in common emitter mode is shown
below:

49. The hybrid model is suitable for small signals at mid band and
describes the action of the transistor. Two equations can be derived
from the diagram, one for input voltage vbe and one for the output ic:
vbe = hie ib + hre vce , ic = hfe ib + hoe vce
If ib is held constant (ib=0) then hre and hoe can be solved:
hre = vbe / vce | ib = 0 , hoe = ic / vce | ib = 0
Also if vce is held constant (vce=0) then hie and hfe can be solved:
hie = vbe / ib | vce = 0 , hfe = ic / ib | vce = 0
These are the four basic parameters for a BJT in common emitter.
Typical values are hre = 1 x10-4, hoe typical value 20uS, hie typically
1k to 20k and hfe can be 50 - 750. The H-parameters can often be
found on the transistor datasheets. The table below lists the four h-
parameters for the BJT in common base and common collector mode.

50. Field Effect Transistor: FET is a three terminal, three layer,
two Junctions, unipolar, semiconductor switching device in
which the current conduction is through the channel rather
than junctions.
Types: •Junction field effect transistor(JFET)•Metal oxide
semiconductor field effect transistor(MOSFET)
JFET : Junction field effect transistor:
The Junction Field Effect Transistor, or JFET, is a voltage
controlled three terminal unipolar semiconductor device
available in N-channel and P-channel configurations

51. JFET Construction:

52. JFET Electrical symbol:

53. Construction Details: A JFET consists of a p-type or n-type
silicon bar containing two pn junctions at the sides as shown
in fig.1.
The bar forms the conducting channel for the charge carriers.
If the bar is of p-type, it is called p-channel JFET as shown in
fig.1(i) and if the bar is of n-type, it is called n-channel JFET as
shown in fig.1(ii).The two pn junctions forming diodes are
connected internally and a common terminal called gate is
taken out.Other terminals are source and drain taken out
from the bar as shown in fig.1.Thus a JFET has three terminals
such as , gate (G), source (S) and drain (D).

54. JFET Polarities: Fig.2 (i) shows the n-channel JFET polarities
and fig.2 (ii) shows the p-channel JFET polarities.
In each case, the voltage between the gate and source is such that the gate is
reverse biased. The source and the drain terminals are interchangeable.

55. The following points may be noted: The input circuit ( i.e. gate to
source) of a JFET is reverse biased. This means that the device has
high input impedance.The drain is so biased w.r.t. source that drain
current ID flows from the source to drain. In all JFETs, source current
IS is equal to the drain current i.e IS = ID.
Principle and Working of JFET Fig.3 shows the circuit of n-channel
JFET with normal polarities. The two pn junctions at the sides form
two depletion layers. The current conduction by charge carriers (i.e.
electrons) is through the channel between the two depletion layers
and out of the drain. The width and hence resistance of this channel
can be controlled by changing the input voltage VGS. The greater the
reverse voltage VGS, the wider will be the depletion layer and
narrower will be the conducting channel.

56. The narrower channel means greater resistance and hence
source to drain current decreases. Reverse will happen when
VGS decreases. Thus JFET operates on the principle that width
and hence resistance of the conducting channel can be varied
by changing the reverse voltage VGS. In other word, the
magnitude of drain current ID can be changed by altering VGS.
The working of JFET can be explained as follows:
Case-i: When a voltage VDS is applied between drain and
source terminals and voltage on the gate is zero as shown in
fig.3(i), the two pn junctions at the sides of the bar establish
depletion layers.

58. The electrons will flow from source to drain through a channel
between the depletion layers.The size of the depletion layers
determines the width of the channel and hence current
conduction through the bar.
Case-ii: When a reverse voltage VGS is applied between gate
and source terminals, as shown in fig.3(ii), the width of
depletion layer is increased.
This reduces the width of conducting channel, thereby
increasing the resistance of n-type bar.
Consequently, the current from source to drain is decreased.
On the other hand, when the reverse bias on the gate is
decreased, the width of the depletion layer also decreases.

60. This increases the width of the conducting channel and hence
source to drain current. A p-channel JFET operates in the same
manner as an n-channel JFET except that channel current
carriers will be the holes instead of electrons and polarities of
VGS and VDS are reversed.
JFET Characteristics:The JFET characteristics of can be studied
for both N-channel and P-channel as discussed below:
N-Channel JFET Characteristics. The N-channel JFET
characteristics or trans conductance curve is shown in the
figure below which is graphed between drain current and
gate-source voltage. There are multiple regions in the curve,
they are ohmic, saturation, cutoff, and breakdown regions.

62. N-Channel JFET Characteristics:
Ohmic Region
The only region in which trans conductance curve shows linear response and
drain current is opposed by the JFET transistor resistance is termed as Ohmic
region.
Saturation Region: In the saturation region, the N-channel junction field effect
transistor is in ON condition and active, as maximum current flows because of
the gate-source voltage applied.
Cutoff Region: In this cutoff region, there will be no drain current flowing and
thus, the N-channel JFET is in OFF condition.
Breakdown Region: If the VDD voltage applied to the drain terminal exceeds
the maximum necessary voltage, then the transistor fails to resist the current
and thus, the current flows from drain terminal to source terminal. Hence, the
transistor enters into the breakdown region.

63. Drain current in the active region: Where ID=Drain current,IDSS=
Shorted gate drain current,VGS=Gate source Voltage,VP=VGSoff
Transconductance is the ratio of change in drain current (δID) to change
in the gate to source voltage (δVGS) at a constant drain to source voltage (VDS
= Constant).

64. Transfer Characteristic of JFET:The transfer characteristic for
a JFET can be determined experimentally, keeping drain-
source voltage, VDS constant and determining drain current,
ID for various values of gate-source voltage, VGS.

65. Dynamic Output Resistance This is the ratio of change of drain to
source voltage (δVDS) to the change of drain current (δID) at a
constant gate to source voltage (VGS = Constant). The ratio is denoted
as rd.

66. Amplification Factor
The amplification factor is defined as the ratio of change of drain
voltage (δVDS) to change of gate voltage (δVGS) at a constant drain
current (ID = Constant).
RELATION BETWEEN rd ,gm and µ :There is a relation between
transconductance (gm) and dynamic output resistance (rd) and that
can be established in the following way.

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