A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for ultra-wide-band (UWB) applications using standard UMC 0.18 µm CMOS technology is reported. Designing of RF circuit components is a challenging job, since even after performing lengthy calculations and finding parameter values it is less guarantee that the design performs as expected. In view of this the optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get the optimized starting values of components in the proposed LNA design. The obtained NSGA-II parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of power out of 1.8 V supply
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
A Novel Architecture for Different DSP Applications Using Field Programmable ...journal ijme
This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.
Negative image amplifier technique for performance enhancement of ultra wideb...IJECEIAES
The paper aims at designing of two stage cascaded ultra-wideband (UWB) low noise amplifier (LNA) by using negative image amplifier technique. The objective of this article is to show the performance improvement using negative image amplifier technique and realization of negative valued lumped elements into microstrip line geometry. The innovative technique to realize the negative lumped elements are carried out by using Richard’s Transformation and transmission line calculation. The AWR microwave office tool is used to obtain characteristics of UWB LNA design with hybrid microwave integrated circuit (HMIC) technology. The 2-stage cascaded LNA design using negative image amplifier technique achieves average gain of 23dB gain and low noise figure of less than 2dB with return loss less than -8dB for UWB 3-10GHz. The Proper bias circuit is extracted using DC characteristics of transistor at biasing point 2V, 20mA and discussed in detail with LNA layout. The negative image matching technique is applied for both input and output matching network. This work will be useful for all low power UWB wireless receiver applications.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
A Novel Architecture for Different DSP Applications Using Field Programmable ...journal ijme
This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.
Negative image amplifier technique for performance enhancement of ultra wideb...IJECEIAES
The paper aims at designing of two stage cascaded ultra-wideband (UWB) low noise amplifier (LNA) by using negative image amplifier technique. The objective of this article is to show the performance improvement using negative image amplifier technique and realization of negative valued lumped elements into microstrip line geometry. The innovative technique to realize the negative lumped elements are carried out by using Richard’s Transformation and transmission line calculation. The AWR microwave office tool is used to obtain characteristics of UWB LNA design with hybrid microwave integrated circuit (HMIC) technology. The 2-stage cascaded LNA design using negative image amplifier technique achieves average gain of 23dB gain and low noise figure of less than 2dB with return loss less than -8dB for UWB 3-10GHz. The Proper bias circuit is extracted using DC characteristics of transistor at biasing point 2V, 20mA and discussed in detail with LNA layout. The negative image matching technique is applied for both input and output matching network. This work will be useful for all low power UWB wireless receiver applications.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Optimization for Minimum Noise Figure of RF Low Noise Amplifier in 0.18µm Tec...IJEEE
Using a modified Cascode topology a 2GHz Low Noise Amplifier (LNA) has been implemented in Cadence Spectre RF tool on UMC 0.18µm technology to work under reduced power supply. After simulation it is found that at resonance frequency of 2GHz, the minimum noise figure is 2.5 dB and noise figure is 3 dB for a voltage gain of 17 dB.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Sigma-Delta Analog to Digital ConvertersSatish Patil
In recent years Sigma-Delta ADCs became one of the most popular types of Analog-to-Digital converters. The key features of these are high-speed, high resolution and low operating voltages. These are commonly used in variety of applications like digital audio CDs, CODEC, biomedical sensor applications and wireless transmitters/receivers. The basic principles involved in this technique are oversampling and noise shaping. This report reviews different techniques proposed for high resolution, low power Sigma-Delta ADC. Conventional design of SDM was dominated by discrete time architecture but in modern designs continuous types are also becoming famous because of their low power attributes. Continuous efforts have been taken to reduce the supply voltages of SDM and recently, lowest reported is 250mv.
A charge recycling three phase dual rail pre charge logic based flip-flopVLSICS Design
Providing resistance against side channel attacks especially differential power analysis (DPA) attacks,
which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges of
designers of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phase
dual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. The new flip-flop uses
inverters that uses the charge recycling technique where charge stored on high output node during
evaluation phase is used to partially charge the low output node in subsequent pre-charge phases. As a
result less charge comes from the power supply thus lowering the power consumption. Simulation results in
Cadence Virtuoso 45 nm CMOS process show improvement in power consumption in inverter up to 60%
while CRTDPL flip-flop consumes around 50% less power compared to TDPL flip-flop.
A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a
total power 1.96mW.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
Optimization for Minimum Noise Figure of RF Low Noise Amplifier in 0.18µm Tec...IJEEE
Using a modified Cascode topology a 2GHz Low Noise Amplifier (LNA) has been implemented in Cadence Spectre RF tool on UMC 0.18µm technology to work under reduced power supply. After simulation it is found that at resonance frequency of 2GHz, the minimum noise figure is 2.5 dB and noise figure is 3 dB for a voltage gain of 17 dB.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Sigma-Delta Analog to Digital ConvertersSatish Patil
In recent years Sigma-Delta ADCs became one of the most popular types of Analog-to-Digital converters. The key features of these are high-speed, high resolution and low operating voltages. These are commonly used in variety of applications like digital audio CDs, CODEC, biomedical sensor applications and wireless transmitters/receivers. The basic principles involved in this technique are oversampling and noise shaping. This report reviews different techniques proposed for high resolution, low power Sigma-Delta ADC. Conventional design of SDM was dominated by discrete time architecture but in modern designs continuous types are also becoming famous because of their low power attributes. Continuous efforts have been taken to reduce the supply voltages of SDM and recently, lowest reported is 250mv.
A charge recycling three phase dual rail pre charge logic based flip-flopVLSICS Design
Providing resistance against side channel attacks especially differential power analysis (DPA) attacks,
which aim at disclosing the secret key of cryptographic algorithm is one of the biggest challenges of
designers of cryptographic devices. In this paper design of novel data flip-flop compatible with three-phase
dual-rail logic (TDPL), called Charge recycling TDPL flip-flop is investigated. The new flip-flop uses
inverters that uses the charge recycling technique where charge stored on high output node during
evaluation phase is used to partially charge the low output node in subsequent pre-charge phases. As a
result less charge comes from the power supply thus lowering the power consumption. Simulation results in
Cadence Virtuoso 45 nm CMOS process show improvement in power consumption in inverter up to 60%
while CRTDPL flip-flop consumes around 50% less power compared to TDPL flip-flop.
A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a
total power 1.96mW.
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
This paper presents a novel approach for completely test enable feature and low-voltage delta– sigma analog-to-digital (A/D) converters for cutting edge wireless applications. Oversampling feature of ADCs and DACs is enough to meet the requirement related to in-band and adjacent channel leakage ratio (ACLR) execution of 3G/4G portable radio. The quantization noise which is not filtered in ADC is addressed. We have achieved work power-optimization and test enable feature of oversampling ADC is uses in design and simulation so that the problem of quantization error in continues time sigma delta ADC is solved. This paper suggests support to designer for selecting appropriate topologies with various channel arrangements, number of bits and oversampling issues. A test enable feature of CT A/D is presented introducing the test signal generation (TSG) and the COrdinate Rotation Digital Computer (CORDIC) for evaluating the performance of ADC. This helps in addressing the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta–sigma modulator ADC for 4G radios is studied.
First order sigma delta modulator with low-power consumption implemented in a...eSAT Journals
Abstract
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits
Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is
necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS
technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and
the power consumption was 5.5 mW under ±1.5V supply voltage .
Index terms: Analog-to-Digital conversion, Delta-Sigma modulation, CMOS technology, Transconductance operational
amplifier.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
Efficient reconfigurable architecture of baseband demodulator in sdreSAT Journals
Abstract This paper presents the simulation architecture and performance analysis with the use of ZCD technic. A Zero-Crossing based All-Digital Baseband Demodulation architecture is proposed in this work. This architecture supports demodulation of all modulation schemes including MSK, PSK, FSK, and QAM. The proposed structure is very low area, low power, and low latency and can operate in real-time. Moreover it can switch, in run-time, between multiple modulation schemes like GMSK (GSM), QPSK (CDMA), GFSK (Bluetooth), 8-PSK (EDGE), Offset-QPSK (W-CDMA), etc. In addition, the phase resolution of the demodulator is scalable with performance. In addition, bit-wise amplitude quantization based quad-decomposition approach is utilized to demodulate higher order M-ary QAM modulations such as 16-QAM & 64-QAM, which is also a highly scalable architecture. This structure of demodulator provides energy-efficient and resource-efficient implementation of various wireless standards in physical layer of SDR. Keywords — Physical layer, Mobile and Wireless Communication, Software Defined radio (SDR), Zero Cross Detection (ZCD), Modulation Schemes, Architecture, high level synthesis, FPGA.
Area Versus Speed Trade-off Analysis of a WiMAX Deinterleaver Circuit Designijsrd.com
Trade-off is one of the main design parameters in the field of electronic circuit design. Whereas smaller electronics devices which use less hardware due to techniques like hardware multiplexing or due to smaller devices created due to techniques developed by nanotechnology and MEMS, are more appealing, a trade-off between area, power and speed is inevitable. This paper analyses the trade-off in the design of Wimax deinterleaver. The main aim is to reduce the hardware utilization in a deinterleaver but speed and power consumption are important parameters which cannot be overlooked.
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wirele...IJERA Editor
This paper presents the design of CT ΣΔ modulator which can provide high DR and SNR over a 20 MHz signal bandwidth. So far all the CT SDM uses either feedback or feedforward loop filter architecture. The proposed topology is a 3rd order low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. Loop filter is designed as RC integrators due to its high linearity and easy interface. The design starts from system level using Matlab/Simulink. Then, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using Cadence Virtuoso 180 nm CMOS technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Harnessing WebAssembly for Real-time Stateless Streaming Pipelines
OPTIMIZATION OF CMOS 0.18 M LOW NOISE AMPLIFIER USING NSGA-II FOR UWB
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
DOI : 10.5121/vlsic.2014.5505 59
OPTIMIZATION OF CMOS 0.18 M LOW NOISE
AMPLIFIER USING NSGA-II FOR UWB
APPLICATIONS
V. P. Bhale* and U. D. Dalal
VLSI Design Laboratory, Department of Electronics Engineering
Sardar Vallabhbhai National Institute of Technology (SVNIT),
Surat-395 007,Gujrat, India
ABSTRACT
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 µm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
KEYWORDS
LNA, NSGA-II Algorithm, Noise Figure, Power Gain, return losses
1. INTRODUCTION
Recent years have experienced explosive growth in the Radio Frequency /microwave
semiconductor industry owing to the proliferation of a host of applications. Single-chip Bluetooth
devices are already available and similar integration is likely to be achieved in cellular telephones
and wireless networking in near future. Radio Frequency components are the basic building
blocks of transceivers operating in GHz frequency range. Designing of RF circuit component
needs lot of effort. After performing lengthy calculations and finding the parameter values it is
not guaranteed that the circuit performs as expected. In Radio Frequency Integrated Circuits
(RFIC), Low Noise Amplifiers are considered as black magic box because of their uncertain
response with higher frequencies. Due to mismatch of input impedance and output impedance
maximum power transformation is not possible. For Designing of the tank circuit, input and
output impedance circuit, we need to design a passive filter with optimized component values.
Optimization of the component value is a time consuming job. In view of this a CAD tool using
Non-Dominated Sorting Genetic Algorithm (NSGA-II) has been employed. The design goal is
formulated as an objective function. Some approximations and estimations on the design
parameters are made in order to satisfy the requirement of the genetic algorithm. Many
applications of genetic algorithm and optimization of LNA parameter by binary coded genetic
algorithm is reported in [2, 3]. In this paper the design and optimization of single ended LNA
using real coded genetic algorithm is presented. The rest of the paper is organized as: section-II
gives brief introduction of Non-Dominated Sorting Genetic Algorithm. In section-III analysis and
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
60
design problem of low noise amplifier is presented, in section-IV design objective and constrains
optimization of LNA is mentioned. In section-V simulation result and discussion is presented.
Scope and limitation of the NSGA-II has been discussed in section-VI and finally section-VII
concludes the paper.
2. ELISTIST NON-DOMINATED SORTING GENETIC ALGORITHM
(NSGA-II)
Genetic algorithms [3, 4] are search techniques used in computing to find true or approximate
solutions to search or optimization problems. It is based on the concepts of natural selection,
reproduction and mutation and has been used extensively in optimization problems. It can be
classified in two sets depending on type of coding of the members; one is binary coded and the
second is real coded [3]. In the past few years GA has undergone lots of developments developing
its features, processing time, etc., some such developments are Multi Objective Genetic
Algorithm (MOGA) [5,6], Elitist Non Dominated Sorting Genetic Algorithm [3].
3. ANALYSIS AND DESIGN OF LOW NOISE AMPLIFIER
The early part of this section is based on the literature survey and concludes with own design. As
one of the essential components, Low Noise Amplifiers (LNAs) for wireless applications have
attracted significant research interest and various approaches to the design of narrow band LNAs
(operating below 3 GHz) and wideband LNAs (operating above 3 GHz) have been proposed
previously [7-15] and as shown in Fig. 1(a-d). Distributed amplifiers [7] can provide very large
bandwidth because of their unique gain-bandwidth tradeoff. However, large power consumption
and chip area make them unsuitable for typical low –power, low cost wireless applications.
Figure 1. Various LNA Topologies (a) Distribute amplifier, (b) common gate, (c) inductive degeneration,
(d) resistive feedback
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61
Common-gate amplifiers [8, 9] exhibit excellent wide band input matching, but suffer from a
relatively large noise figure (NF). Narrow-band LNAs like an inductively degenerated common-
source amplifier can also be converted into a wideband one by adding a wideband input matching
network [10]. However, the insertion loss of the passive input matching degrades the NF rapidly
with frequency. Resistive-feedback amplifiers [11, 12-14] have very good wideband input
matching characteristics. However, low NF and low power consumption can be hardly achieved
simultaneously across a large frequency range. In [15], the noise cancellation technique is used to
relax this trade-off in resistive feedback amplifiers.
(a) (b)
Figure 2. (a) Inductive source degeneration, (b) Small signal equivalent of 2(a)
A typical LNA must fulfill several challenging requirements. The LNA must provide a good input
matching over a band more than 500 MHz. A high gain is also preferred to amplify the weak
signals at the receiver and to overcome the noise effects from the subsequent stages. In addition,
the noise figure of the LNA must be low (typically < 3 dB) since it plays a major role in defining
the receiver's sensitivity. Moreover, the LNA also has to be power efficient and physically small
to save power and reduce the cost, respectively. An inductively degenerated LNA configuration is
proposed, as shown in Figure 2 (a). Inductive degeneration improves the linearity of the amplifier.
The input impedance can be derived from the small signal analysis [16] of Figure 2 (b). By
looking into the input side of Figure 2 (b), input impedance Zin can be:
s
gs
m
gs
ggsin L
C
g
sC
RLLsZ )(
1
)( ++++=
(1)
Where Ls, Lg are the source and gate inductances, respectively; Rg is the transistor gate resistance,
Cgs is the transistor gate-to-source capacitance; gm is the transistor trans-conductance. The
inductor parasitic resistance is ignored here. Input match requires that at the resonance frequency
of the circuit, the impedance of the input stage is purely real and should be equal to 50 Ω. It
follows that:
50)( =+ s
gs
m
g L
C
g
R
(2)
Where ω0 is the resonance frequency (rad/s), and
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
62
0
1
)(
0
0 =++
gs
gs
Cj
LLj
ω
ω
(3)
The noise factor (F) is defined as [7, 8]:
20
)(1
T
sm
s
g
s
l
Rg
R
R
R
R
F
ω
ω
α
γ
+++=
(4)
)(log10 10 FNF ⋅= Where unity frequency:
gs
m
T
C
g
=ω ,
0d
m
g
g
≡α , Rs : source resistance,
Rl : series resistance of inductors, Rg : gate resistance, γ: the thermal noise coefficient, ω0 : the
resonance frequency, gm: transistor trans-conductance. For a source inductively degenerated
LNA in Fig.2, we could put a lower bound on the trans-conductance of the input transistor to
ensure that the final designed LNA can provide a reasonable gain [9]
−
==
01
2
0
10
0 1
1
CLw
Ljw
Ljw
ZGA
s
eqmV
(5)
In order to formulate a geometric programming problem, we have to do some transformation and
introduce a new variable to satisfy the requirement of geometric programming on the objective
and constraints. Inequality constraints, and the objective function must be in the form of
polynomial, equality constrains must be in the form of monomial. Here noise figure and gain are
formulated for low noise amplifier. For low noise amplifiers, Objective function of Noise Figure
can be formulated as:
( )2
min 02.050 optn GRFF −××+=
(6)
Where,
5
)1(21 2
0
min
×
−××××+
=
Wt
CW
F
γδ
mG
Rn
×
=
α
γ
γ
δ
α
×
−×
××=
5
)1( 2
0
C
CgsWGopt
The objective function of the Gain of LNA can be formulated as:
load
loadt
RW
RW
Gain
××
×
=
20 (7)
And the objective function of power consumption has been formulated as:
DCDDC VIP ×=
(8)
Where,
gthChannelLen
VWidthC
I odoxn
D
×
×××
=
2
2
µ
In above equation, second order effects on drain current have been neglected to reduce the
complexity of the program. As the schematic diagram of the LNA is depicted in Figure 3, an
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63
input impedance matching circuit is needed to match the source impedance to transistor input
impedance. Objective function for Input impedance can be formulated from following equation.
s
gs
m
gs
ggsin L
C
g
sC
RLLsZ )(
1
)( ++++=
(9)
Ls and Lg is used to tune the input impedance (Zin) to 50 Ω at 3 GHz frequencies. Cgs and Rg
Model the impedance looking into the gate of MOSFET. Here we can include pad capacitance
and bond wire inductance also [10].
4. DESIGN OBJECTIVES AND CONSTRAINT OPTIMIZATION FOR
NSGA-II
The simulations have been done for LNA with following constraints. Based on the technology
parameters following have been defined as constant:
VVddVVth
mLnH
RLRsmfFCox
8.1,47.0
,5.0,18.0)(,5.2,1)/(
,50)(,50)(,632.8)2/(
==
====Ω
=Ω=Ω=
λµγβ
µ
Design constraints for the component of circuit were taken as follows:
(1) mW µ10515 ≤≤ (2) nHLs 501.0 ≤≤
(3) nHLg 501.0 ≤≤ (4) pFC 5.01.0 ≤≤
Simulations have been done with these parameters using NSGA-II. The NSGA parameters that
were given are as follows: Mutation probability= 0.23671, Population size=100, Crossover
Probability=0.99431, Number of generations=50.
5. SIMULATION RESULTS AND DISCUSSIONS
5.1. Simulation results using NSGA-II
The above mentioned optimization technique is implemented for Low Noise Amplifier design to
optimize gain and noise figure. Direct equations have been used for gain and noise figure which
were calculated for cascode LNA with inductive source degeneration. Program structure for LNA
optimization using NSGA-II is shown in Figure 3 below. The “func-con. h” header file has been
modified and the fitness functions and constraint functions have been replaced with the equations
as discussed in section 3. Also, “LNA_equations.h” file has been added, which actually evaluates
all these equations.
Figure 3. LNA Optimization Program Structure
LNA Equations header file
NSGA-II Optimization Core
Input file
handler
Output file handler
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After NSGA-II optimizer generates output files, another program convert those into design
parameters and we can plot those values using GNUPLOT software as plotted in Figure 4(a-f).
The trans-conductance, gm, of the device is very much important to achieve good gain for LNA.
However, this gm depends on the transistor width. Also, gm/ID ratio needs to be maintained to
achieve a required LNA gain. Thus, the width of the transistor needs to be chosen to give enough
gain and minimum noise figure. From Figure 4 (a), thus, ‘W’ is chosen to be 105 µm. The
overdrive voltage is one of the important parameters for transistor operating point analysis. The
transistor should operate in the desired operating region for maximum gain. Thus, plots in Figure
4 (b) are plotted using NSGA-II to guess the initial overdrive voltage required for the transistor to
be in the desired operating region.
The optimized value of food is chosen to be 0.35 V from Figure 4 (b) since at this overdrive
voltage maximum gain with low noise figure can be achieved simultaneously. The role of a
source degenerated inductor (Ls) here is to match the input impedance to 50 Ω with low noise.
From Figure 4 (c), it can be seen that the noise is increasing with Lsource .Thus the optimum value
of source at a minimum noise figure is chosen to be 0.27 NH.
(a)
(b)
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65
(c)
(d)
(e)
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66
(f)
Figure 4. Simulation results using NSGA-II (a) Noise vs. Gain vs. Width of the transistor, (b) Noise vs.
Gain vs. Overdrive voltage, (c) Noise vs. Lsource (d) Power dissipation vs. Lsource , (e) Gain vs. Lsource &
(f) Power vs. Noise vs. Gain
The effect of variation of a source inductor in power consumption can be seen from Figure 4 (d),
where it can be seen that with the increase in value of source degeneration inductor; power
dissipation reduces. But, for RF design the inductor should not be bulky. There always exists a
trade-off among power dissipation, gain and noise figure for a Low Noise Amplifier design. The
same can be seen in Figure 4 (e). While, from Figure 4 (f), it can be seen that the gain reduces
with the increase in value of the source degenerated inductance. Thus, Lsource = 0.2 nH has been
chosen as further optimized value which gives the best compromise between gain and noise
figure trade-off.
5.2. Simulation of LNA using Specter RF
The initial start up values given after running NSGA-II algorithm has been used for the designing
of CMOS Low Noise Amplifier for 0.18 µm technology. The design is finally simulated using the
Cadence Specter design tool. Figure 5 shows the proposed current reused LNA design. The S-
parameter analysis is performed to obtain the gain and noise figure parameters. Also parallel LC
tank circuit at the output tunes to the resonating frequency of 4 GHz. Capacitors at the input and
output are dc blocking capacitor. The source terminal inductor (Ls) needs to be properly design to
have a 50 Ω input matching. The dc blocking capacitors has been chosen to be of 103 fF each.
While Lg is calculated from Eq. (13), once the optimum value of Ls is chosen to be 0.2 nH.
Usually the value of a lead is picked up from the available literature as references and accordingly
the parallel tuning capacitor needs to be tuned to operate at 4 GHz frequency. The value of bias
resistor, Rbias, is chosen to be large to minimize the noise entering into the design.
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Figure 5. Proposed current reused two stage LNA
5.2.1. Parametric analysis
The parametric analysis is used for automating the generation of multiple simulations to test the
effect of a source degeneration inductor (Ls) variation on the small signal gain (S21). Ls is sweep
from 50 pH to 200 pH as shown in Figure 6. It is observed that for 3-5 GHz band gain flatness is
good for Ls as 200 pH, so, Ls is chosen to be 200 pH.
Figure 6. Parametric Analysis for Small Signal Gain
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Figure 7. Overall S-parameter response of Single stage LNA
5.2.2. S-Parameter analysis
The simulated S-parameter results are as shown in Figure 7. The simulated results show that the
LNA has a maximum flat gain of + 22 dB from 3 to 5 GHz band. Also, Figure 8 shows a smith
chart analysis plots for input impedance matching. From smith chart it can be seen that the real
part of the impedance is matched to 47 Ω. Thus minimum input and output return loss of < -10
dB each can be observed for 3 to 5 GHz. The input and output return losses have to be further
improved by proper matching. The LNA also attends a high reverse isolation (S12) of < - 40 dB
for 3 to 5 GHz.
Figure 8. Input Impedance Matching using smith chart
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69
5.2.3. Stability analysis
In the presence of feedback paths from the output to the input, the circuit might become unstable
for certain combinations of source and load impedances. An LNA design that is normally stable
might oscillate at the extremes of the manufacturing or voltage variations, and perhaps at
unexpectedly high or low frequencies. The Stern stability factor characterizes circuit stability as
in equation below:
Kf= 1+|βf |2
-|S11|2
-|S22|2
/ 2|S21||S12| (10)
Figure 9. Stability Analysis
Where, βf = S11S22-S21S12 , If Kf >1 and βf < 1, then the circuit is unconditionally stable. The
stability evaluation for the S parameters over a wide frequency range has been done to ensure that
the Kf remains greater than one for all frequencies. As the coupling (S12) decreases, that is as the
reverse isolation increases, stability improves. One can use the techniques such as resistive
loading and neutralization to improve stability for an LNA [11]. Stability analysis shows that Kf
>1 and βf < 1 across the frequency band of interest, stating that designed LNA is un-conditionally
stable as shown in Figure 9.
5.2.4 Linearity analysis
Linearity is also important parameter for LNA design along with gain. The linearity limits the
actual power that can be drawn to the load by the LNA. The linearity is simulated using periodic
steady-state (PSS) analysis. Figure 7 shows the linearity analysis with P1dB compression point of
-6.46719 dBm at 4 GHz.
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70
Figure 10. P1dB compression point
5.2.5. Noise analysis
The overall noise figure (NF) and minimum noise figure (NFmin) of 2.31 dB and 2.1 dB
respectively can be seen from Figure 11 for cascade common source with current re-use feedback.
Table-1 shows the performance summary of the proposed low noise amplifier and its comparison
with the previously reported LNA designs. At the time of designing parasitic play important role
in obtained results but here we are not considering them because our first motivation is to take
initial guess of the values. The design parameters obtained from multi objective genetic algorithm
is comparable with the result obtained in Cadence Spectre tool.
Figure 11. Noise Figure plots for two stage LNA
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71
Table 1 Comparison of Wideband LNAs: Published and the optimized LNA design parameters
Proposed LNA designs Previously Reported LNA Designs
Targeted parameters
Optimized two stage
LNA design with
current re-used using
NSGA-II [15][16] [17] [18]
Technology 0.18µm CMOS 0.18µm CMOS
0.65 µm
CMOS
0.18 µm
CMOS
0.18 µm
CMOS
Frequency of
Operation 3-5 GHz 3-5 GHz 0.2-5.2 GHz 1-5 GHz 3-5 GHz
Supply
Voltage 1.8 V 1.8 V 1.2 V 1.8 V 1.8 V
Gain
20 dB
22 dB 13-15.6 dB 11-13.7 dB 8.6-9.5 dB
S11 < -10 dB < -10 dB *** <-10 dB <-10.3 dB
S22 < -10 dB < -10 dB *** *** -11.8 dB
S12 < -10 dB -40 dB *** *** ***
NF < 4 dB 3.5 dB < 3.5 5-6.5 dB 2.7 dB
NFmin < 3 dB 3 dB *** *** ***
P1dB < -10 dBm -6.46719 *** *** ***
Power < 15 mW 12.5 mW *** 9 mW 15 mW
Note: *** Not mentioned
6. SCOPE AND LIMITATION OF DESIGNED TOOL
Designed optimization tool gives only approximate values of the design parameters. This tool is
designed only for final stages of RFIC design process. Parasitic effects associated with passive
on-chip components like capacitors, inductors and resistors have not been taken into account for
shorter simulation time of the circuit.
7. CONCLUSION
This paper shows that the optimization of RF Circuits is possible with real coded genetic
algorithm. It is found that real coded Multi-Objective Genetic Algorithm has many advantages
over binary coded genetic algorithm. Non-Dominated Sorting Genetic Algorithm is used for
optimization tool, which is giving comparative results with design software simulation like
Cadence Spectre tool. In this paper it is shown that the Low Noise Amplifier can be designed for
the noise figure of 3.5 dB and power gain of 22 dB. The two stage LNA topology with current
reused technique is designed and optimized for 3-5 GHz UWB applications. The simulated S11
and S22 parameters are well below – 10 dB is obtained with the simple matching network for the
desired band of 3-5 GHz. The designed LNA dissipates 22 mW of power out of 1.8 V supply.
Also the proposed LNA design is found to be unconditionally stable and operates linearly
throughout the desired band. A comparison between the present results and the results of
previously reported LNA shows that the reported LNA design reaches the state-of-the-art LNA
designs for UWB application. In future; the NSGA-II optimization tool can be used to extend for
3.1-10.6 GHz LNA design for ultra-wide-band wireless RF system. Thus the design tool is useful
in finding circuit element values quickly reducing the RF circuit designer time.
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72
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AUTHORS
Vishakha P. Bhale received B.E. (Electronics and Telecommunication) and M.E. (Digital
Electronics) in 2002 and 2006 respectively. Presently she is pursuing Ph.D. in RF circuit
designs for wireless communication application using VLSI design. Her area of interest
is analogue RF circuit designs, Low power VLSI designs, Wireless communication
system designs for portable applications.
Dr. Upena Dalal received the B.E. in Electronics from SVRCET, Surat in 1991 and
obtained M.E. (Electronics & Communications) from DDIT, Nadiad with Gold Medal.
Presently she is working as Associate Prof. in Electronics Engineering Department, Sardar
Vallabhbhai National Institute of Technology (SV NIT), Surat,Gujrat, India. She ha s 20
years of academic experience. She has published 70+ conference and journal papers at
national and international level. Her book on “Wireless Communication” is published by
Oxford University Press in July 2009. One more book edited by her and Dr Y P Kosta
titled “Wi-MAX New Developments” is published by Intech, Vienna, Austria. She has organized 8 National
level training programs and two international conferences. She is a LM of several technical technical bodies.