Clock gating

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Clock gating

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  • "Clock Gating" An Effective Low-Power Technique
  • "Clock Gating" An Effective Low-Power Technique
  • Clock gating

    1. 2. <ul><li>Power Consumption Primitives </li></ul><ul><li>Characteristics of Power Consumption in </li></ul><ul><li>Microprocessors </li></ul><ul><li>Clock Gating and Power Reduction </li></ul><ul><li>Similar Approaches </li></ul><ul><li>Power Reduction Example </li></ul>
    2. 3. <ul><li>P (total) = P (static) + P (dynamic) </li></ul><ul><li>Static Power </li></ul><ul><ul><li>Currently Negligible </li></ul></ul><ul><ul><li>But Considerable in Future </li></ul></ul><ul><li>Dynamic Power </li></ul><ul><ul><li>P (dynamic) = C L V dd 2 . A .F </li></ul></ul><ul><ul><li>Major Part of Total Power (e.g. 95%) </li></ul></ul>
    3. 4. <ul><li>Clock Circuitry Power Consumption </li></ul><ul><ul><li>15 to 45% of Total </li></ul></ul><ul><ul><li>P (clock circuitry) ~ Frequency </li></ul></ul><ul><li>Activity of Functional Units </li></ul><ul><ul><li>A (units) < 50% in Execution Time </li></ul></ul>
    4. 5. <ul><li>Clock tree consume more than 50 % of dynamic power. The components of this power are: </li></ul><ul><li>Power consumed by combinatorial logic whose values are changing on each clock edge </li></ul><ul><li>2) Power consumed by flip-flops and </li></ul><ul><li>3) The power consumed by the clock buffer tree in the design. </li></ul>Clock Gating and Power Reduction
    5. 6. <ul><li>There are two types of clock gating styles available. They are: </li></ul><ul><li>Latch-based clock gating </li></ul><ul><li>2) Latch-free clock gating. </li></ul>
    6. 7. Latch free clock gating
    7. 8. Latch based clock gating
    8. 9. <ul><li>Main Idea </li></ul><ul><ul><li>Clock Circuitry Partitioning </li></ul></ul><ul><ul><li>Shutting down Unused Partitions </li></ul></ul><ul><li>Implementation </li></ul><ul><ul><li>Creating Local Clocks </li></ul></ul><ul><ul><li>Buffers or Flip-Flops with enable signal </li></ul></ul><ul><li>Net Effects </li></ul><ul><ul><li>Reduction of Unnecessary Switching </li></ul></ul><ul><ul><li>Switched Capacitance Reduction of Clock Circuitry </li></ul></ul><ul><ul><li>Power Consumption Reduction </li></ul></ul>
    9. 10. <ul><li>How to determine unused modules? </li></ul><ul><ul><li>Dynamically in Decode Stage </li></ul></ul><ul><ul><li>Statically with Compiler Assistance </li></ul></ul><ul><li>Disadvantages </li></ul><ul><ul><li>Additional Circuitry </li></ul></ul><ul><ul><li>More Complicated Timing Analysis, Design, Test and Verification </li></ul></ul><ul><ul><li>Possible High L x di/dt Noise </li></ul></ul>
    10. 11. <ul><li>Data Gating </li></ul><ul><ul><li>Effective in Wide Modules Like ALUs </li></ul></ul><ul><ul><li>Complicated Design </li></ul></ul><ul><ul><li>Possible Increase of Critical Path Delay </li></ul></ul><ul><li>Powering Down Unused Modules </li></ul><ul><ul><li>Possible Long Wake-up Times </li></ul></ul><ul><ul><li>Need of Compiler and/or OS Support </li></ul></ul><ul><li>Using Asynchronous Systems </li></ul><ul><ul><li>Unnecessary Activity Elimination </li></ul></ul><ul><ul><li>Harder Design </li></ul></ul>
    11. 12. Components - flip-flops, latches, ALU, adder, and shifter Functions - decode, execute, and load store unit Power Reduction Example
    12. 13. <ul><li>Clock Gating as an Architectural Technique </li></ul><ul><li>Turning Unused Parts of Circuit Off </li></ul><ul><li>High P(dynamic)/P (total) Ratio </li></ul><ul><li>Decrease of Activity to Reduce Power </li></ul><ul><li>Considerable Power Reduction (up to 25%) </li></ul><ul><li>Highly Used Technique </li></ul>Summary

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