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Flipflops JK T SR D All FlipFlop Slides. Uploaded by SidRehmani.
Jk flip flop presentation, T flip flop presentation, D flip flop presentation, D flip flop presentation.
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This presentation is all about counters, focusing on synchronous and asynchronous counters. The unique feature is the incorporation of the circuit images generated from MULTISIM software imparting practical knowledge to the users.
Flipflops JK T SR D All FlipFlop SlidesSid Rehmani
Flipflops JK T SR D All FlipFlop Slides. Uploaded by SidRehmani.
Jk flip flop presentation, T flip flop presentation, D flip flop presentation, D flip flop presentation.
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The Microprocessor System. A semester course review. Summarize important points for whole subject. Using the 8051 architecture as the practical and projects development.
This project is based on Data Path Architecture which consists of Shift register, MAC Unit, 16-Bit ALU and Tri-State Buffer. This whole architecture is implemented by using VHDL and simulated by using Modelsim.
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Addressing mode and instruction set using 8051logesh waran
1. Immediate addressing mode:
In this type, the operand is specified in the instruction along with the opcode. In simple way, it means data is provided in instruction itself.
Ex: MOV A,#05H -> Where MOV stands for move, # represents immediate data. 05h is the data. It means the immediate date 05h provided in instruction is moved into A register.
2.Register addressing mode:
Here the operand in contained in the specific register of microcontroller. The user must provide the name of register from where the operand/data need to be fetched. The permitted registers are A, R7-R0 of each register bank. Ex: MOV A,R0-> content of R0 register is copied into Accumulator.
3. Direct addressing mode:
In this mode the direct address of memory location is provided in instruction to fetch the operand. Only internal RAM and SFR's address can be used in this type of instruction.
Ex: MOV A, 30H => Content of RAM address 30H is copied into Accumulator.
4. Register Indirect addressing mode:
Here the address of memory location is indirectly provided by a register. The '@' sign indicates that the register holds the address of memory location i.e. fetch the content of memory location whose address is provided in register.
Ex: MOV A,@R0 => Copy the content of memory location whose address is given in R0 register.
5. Indexed Addressing mode:
This addressing mode is basically used for accessing data from look up table. Here the address of memory is indexed i.e. added to form the actual address of memory.
Ex: MOVC A,@A+DPTR => here 'C' means Code. Here the content of A register is added with content of DPTR and the resultant is the address of memory location from where the data is copied to A register.
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Looking for the best engineering colleges in Jaipur for 2024?
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10) JNU
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2. Outline
• 8051 Programmer’s Model
• Addressing Modes
• Data Movement Instructions
• Arithmetic Instructions
• Logical Instructions
• Shift Instructions
• Bit Manipulation
• Program Control Instructions
Dr. Noorullah Shariff
3. 8051 Introduction
• 8 bit Data bus, 16 bit Address bus
• Many Special Function Registers (SFRs) for
control and I/O
Dr. Noorullah Shariff
4. 8051 Programmer’s Model (1)
Program Memory
OR
FFFF
0000
FFFF
0000
1000
0FFF
if EA = 1 if EA = 0
• All instructions
• Constant Data
(Using MOVC)
64 K
External
60 K
External
4 K
Internal
0
7
7
0
Data Memory
SFRs
RAM
80
FF
00
7F
AND
Direct
Direct , Register,
Reg. Indirect
FFFF
0000
64 K
External
(Using MOVX)
@R
@DPTR
Internal
Dr. Noorullah Shariff
5. 8051 Programmer’s Model (2)
Port 0
Stack pointer
Data pointer DPTR
Power Control
timer/counter control
timer/counter Mode
timer 0 Low
timer 1 Low
timer 0 High
timer 1 High
Port 1
Serial Control
Serial Data Buffer
Port 2
Interrupt Enable Ctr 1* IE
* P2
SBUF
* SCON
* P1
* TH1
* TH0
* TL1
* TL0
TMOD
* TCEN
PCON
DPH
DPL
SP
* P080
81
82
83
87
88
89
8A
8B
8C
8D
90
98
A0
99
A8
* P3
* IP
* PSW
* ACC
* BF0
FF
E0
D0
B8
B0
SFRs
SFRs 7F
00
08
10
18
20
30
Scratch Pad Area
RAM
Bit Addressable RAM
Bank 3
Bank 2
Bank 1
Bank 0
R0
R7
R0
R7
R0
R7
R0
R7
Select Bank
with
PSW.4 , .3 =
RS1, RS0
Bit #00 7F OR
20.0 2F.7
* = Bit Addressable
Dr. Noorullah Shariff
6. 8051 Addressing Modes (1)
• Immediate - # Label or Number
MOV R6,#14 ; R6 14 10
MOV A,#0CAh ; Acc CA 16
MOV DPTR,#loc ; DPTR value of symbol “loc”
• Direct - Label or Number
MOV PSW,R5 ; M(PSW) R5
MOV A,045h ; Acc M(45 10)
• Register - Rn
MOV R1,A ; R1 Acc
MOV B,R3 ; B R3
Dr. Noorullah Shariff
7. 8051 Addressing Modes (2)
• Register Indirect - @R0, @R1, @DPTR
MOV @R0,#250 ; M(R0) 250 10
MOV A,@R1 ; A M(R1)
MOVX @DPTR,A ; External data M(DPTR) A
• Register Indirect Indexed - @A+DPTR, @A+PC
MOVC A,@A+DPTR ; A ROM(A+DPTR)
MOVC A,@A+PC ; A ROM(A+PC)
JMP @A+DPTR ; PC (A+DPTR)
• Bit - bit number or label.bit or bit label
MOV C,IE.0 ; CY bit 0 of IE reg (EX0)
MOV C,EX0 ; same
SETB 07Fh ; Bit 7F 1
SETB 2F.7 ; same
Dr. Noorullah Shariff
8. 8051 Instructions
• Instruction Classes
– Data Movement
– Arithmetic
– Logical
– Shift
– Bit Manipulation
– Program Control
Dr. Noorullah Shariff
9. 8051 Data Movement - 1
MOV R, # Rn
D
A
MOVE
MOV A, # A Immediate
D A Direct
R A Register
@R A Register Indirect
MOV D, # Direct
D
R
@R
A
MOV @R, # Register Indirect
D
ADr. Noorullah Shariff
10. 8051 Data Movement - 2
• Move External Data RAM
MOVX A, @R
A, @DPTR
MOVX @R, A
@DPTR, A
Move From Program Memory
MOVC A, @A+DPTR Acc Rom(A+DPTR)
A, @A+PC Acc Rom(A+PC)
Others
PUSH D SP SP+1, m(SP) D
POP D D m(SP), SP SP - 1
XCH A, R SWAP Acc Rn
D
@R
Dr. Noorullah Shariff
11. 8051 Arithmetic - 1
ADDC A, # Acc A+Immediate+Carry
D
R
@R
Add/Subtract
ADD A, # Acc A+Immediate
D
R
@R
SUBB A, # Acc Acc-Immediate-Carry
D
R
@R
Dr. Noorullah Shariff
12. 8051 Arithmetic - 2
Inc/Dec
INC A Acc Acc+1
D
R
@R
DEC A Acc Acc-1
D
R
@R
Mul/Div
MUL AB B:A Acc * B (unsigned)
DIV AB A Quo ( A/B ) (unsigned)
B Rem( A/B )
Dr. Noorullah Shariff
13. 8051 Logical
• Other
CLR A Acc 0
CPL A Acc Acc
SWAP A Acc(7-4) Acc(3-0)
AND,OR,XOR
AND A, #
ORL D
XRL R
@R
D, A
D, #
Dr. Noorullah Shariff
15. 8051 Bit Manipulation - 1
Clear/Set/Complement
CLR C Carry 0
bit bit 0
SETB C
bit
CPL C
bit
And, Or, Move
ANL C, bit Carry Carry AND bit
C, /bit Carry Carry AND bit
ORL C, bit
C, /bit
MOV C, bit
bit, C
Dr. Noorullah Shariff
16. 8051 Bit Manipulation - 2
Jump
JC label Jump if Carry set
JNC label Jump if Carry clear
JB bit, label Jump if bit set
JNB bit, label Jump if bit clear
JBC bit, label Jump if bit set, then clear bit
label = PC relative (+ 127)
Dr. Noorullah Shariff
17. 8051 Program Control - 1
Jump
AJMP label-A Absolute Jump- 11 bits(2K)
LJMP label-L Long Jump - 16 bits (64K)
SJMP label Short Jump
JMP @A+DPTR Jump Indirect PC (A+DPTR)
JZ label Jump if zero
JNZ label Jump if not zero
Compare and Jump
CJNE A, #, label Compare 1st
op to 2nd
op and
A, D, label jump to label if not Equal
R, #, label
@R,#, label
Dr. Noorullah Shariff
18. 8051 Program Control - 2
Decrement and Jump
DJNZ R, label Rn = Rn-1 , Jump if not zero
D, label
Subroutines
ACALL label-A Absolute Call - 11 bits (2K)
LCALL label-L Long Call - 16 bits (64K)
RET Return from Subroutine
RETI Return from ISR
PC m(SP), SP SP-2
Dr. Noorullah Shariff
19. example of delay
mov a,#0aah
Back1:mov p0,a
lcall delay1
cpl a
sjmp back1
Delay1:mov r0,#0ffh;1cycle
Here: djnz r0,here ;2cycle
ret ;2cycle
end
Delay=1+255*2+2=513 cycle
Delay2:
mov r6,#0ffh
back1: mov r7,#0ffh ;1cycle
Here: djnz r7,here ;2cycle
djnz r6,back1;2cycle
ret ;2cycle
end
Delay=1+(1+255*2+2)*255+2
=130818 machine cycle
20. Long delay Example
GREEN_LED: equ P1.6
org ooh
ljmp Main
org 100h
Main: clr GREEN_LED
Again: acall Delay
cpl GREEN_LED
sjmp Again
Delay: mov R7, #02
Loop1: mov R6, #00h
Loop0: mov R5, #00h
djnz R5, $
djnz R6, Loop0
djnz R7, Loop1
reset service
main program
subroutine