The document provides an overview of semiconductor technology and industry. It discusses the history and evolution of transistor technology from the point contact transistor to today's nanowire transistors. It describes Moore's law and how transistor counts have increased exponentially over time due to scaling. The document also outlines the semiconductor manufacturing process and describes the infrastructure required for wafer fabrication facilities. It analyzes cost structures, yield optimization, and industry consolidation trends. Finally, it discusses future opportunities around applications like 5G, AI, and big data driving demand rather than technology alone.

1. An Overview of Semiconductor
technology & Industry
Dr. Len Mei
2018/11/14
1

2. Agenda
• Technology
• Industry and Factory
• Economics
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3. 11/14/2018
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4. How technology started
On Dec.,23,1947, John
Bardeen and Walter
Brattain demonstrated a
point contact transistor
at Bell Lab
On July 4, 1951, William
Shockley built and
demonstrated a junction
transistor
Three of them won 1956
Nobel prize of Physics
4

5. Kilby’s integrated circuit 1958
 On September 12,
1958 Jack Kilby at
Texas Instrument put
two transistors on the
same Silicon.
 Integrated circuit
was born (2000 Nobel
prize of Physics)
5

6. Moore’s Law
• Moore’s Law: Gordon Moore, founder of Intel,
predicted that the number of transistors on
integrated circuit could double every two years.
• Semiconductor industry today is a $460 billion
industry.
• Semiconductor is the foundation of trillion
dollars electronics industry
6

7. Number of transistors per area
copy right by Dr. Len Mei 2017
7

8. Transistor count increases because it
becomes smaller…
8
In 2018, the most
advanced IC
production is using
7 nm technology.

9. Number of transistors per chip
9

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Intel 4004 – 2,300 transistors – 10 um
Intel’s integrated circuit 1970
The industry of IC was born.

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Intel 10 core xeon westmere – 2 billion transistors – 32 nm
2018
A12, Kirin 980 are
made at TSMC
Snapdragon is made
at Samsung
7 nm, 6.9 b transistors
7 nm
10 nm, 5.3 b transistors 7 nm, 6.9 b transistors
Integrated circuits 2018

12. Cross section of
an Integrated
Circuit
transistor
Minimum feature size
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13. 3D view of integrated circuit
Oxide removed
Silicon substrate
Poly silicon
Metal conductor
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14. Size comparison
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40 nm

15. 15
Transistor/ wafer
=
Chair/ Brazil
=
6 * 106

16. Limits of scaling
16

17. Large and small transistors
• Scaling factor κ
17
Substrate doping must increase to reduce
the depletion layer thickness in source and
drain.
gate
source drain
Electron flow
Operation voltage
Gate oxide
Depletion layer
N+ N+
P

18. 18
α = reduction of dimension/ reduction of voltage.
α = 1.75 ~ 5

19. Ideal shrink
• All dimensions reduce by κ
• Substrate doping for both NMOS Na, PMOS Nd
must increase by κ to keep the same depletion
layer thickness
• Power supply must reduce by κ to keep the same
electrical field across gate
• Capacity of transistor reduces by 1/ κ, but not by
1/ κ2 because gate oxide becomes thinner
• Inversion charge per transistor keeps the same
(Q=CV)
19

20. Ideal shrink
• Circuit delay τ is proportional to capacitance,
thus reduces by 1/ κ. Frequency f is the inverse
of τ .
• Power dissipation per transistor is due to the
charging and discharging of transistor load. P =
CV dd
2
f = Q Vdd f = i Vdd.
• Power density is the power dissipation per area,
is thus unchanged.
20

21. Chip frequency improvement
21

22. Actual shrink
• Actual shrink is non-ideal because
▫ Threshold voltage is limited by Silicon property
▫ At low Vdd, signal to noise ratio decreases
▫ At small geometry, parasitic resistance and
capacity increases.
▫ Transistors become more leaky
▫ Vds SAT=Vgs - Vth
• Therefore, Vdd cannot shrink by κ. Rather,
• α = κ / reduction of voltage.
• α = 1 ~ 5
22

23. VDD scaling from 1.4 um to 0.1 um
23
90 nm
α = 1
α=1.5

24. VDD scaling from 0.25 um to 10 nm
24
Conventional transistor
α=1.5
α=2.75
α=5

25. Smaller transistors => more leakage
• Gate leakage: When gate oxide becomes thinner,
high electrical field across oxide causes higher
gate tunneling current.
• Subthreshold leakage: When gate becomes
smaller faster than the Source Drain voltage
becomes smaller, field across Source/Well and
Drain increases, causing higher ionization.
• Holes created by ionization flow to substrate
causing leakage.
25

26. Leakage currents = gate leakage +
substrate leakage + subthreshold
leakage
26
Substrate leakage
Gate leakage
Subthreshold leakage
GIDL current
ionization
Junction
leakage

27. Shrink of gate oxide thickness
27

28. Gate tunneling current increases for
smaller transistors
28

29. Short channel effect
29
Short channel Long channel
DSDS
Blue region = most negative voltage, Red region = most positive voltage

30. Short channel effect
30
long
When channel shortens, potential drop at depletion regions
merges.
long short
Channel length
Drain Induced
Barrier Lowering
DIBL

31. 31
Source
Drain
Gate
Substrate
V
VDS
VGS
Gate oxide surface

32. Gate leakage vs. subthreshold leakage
32
Gate leakage
Subthreshold leakage
Subthreshold leakage is sensitive to T

33. Steep subthreshold FET
33
current
Gate voltage
Threshold voltage Vth
Ideal subthreshold slope
Steep subthreshold slope
Non-ideal subthreshold slope
VDD
Steep SS FET
Subthreshold slope =
decade of current/mv

34. Transistor evolution
• Alumium gate before 1978
• Poly gate 1978
• Silicide gate 1984
• Lightly Doped Drain (LDD) with Oxide spacer
transistors 1990
• High k gate oxide transistors 2006
• FinFET 2009
• Nanowire transistor 2019.
34

35. LDD (Lightly Doped Drain or oxide
spacer) transistor
35

36. High k gate oxides (hafnium dioxide ,hafnium
silicate, zirconium silicate, and zirconium dioxide)
36

37. FinFET
37
Conventional transistor FinFET transistor
Field is applied in one direction. Field is applied in three directions.
Technology node <30 nm

38. Nanowire transistor
38
Field is applied in all directions.

39. Nanowire transistor
39

40. Vertical nanowire transistors
40
Nanowire transistor is also known
as gate all around (GAA) transistor.

41. Array of vertical nanowire transistors
41

42. Nanowire transistor opens up
possibility of 3D integrated circuits
42

43. Limits of interconnection
Thinner interconnection => higher parasitic
resistance
Thinner dielectric => higher parasitic
capacitance
43

44. IC going 3D, and chip level packaging
• When devices cannot be shrunk anymore, they
are going 3D.
▫ 3D in wafer processing such as 3D NAND
▫ 3D in packaging
▫ WLP allows chips using different technologies,
such as DRAM, NAND and logic processed
separately.
44

45. 45

46. 46

47. 47

48. 48

49. 3D packaging
49

50. 11/14/2018
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51. Industry (by products)
• Memory (Samsung, SK Hynix, Micron, Sandisk,
Toshiba)
• Microprocessors and communication chips
(Intel, AMD, Samsung, ARM, Qualcom)
• Application specific chips ASIC (Broadcom,
Toshiba, Samsung, Nvidia, STM, Infineon)
• Mixed signal and analog chips (Analog Devices,
NXP, Infinion)
• Foundry (TSMC, Global Foundry, UMC, SMIC)
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52. Industry – (by business model)
• IDM (integrated device manufacturer) – Intel,
STM, Samsung, Toshiba, Micron, SK Hynix
• Fabless design houses – Nvidia, Qualcom,
Broadcom
• Foundry – TSMC, UMC, Global Foundry, SMIC
Design
(fabless company)
Manufacturing
(foundry)
Design and Manufacturing (IDM)
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53. Top 8 semiconductor companies 2017
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1) Intel. Sales: $56.31 billion (IDM)
2) Samsung. Sales: $43.54 billion. .(IDM)
3) Taiwan Semiconductor Manufacturing
Company. Sales: $29.32 billion. (Foundry)
4) Qualcomm. Sales: $15.44 billion. .(Design)
5) Broadcom. Sales: $15.33 billion. ...(Design)
6) SK Hynix. Sales: $14.23 billion. ...(IDM)
7) Micron Technology. Sales: $12.84 billion.(IDM)
8) Texas Instruments. Sales: $12.35 billion (IDM).

54. Worldwide semiconductor market
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55. Wafer fab
• Wafer fab is a highly specialized factory
• Cleanroom –
▫ temperature,
▫ humidity,
▫ vibration,
▫ particle,
▫ air flow,
▫ electrostatic charge,
▫ electromagnetic wave
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56. Utilities
• Power - power substation (80KVA), power
distribution, emergency power, backup power,
• Water (300CMH) - DI water, cooling water,
• Bulk gases -N2, O2, compressed air
• Specialty gases, natural gas
• Chemicals,
• Exhaust piping, exhaust treatment,
• Liquid waste drain, waste treatment plant
• Factory automation (MES), AMHS, equipment
automation, data automation
56

57. Fab automation
• Equipment automation..
▫ Allows each equipment to operate by itself at a
push of bottom
▫ Collects operation data
• Factory automation
▫ Wafer transport system
▫ Manufacturing execution system
• Data automation
▫ Collect equipment data, operation data
▫ Monitor and analyze data in real time
57

58. 58

59. 59

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Cooling water system for cleanroom

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Power panels for equipment

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Exhaust system

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Nitrogen plant

67. Principle of cleanroom
• Cleanroom controls temperature, humidity,
vibration and particle
• Temperature, particle, humidity are controlled
by
▫ Take outside air
▫ Cools down to condense vapor
▫ Heats up to desired temperature 21C
▫ Inject vapor to desired humidity 45%
▫ Filter through HEPA filter
▫ Create laminar flow
67

68. 68

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Cleanroom waffle floor
Under construction

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Cleanroom ready for
equipment
installation

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Len

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Yellow light room for photolithography

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An implanter under
installation

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An implanter installed

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Photolithography room

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stocker

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Intra bay AMHS
Interbay AMHS
stockers
Typical wafer fab layout
equipment bay

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Interbay AMHS

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Intrabay AMHS

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stocker

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82. Cost
 Manufacturing cost - wafer
▫ Substrate cost (10%)
▫ Equipment depreciation cost (50%)
▫ Labor cost (8%)
▫ Materials cost (13%)
▫ Equipment maintenance cost (13%)
▫ Utility cost (6%)
Manufacturing cost – packaging and testing
 R&D cost
o Process development
o Product design
Marketing/ sales cost
Administration cost
Financial cost
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83. Largest variation of cost - yield
Yield = number of good chips / total chips on a
wafer
Yield loss can happen at every step of
manufacturing
▫ In-line – scrap, rework
▫ DC parameter test – downgrade
▫ Wafer sort - probe yield
▫ Packaging yield loss
▫ Burn-in yield loss
▫ Final test yield loss
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84. Yield loss
• Defects (systematic and random)
• Process deviation
• Mis-operation
• Bad quality materials
• Utility problems
• Process windows vs design windows
• Capability of equipment
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85. Racing against time – new technology
introduction
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• When new technology is introduced, yield is low,
therefore, cost is high
• When yield is improved, cost is reduced
• However, the price also drops
• The cost has to be reduced faster than the price
drops in order to guarantee a window of profit

86. Window of profit for product life
86
cost
price
time

87. Technology drives demand
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88. Technology drives demand
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Microprocessor and memory speed

89. Cost of wafer fab vs. market size
Cost of a typical fab $500 m
Total worldwide market $120 b
Ratio of 240 to 1
Cost of a typical fab $10 b
Total worldwide market $430 b
Ratio of 43 to 1
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90. Cost goes up x6 faster than sales
• In 18 years, the market size only doubled, but
the cost of factory increase by 12 times
• That means cost increases 6 times faster than
sales
▫ 193 nm scanner costs $60 m each and EUV
scanner costs >$120 m
▫ Number of process steps increase from 200 to 700
=> more labor, more materials, more utilities
▫ Sales price drops (such as computer/ TV/ cell
phone/ digital camera)
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91. The rise of foundry business model
• Before 1990, semiconductor industry was
dominated by IDM (Integrated device
manufacturer).
• After 2000, semiconductor industry is
dominated by design houses and foundry
(except for memory).
• Even design houses are becoming capital
intensive. A mask set for 20 nm chip costs >$1
million
91

92. Consolidation has happened
• Each generation of technology costs $500 m to
develop
• Technology becomes obsolete quickly. New
technology means better performance, lower
cost.
• Any company less than $10 b can neither afford
to build a new fab or to develop new technology
(8 semiconductor companies > $12 b)
• Trend is for consolidation.
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93. Return on investment is not
guaranteed
• However, the investment (R&D and factory)
does not guarantee returns because
▫ Technology development may not be successful
▫ Margin is ultra thin
▫ The market size is barely sufficient to allow top 2
companies in each business area to be profitable
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94. NAND market
• NAND is the key component of data storage.
• Data storage is the corner stone of data center.
• Data center drives cloud computing, internet,
Big Data, blockchain, Fintech and artificial
intelligence, and is the most important
infrastructure of 21st century.
• The country which controls NAND is like the
country which controls petroleum in 20th
century.
94

95. What is the future
• End of technology roadmap is in sight. In a
decade, transistor will be only few atoms big.
• Market will be driven by applications rather than
semiconductor technology.
• Applications like 5G, Big Data, cloud computing,
artificial intelligence, blockchain will drive
demand
• In the past, the leader is the company that can
evolve new technology sooner than others
• In the future, the leader is the company that can
have the most efficient production
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96. Evolution of business model
96
Chip design
and sales
Chip
foundry
System
integration
System house
Design house
Fab
Chip design
and sales
In house fab
System
integration
Chip design
and sales
Chip
foundry
System
integration
PAST NOW FUTURE

97. Summary
• By 2025, semiconductor industry will face the
end of technology development and Moore’s law
will breakdown
• By then, semiconductor industry can only grow
with diversified applications rather than higher
performance.
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