Advanced lithographic technologies

2009/07/17 copy right by Dr. Len Mei 2017 1
Dr. Len Mei
Discussion on Advanced
Semiconductor
Photolithographic
Technologies

Moore’s Law and
Photolithography
 Moore’s Law is mostly enabled by photolithographic
technology
 To print smaller feature size, light of smaller
wavelength is needed to minimize light interference
and diffraction.
22009/07/17

copy right by Dr. Len Mei 2017 3

Number of transistors per area

Equations of photolithograpy
 NA is the numerical aperture
 n is the refraction index
 λ is the wavelength
 Θ is the maximum half focal
point angle
 DOF is depth of focus
 к1 is a constant 0.4
 Imax and Imin are the
maximum and minimum
intensity

Index of refraction n and
wavelength λ
 Two ways to improve resolution:
 Make wavelength λ smaller
 Make n larger
 For air, n = 1
 For water, n = 1.33
 For oil, n = 1.52
 λ smaller: 436 nm, 365 nm, 248 nm,
193 nm

Wavelength vs. technology
copy right by Dr. Len Mei 200907 72009/07/17
ArF DUV 193 nm
4:1 KrF DUV 248 nm
5:1 G-line 436 nm
5:1 I-line 365 nm
VisiblelightDeepUV
EUV 13.5 nm
EUV
1:1 G-line 436 nm
157 nm EUV was abondaned.
immersion
visible
invisible

Spectrum
EUV 13.5 nm
DUV 248 nm, 193 nm
G line 436 nm
i line 365 nm
Limit of semiconductor 3 nm
Size of atom 0.3 nm
Size of virus 100 nm

Wavelength to resolution ratio
Wavelength Resolution Ratio
436 nm 1 um ~0.5
365 nm 0.5 um ~0.7
248 nm 0.2 um ~1.3
193 nm 60 nm ~3
193 nm immersion 20 nm ~10
13.5 nm 7 nm ~2
Wavelength must be smaller than the
printed feature size.

Photolithographic technology
development at user side
(wafer fab)

Technologies to compensate
wavelength longer than the dimension
of patterns
 All other techniques to enhance resolution
are generally known as Resolution
Enhancement Technique (RET)
 RET above 60 nm
 Optical proximity correction (OPC)
 Off axis illumination (OAI)
 Phase shift mask (PSM)
 Hard mask (HM)
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Technologies to compensate
wavelength longer than the dimension
of patterns
 Below 60 nm, additional technologies are
required:
 Double patterning (DP)
 Multiple patterning (MP)
 Restricted design rules (RDR)
 Gridded design rules (GDR)
 Source mask optimization (SMO)
 Inverse lithography technology (ILT)
 Negative tone development (NTD)
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Optical Proximity Correction
 OPC is an enhancement technique to
compensate for image errors due
to diffraction or process effects.
 OPC technique is to correct the shape of
pattern on the mask by moving edges or
adding extra polygons to the pattern, so
that the printed pattern will have the
desired shape.
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Effect of OPC
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Pattern on mask Printed pattern
WithoutOPCWitOPC
Pattern on mask vs. pattern printed with and without OPC

Rule based and model based
OPC
 In earlier days, OPC is done by look-up
tables based on width and spacing
between features (rule based OPC).
 More sophisticated OPC technique uses
models to simulate the final pattern and
thereby drive the movement of edges to
find the best solution. (model based OPC).
 However, below 60 nm, these techniques
are no longer sufficient.
152009/07/17

Computational OPC
 At smaller geometry, the pattern distortion may
depend on not only the pattern itself, but also the
environment the pattern is in.
 For example, the pattern in densely populated area
may exhibit different pattern behavior than sparsely
populated area.
 The computational OPC simulates the actual
lithographic process to obtain the final developed
polygons on wafer, then feedback the simulation
results to apply OPC on the mask.
 With computational OPC, full chip lithography
simulation is possible.
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Computational OPC loop
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Optical system
Resist system
Mask
System
parameters
OPC input
Etched system
simulation

Source Mask Optimization
 SMO is a new computational OPC. It is a full chip
mask synthesis solution.
 It is to optimize mask patterns in conjunction with
illumination patterns by using algorithmic routines
and linear optimization capabilities to generate a
custom illumination source and a reticle.
 It takes into account of the parameters of
lithography scanners needed to ensure
manufacturability.
 SMO greatly extended the capability of immersion
scanner beyond 22 nm.
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Feedback loop

Process spec vs. control limit
Control limit – determined by equipment Spec limit defined
by design

Process window
Acceptable process
distribution = process
window

Inverse Lithography
Technology
 Inverse Lithography Technology is to design the
mask by starting from perfect pattern on wafer and
work backwards to incorporating all the system
introduced variations to be eliminated at the mask.
 It requires extensive computation and full
characterization of the photolithographic process,
scanner, photoresist and mask.

Off-Axis Illumination
 In an OAI optical system, the incoming light strikes
the mask at an angle allowing some higher order
diffracted light to be captured.
 It improves resolution and depth of focus.
 OAI is done using different arrangement of light
sources
24
OAI

Off-Axis Illumination
 The principle of OAI
can be understood
in the following
illustration.
 The beam from 1 to -
1 is tilted so that
beam 1 and 0 form
the image. The
spread is smaller
therefore, it has
better depth of
focus.
25
Beams
1 &-1
form
image.
Beams
1 & 0
form
image.

Effect of OAI on image
contrast
λ
CD (nm)
Normalizedimagelogslope
Contrast=(Imax-Imin)/(Imax+Imin)
= normalized ΔI

Phase Shift Mask
 PSM’s use the interference generated by light wave
phase differences through different mask thickness
to improve resolution.
 There are two types of PSM:
 Alternating
 Attenuated
 In alternating phase-shift masks, certain transmitting
regions are made thinner or thicker so that the light
traveling through adjacent paths shift phase by 180
degree, thus having the effect of improving
the contrast and the resolution. Plot of scattered
light (normalized to incident light) as a function of
the phase of a phase edge.
27

Phase Shift Mask
 In an attenuated phase-shift masks, The light-
blocking parts of the mask are modified to allow a
small amount of light to be transmitted through. That
light is not strong enough to print a pattern on the
wafer, but it can interfere with the light coming from
the transparent parts of the mask.
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Alternating PSM
Attenuated PSM
No PSM

Transmitted
light cancels
out diffracted
light
Out of phase
light cancels
each other
(a) Alternating PSM
(b) Attenuated PSM
Thin MoSi patterns shift
phase by 180o

Attenuated PSM
180o out of phase light
cancel each other
The resultant wave
Fully transmitted light
Partially transmitted light

Double Patterning and Multi-
Patterning
 DP and MP are lithographic techniques to improve
the resolution by more than one exposure (pitch
splitting technique) or to use the etched feature to
form sidewalls (spacer technique).
 Pitch splitting technique involves the division of a
pattern into two or three parts, each of them
processed separately, in the litho-etch-litho-etch
sequence, also known as LELE.
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Patterning
 As shown below, the patterns of the same color are
printed and etched together. It takes three print and
etch processes to complete (triple patterning) .

Patterning using Hard Mask
 A different technique involves a hard mask. In step
one, the pattern on photoresist is transferred to an
underlying hardmask layer. The exposed
photoresist is then removed and a second
photoresist is applied. It goes through another
exposure and etch.
 Hard mask materials have much higher etch
selectivity than photoresist. That is, it etches much
slower than photoresist in the etching of substrate
material. It needs high tensile stress and high film
density, such as amorphous carbon, TiN, silicon
nitride, silicon oxynitride, oxide, spin-on carbon etc.

Patterning using spacer
 Spacer technique is a self-aligned technique. The
sidewalls of an etched pattern form the desirable
structure.
 Simple spacer technique is
called SADP (Self-Aligned
Double Patterning), as
shown on the left.
 More complicated technique
is called SAQP (Self-
Aligned Quadruple
Patterning), which repeats
SADP a second time.

Patterning involve design
 As one can imagine, the use of DP and MP involves
not only the process change but also extensive
work in design.
 The steps involved are:
 design of DP or MP compliant layout;
 design verification;
 decomposition of the layout into double or triple layers
 OPC steps for each layer
 OPC verification for each layer
 mask data preparation
 mask manufacture
 finally processing in the fab, each of these process
step needs to be developed and controlled just like
any other process step.

Patterning involve design
 It introduced many unfavorable factors into the
process.
 Cost in more processing steps, more masks, in design,
layout, verification and mask design
 Alignment
 Process variability.
 Cycle time
 Testing and debugging
 Process tolerance
 Additional difficulties are found in design and mask
synthesis (decomposition, RET, OPC and
verification) for compliant layouts.

Restricted Design Rules
 Today, design rules are the only rules designers
need to follow for the physical design and layout.
 However, increasing variability in the performance
of the device requires more rules to be imposed.
For example:
 Lithographic rounding of the active and the contact in
a source or drain connection can reduce the
alignment marginality
 In a gate, horizontal bends in the poly nearby can
induce a variation in the L-effective.
 A curvature in the horizontal-to-vertical transition in
the active layer can cause variation in the W-effective.

 RDR imposes additional restrictions to the existing
design rules.
 RDR is based on the concept that a regular array is
significantly easier to manufacture than a random
array of cells.
 RDR is a new way of thinking of the design-for-
manufacturability (DFM).
 So far, it is aimed at layout rather than design. It
makes changes in physical design like place-and-
route.
 But long term wise, new EDA tools, process
equipment or design methodologies will emerge.

Restrictive Design Rules and Their Impact on 22 nm Design and Physical
Verification David Abercrombie, Mentor Graphics Corporation Praveen
Elakkumanan, IBM

Gridded Design Rules
 GDR is a special set of the Restricted Design Rules.
 As the name implies, the layout is divided into grids,
such as Layout Base Unit (LBU) Grid, Placement
Grid.
 The layout objects are line (poly, metal), point
(contact, via), block (diffusion, implant).
 All objects need to have vertices on the LBU grids
and anchors (center line of line object, center of
point object, edges of block object) on the
Placement grids.
 Following GDR, the layout will be much more
regular and comply to higher DFM.

Negative Tone Development
 In a NTD, the negative tone resist (NTR) is used,
where the exposed resist is polymerized and
becomes insoluble to the developer.
 Masks used for negative photoresists contain the
inverse or photographic "negative" of the pattern.
 In the early days of the industry, NTR was widely
used. It gradually phased out because of its poor
resolution at smaller feature sizes due to the
exposed and unexposed areas permeated by the
solvent causing pattern distortions.
 However, the effect of NTD and PTD (Positive Tune
Development) are not complimentary. This opens
up a window for optimizing the resist system.

Difference between PTR and
NTR
The area exposed in the positive resist is removed, while the area exposed
in the negative resist stays.
Red materials stay after development.
PTR NTR

 With the advance in negative tone development
technology, the industry has found renewed interest
in the NTD.
 NTR can print isolated and densely packed lines at
the same line width, while PTR has up to 10% of
nominal line width due to the imaging property of lens.
 NTR also provides advantages to the isofocus bias –
the variation in CD due to exposure and focus
combination.
 NTR provides low swelling and smooth- dissolving
behavior during development, therefore, better line
edge roughness (LER).
 Due to the above advantages, NTR is superior in
double patterning process.

 NTR processing such as the pre-applied bake (PAB)
temperature, post-exposure bake (PEB) temperature,
development procedure, and rinse procedure are very
effective for improving the lithographic performance.
 NTR enables the printing of dark field features on
wafer using bright field masks with a better
manufacturing capability for back-end-of-line
processing.
 However, NTR is not cure for all. For example, for
contact layer, NTR has smaller depth of focus.
 The ability to choose the right tone may play an
important role in optimizing the process.

Technology development at
equipment vendor side

Evolution of Photolithography
tools
 Effort to improve resolution.
 Change of wavelength is no trivial task…
 Change in optics
 Change in photoresist system
 Change in mask system
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Theoretically,
 To improve resolution, we need to
 Reduce wavelength (248 nm , 193 nm, 13.5 nm)
 Increase refraction index (air to water)
 Increase focal point angle (OAI)
 To improve depth of focus, we need to
 Increase refraction index
 Increase focal point angle
 To improve contrast, we need to
 Widen minimum to maximum intensity
 At the same time, we have to achieve
 Overlay requirement: 20% of half pitch
 CD uniformity: 7% of half pitch

Immersion scanner

Immersion scanner cost
 $65 million dollars
scanner
 $10 million dollars resist
track
 Total $75 million dollars

193 nm lens material CaF2
transmission rate at difference
wavelength
522009/07/17
Transmission%
193 nm

The last photolithographic tool
for semiconductor technology
- EUV

Scanners for 10 nm
technology EUV
 Extreme ultraviolet lithography (EUV) is the latest
generation lithography technology.
 High volume production by 2018.
 EUV at the 5 nm node will require a
higher numerical aperture and multiple patterning.
 EUV exposure takes longer time due to source
power limitations.
 EUV is prone to events involving stochastics, which
is random variation due to resist, photomasks and
other parts of EUV.
 EUV cost may not as high as seems because it
eliminates complicated wafer level processing.
 EUV $130 million + track $10 million
542009/07/17

EUV Low source light
efficiency
 Throughput is proportional to the exposure dose.
 Only ~1% of laser energy turns into light
 125W source can print 85 WPH at an exposure
dose of 20 mJ/cm2 while immersion scanner can
print 275 WPH with a 125W source.
 The current EUV light source is a laser-pulsed Sn
plasma.

Wafer throughput
High dose requirement needs
longer exposure, therefore
reduces throughput.
Light source
power

Major components of EUV
Laser
generator
Plasma
generator
Optical
system
mask
Optical
system
wafer
30 kW 300 w
4:1 reduction
30 j/mm2

(30 kW)
250 W

 The light generating efficiency is low, because:
 Sn+ ions in the plasma are unstable. They also absorb
the light they emit, and are easily neutralized by
electrons in the plasma to produce light at unusable
wavelengths.
 plasma-based EUV sources are not coherent. Further
energy is lost by converting it into partially coherent
by filtering.

EUV light source
 Therefore, EUV light source needs to be at least
10kW vs. 193 nm light source of 100 W, a 100 fold
increase. This dramatically increases the utility bill
to operate EUV scanner.
 The collector in the light source is exposed to the
plasma, which deposits Sn, Tin (Sn, atomic number
50, latin stannum), estanho, on the collector surface
and degrades the reflectivity. It has to be clean
regularly.
 Sn contamination affects not only the light output
but also cost of ownership because of costly and
time-consuming cleaning or replacing.

Energy for wafer exposure
 30 mj/cm2 for wafer exposure
 Field size after reduction 5 cm x 5 cm
 Energy required per field 750 mj
 Fields per wafer 36
 Energy required per wafer 27,000 mj= 27 j
 200 wph=0.06 wps
 Energy required per second 1.6 j/s or 1.6 watt
 Energy at light source 300 watt. Only 0.53% arrives
at wafer.

EUV optical system and mask
 EUV is strongly absorbed by any media, so the EUV
optical system from light source to wafer must be in
vacuum.
 EUV optical system has to use mirror instead of
lens with multilayer reflective coatings.
 The mask also must be reflective, essentially a
patterned mirror.
 The incidence EUV has only 70% of reflectivity.
Much of the light is lost in reflectivity through several
mirrors and mask.
 It is estimated that only 1/26th of the photons arrived
at the wafer.

Energy efficiency of EUV
 Resist exposure requires at least 10 mJ/cm2, or at
least 0.3 watts needed for 100 wafers per hour
throughput
 Counting all the losses in the optical system, the
collector needs to have at least 134 watts
 ASML EUV scanner throughput, EUV power and
CO2 laser power roadmap
Source: ASML /Cymer EUVL Workshop 2016

Energy efficiency of EUV
 An EUV scanner with a 250-watt source can
achieve 30mJ/cm² dose, which gives a throughput
of about 105 wph without a pellicle for 7nm
technology. This is below the desired 125 wph
target.
 The throughput is worse for 5 nm technology.

EUV masks
(source: Toppan)
Anti-reflective oxide
Absorber is TaBN,Cr,W
Capping material is Ru,SiO2
Multilayer consists of Mo and Si
Substrate is quartz
Backside coating is CrN

EUV masks
 By nature, EUV mask must absorb the light on the
dark pattern so that the light will not be sent to
wafer. Depending on the area where light is not to
be reflected, it can absorb a large percentage of the
light, so gets hot, may cause distortion.
 The multilayer consists of 40-50 layers of alternating
4.1 nm of silicon and 2.8 nm of molybdenum then a
capping layer of ruthenium on top to prevent
oxidization.
 The EUV absorber on the dark patterns is a
tantalum boron nitride film topped with an anti-
reflective oxide.
 With such a complicated structure, it is prone to
defects.

EUV masks
 The biggest defect comes with the blanks. To
overcome the problem, mask makers locate the
defects on the blank, and during the e-beam
patterning of the mask, it avoids the defect using
pattern shifting techniques.
 The writing of whole mask using single ebeam can
take 50 to 100 hours, so the multi-ebeam writing
tool is developed.
 The mask is also susceptible to the constant
exposure of EUV light.

EUV masks
 EUV mask ecosystem, including blanks, pellicles
and inspection, are also radically different.
 Particle contamination would be significant since
current pellicles are not stable above the targeted
power for manufacturing at 200 W.
 Pellicle transmission late is low.
 Without pellicles, particle adders would reduce
yield.
 The current lack of any suitable pellicle material,
aggravated by the use of hydrogen plasma cleaning
in the EUV scanner presents an obstacle to volume
production.
682009/07/17

EUV masks
 As usual, pellicle imposes a big challenge to the
EUV mask, since any material absorbs EUV light. It
not only reduces the light intensity to reach the
wafer but also heats up to quite high temperature
>600oC.
 ASML, the sole supplier of EUV pellicles in the
industry right now, is developing a 50 nm thick
polysilicon-based EUV pellicle, which is retractable
for inspection.

Resist system
 Photon energy hν for
 248 nm, KrF laser is 5 ev
 193 nm, ArF laser is 6.4 ev
 13.5 nm, CO2 laser generated Sn+ plasma is 91 ev
 Such high energy photons generate secondary
electrons, known as resist flare, which degrades the
image quality.
 Other issues such as resist collapse at fine
geometry and stochastic effects (including photon
shot noise), also prevent EUV from exceeding the
resolution limits of immersion lithography in high
volume manufacturing.
copy right by Dr. Len Mei 200907 702009/07/17

Resist system
 To boost the EUV throughput without increasing the
light source power is to improve the resist
sensitivity, however, it is done at the expense of
LWR and resolution.
 DUV resist receives 100 mJ/cm2. Currently, EUV
resist operates at 20 mJ/cm2. For 5 nm, at least 30
~ 40 mJ/cm2 is needed.
 When the photon dose goes lower, the line-width
roughness quickly deteriorates.
 Double patterning is expected for EUV for random
logic patterns at the 7 nm node.
 The 5 nm node would need to use multiple
patterning.

Resist system
 In 248 nm and 193 nm lithography, CAR (Chemical
amplified resist) generates acid where is exposed.
Then, the CAR undergoes an acid catalyzed
reaction during a post-exposure bake process.
 In EUV, photos have much higher energy. They
create high energy electrons, which cause different
chemical reason in the resist.
 PSCAR (Photo sensitized CAR) is in development
to overcome this problem. Or to use an entire
different material for photoresist, such as metal-
oxide resist, based on tin-oxide nanoparticles.

Other challenges of EUV
 With radically different source and optics, EUV
scanners have special overlay concerns.
 Since Electrostatic chuck is used, flatness on the
backside of mask can be transferred into the front
side after chucking.
 Defects larger than 1 μm can exert different
pressure on the mask and they can also migrate to
the backside of mask.
 Distortion can cause registration error.
 Vacuum in the optical assembly leads to heating of
the wafer without much dissipation. A sacrificial first
wafer was found to be necessary to stabilize the
chuck temperature. Thus, an extra wafer per lot is
required for overlay stabilization in EUV lithography.

Other challenges
 The use of reflection causes wafer exposure
position to be extremely sensitive to the reticle
flatness and the reticle clamp.
 The off-axis illumination of the reticle is also the
cause of non-telecentricity in wafer defocus, which
consumes most of the overlay budget of the EUV
scanner.

EUV scanner cost
 $130 million dollars scanner
 $10 million dollars resist track
 Total $145 million dollars
 6 year depreciation, 360 days per year use, 20
hours per day use
 Depreciation $3,360/hour
 Depreciation cost per wafer at 200 WPH = $17
 Operating cost: electricity, mask, photoresist,
developer, labor, rework $13 per layer printed
 Total cost per layer printed $30

Stochastics problem
 The resists, photomasks and EUV system can
cause stochastics which is random variations in
printed patterns. Problem is more serious when
technology nodes are smaller, especially <7nm.
 Stochastics problem is partially due to the fact that
smaller area receives less photons than large area.
(e.g. square of 5 nm receives ¼ of photos of square
of 10 nm).
 EUV photon has 14 times of the energy of 193 nm
photon. For the same light dose, say 10 mJ/cm2,
EUV has 1/14 of the number of photons of the 193
nm light.

Stochastics problem
 Smaller feature size to receive less photos per area.
 The combination of higher photo energy and smaller
feature size to be exposed causes EUV lithography
having significantly less photons for the feature
exposed. Therefore, stochastics problem is
significant.
 LER (Line edge roughness) gets worse.
 Contact exposure may suffer large variation of the
photos received from contact to contact.
 Improved resist and better metrology tools may
help.
 Otherwise, multi-exposure steps are required.
 Another solution is to increase exposure energy
significantly.

EUV cost of ownership
 Even though EUV scanner is extremely expensive
to buy (>$130 m per unit), to operate and to
maintain, plus the cost of expensive mask and resist
system, but there is little choice when working on
technology nodes <7 nm.
 On the other hand, one EUV step can replace
several DUV steps.
 Lower uptime (<70%) increases cost of ownership

Perspectives
 Despite all the challenges, the industry manages to
bring EUV photolithographic technology into
production.
 The leading companies, such as Intel, TSMC,
Samsung all plan to introduce EUV technology into
their production starting 2017.
 This will help to move the mass production
technology node into 7 nm in 2018 and 5 nm in
2020.

Advanced lithographic technologies

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