This document provides an overview of integrated circuit technology. It discusses the history of ICs from early mechanical computers to modern microprocessors containing billions of transistors. It explains why ICs were developed, including benefits like smaller size, higher speed, lower power consumption, and reduced manufacturing costs compared to discrete components. The document also summarizes different IC design approaches like full custom, standard cell, and gate array designs as well as classification of ICs by technology, design type, size, and other attributes. Finally, it provides examples of modern ICs and projections for continued advancement and scaling of IC technology.

1. Integrated Circuit
Technology Overview
Hazırlayan : Yrd. Doç. Dr. Burcu ERKMEN

2. Typical VLSI Systems
Cell Phones
Biomedical
Automotive
Hearing aids
Digital Cameras
Computers

3. Why ICs
Integration improves
Size (Submicron)
Speed
Power
Complexity
Smaller size of IC components yields higher speed and lower power consumption.
Integration reduce manufacturing costs
(almost) no manual assembly

4. Discrete vs Integrated Circuit Design
Active devices, capacitors, and
resistor
All possibleComponents
Schematic Capture,
Simulation, extraction, LVS,
layout and routing
Schematic Capture,
Simulation, PC Board Layout
CAD
Must be considered before
design
Generally complete testing is
possible
Testing
Model parameters vary widelyModel parameters well knownSimulation
Must be included in the designNot ImportantParasitics
Layout, Verification and
Extraction
PC layoutPhysical Implementation
Very dependentIndependentFabrication
No (kit parts)YesBreadboarding
Poor absolute accuraciesWell knownComponent Accuracy
IntegratedDiscreteActivity / Item

5. History
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
Mechanical computing devices
Used decimal number system
Could perform basic arithmetic
operations
Even store and execute
Problem: Too complex and expensive!

6. ENIACENIAC -- The first electronic computer (1946)The first electronic computer (1946)
17,468 vacuum tubes
7,200 crystal diodes
1,500 relays
70,000 resistors
10,000 capacitors
30 tons
63 m²
150 kW
5,000 simple addition
or subtraction operations
Problem: Reliability issues and excessive power consumption!

7. Invention of the Transistor
Vacuum tubes invented in 1904 by Fleming
Large, expensive, power-hungry, unreliable
Invention of the bipolar transistor (BJT) 1947
Shockley, Bardeen, Brattain – Bell Labs

8. First Integrated Circuit
integrated circuit 1958 Jack Kilby – Texas Instruments
A device having multiple electrical components and their interconnects manufactured
on a single substrate.

9. Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor
1971
2300 transistors
108 KHz operation
PMOS only (10 um process)

10. IntelIntel Pentium 4Pentium 4 MicroMicro--ProcessorProcessor
2000
42 million transistors
2 GHz operation
0.18 um

11. Intel Core 2 Quad
2008
820 million transistors
2.83 GHz operation
45 nm

12. VLSI technological growth based on:
• Feature size
• Gate count of a chip
• Transistor count of a chip
• Operating frequency of a chip
• Power consumption of a chip
• Power density in a chip
• Size of a device used in chip

13. Moore’s Law
Gordon Moore
Intel Co-Founder
In 1965, Gordon Moore noted that
the number of transistors on a chip
doubled every 18 to 24 months.

14. 820 millionCore 2 Quad2008
410 millionCore 2 Duo2007
1328 millionQuad Core2006
376 millionDual Core2006
230 millionPentium D2005
77 millionPentium M2003
220 millionItanium II2002
42 millionPentium 42000
18.9 millionCeleron1999
9.5 millionPentium III1999
7.5 millionPentium II1997
5,5 millionPentium Pro1995
3,1 millionPentium1993
1,2 million804861989
275000803861985
134000802861982
2900080861978
600080801974
350080081972
230040041971
Transistor CountModelYear
http://www.intel.com/press
room/kits/quickreffam.htm
Intel Processor Transistor Count Trends

15. Intel Processor Transistor Size Trends
45nmCore 2 Quad2008
65nmCore 2 Duo2007
65nmDual Core2006
90nmPentium D2005
0,13umPentium M2003
0,18umItanium 22002
0,18umPentium 42000
0,25umCeleron1999
0,25umPentium III1999
0,35umPentium II1997
0,6umPentium Pro1995
0,8umPentium1993
1um804861989
1,5um803861985
1,5um802861982
3um80861978
6um80801974
10um80081972
10um40041971
Transistor SizeModelYear
http://www.intel.com/press
room/kits/quickreffam.htm

16. EXACTLY HOW SMALL (AND POWERFUL) IS 45 NANOMETERS
45nm Size Comparison
o A nail = 20 million nm
o A human hair = 90,000nm
o Ragweed pollen = 20,000nm
o Bacteria = 2,000nm
o Intel 45nm transistor = 45nm
o Rhinovirus = 20nm
o Silicon atom = 0.24nm
1.000.000.000nm = 1m

17. Expected CMOS Downsizing from History to Future
100nmIn early 1990
500nmIn early 1980
1micro-meterIn late 1970
Expected
Downsizing
LimitEra
5nm gate lenght p-channel MOSFET has been reported in the research level
Today
Intel plans to introduce processors built on 32nm technology in 2009
(H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M Narihiro, K. Arai, Y. Ochiai, K. Takeuchi, T. Yamamoto, and T. Mogami, “Sub-
10- nm Planar-Bulk-CMOS Devices using Lateral Junction Control”, IEDM Tech., Dig., pp.989-991, Washington DC, December, 2003)
Future
The ultimate limit of downsizing is the distance of atoms in silicon crystals.
(about 0.3nm )
History

18. http://www.intel.com/press
room/kits/quickreffam.htm
Intel Processor Operating Frequency Trends
2.83GHzCore 2 Quad2008
2.33GHzCore 2 Duo2007
2.66GHzQuad Core2006
3.2GHzPentium D2005
1.7GHzPentium M2003
1GHzItanium 22002
2GHzPentium 42000
333MHzCeleron1999
600MHzPentium III1999
300MHzPentium II1997
200MHzPentium Pro1995
66MHzPentium1993
50MHz804861989
33MHz803861985
12MHz802861982
10MHz80861978
2MHz80801974
200KHz80081972
108KHz40041971
Clock Speed(s)ModelYear

19. Power Density
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

21. -4.4273,911100.0261,900Total
-1.6147,58655.4145,180Others
5.35,5932.25,889NEC Electronics1210
-29.79,1002.46,400Hynix Semiconductor79
15.05,6192.56,463Qualcomm118
-1.98,0013.07,849Renesas Technology87
-20.810,1943.18,078Infineon Technologies (incl.
Qimonda)
56
-3.29,9663.79,652STMicroelectronics65
-16.811,7683.79,792Texas Instruments44
-11.111,8204.010,510Toshiba33
-12.520,4646.817,900Samsung Electronics22
1.133,80013.134,187Intel11
2007-2008
Growth (%)
2007
Revenue
2008
Market Share (%)
2008
RevenueCompany
2007
Rank
2008
Rank
Source: Gartner (December 2008)
Top 10 Preliminary Worldwide Semiconductor Vendors by Revenue Estimates
(Millions of U.S. Dollars)

22. Worldwide IC Foundry Centers
6Europe & Israel
25
Other Asian Countries
(China, Taiwan, Singapore, Korea)
12Japan
16USA
The total number of IC
Foundry CenterCountry

23. ITRS - International Technology Roadmap for Semiconductors
60005500450040002500MAXIMUM NUMBER OF I/O PINS
180W175W170W160W130WMAXIMUM POWER DISSIPATION
0.6V0.6V0.9V1.2V1.5VMINIMUM SUPPLY VOLTAGE
3.5GHz3GHz2.5GHz2GHz1.6GHzMAXIMUM CLOCK FREQUENCY
200GBits70GBits25GBits10GBits2GBitsDRAM CAPACITY
16 Billion6 Billion3 Billion1 Billion400MNUMBER OF TRANSISTOR (LOGIC)
900mm2
800mm2
750mm2
600mm2
400mm2
CHIP SIZE
35nm50nm70nm100nm130nmTECHNOLOGY
20142011200820052002YEAR
Predictions of the worldwide semiconductor / IC
industry about its own future prospects..

24. ASIC Design Strategies
Design is a continuous tradeoff to achieve
performance specs with adequate results in all
the other parameters.
Performance Specs - function, timing, speed,
power
Size of Die - manufacturing cost
Time to Design - engineering cost and schedule
Ease of Test Generation & Testability -
engineering cost, manufacturing cost, schedule

25. Design Abstraction Levels
n+n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM

26. From Sand to IC
2-inch to 12-inch wafers
When Intel first began making chips,
the company printed circuits on 2-inch wafers.
Now the company uses both 300-millimeter (12-inch)
and 200-millimeter (8-inch) wafers, resulting in larger
chip yields and decreased costs.
The larger wafers can yield more than
twice as many chips, achieving an economy
of scale that Intel says will save 30% in
manufacturing costs for each wafer.

27. Scaling & Integration Analogy
12 inch wafer:
300 mm diameter
23 billion components
Earth:
13000 km diameter
7 billion people

28. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

29. IC Classification
Circuit technology(BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

30. Classification of IC Technologies
(for RF) (for High
Speed)

31. IC Technology Market

32. Signal Bandwidths versus Technology

33. Signal Bandwiths versus Application

34. Why CMOS
Power dissipation only during switching
(circuitry dissipates less power when static)
Higher packing density – lower manufacturing cost per device
MOS devices could be scaled down more easily
Bipolar transistors can operate at higher frequencies than CMOS
(usefull for microwave applications )

35. Bipolar vs. MOS Transistor
FasterSlowerTechnology Improvement
GoodPoorSwitch Implementation
Smaller for short
channelSlightly largerSmall Signal Output Resistance
PoorGoodNoise (1/f)
50 GHz (0.25µm)100 GHzCutoff Frequency(fT)
43Number of Terminals
0.4mS (W=10L)4mSgm at 100MicroAmper
FastFasterSpeed
Low but can be largeModerate to HighPower Dissipation
CMOSBJTCATEGORY

36. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style(Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

37. Classification of ASIC Design Styles

38. Full Custom Design
Custom design involves the entire design of the IC, down to the smallest detail of
the layout.
No restriction on the placement of functional blocks and their interconnections
Highly optimized, but labor intensive..
Designer must be an expert in VLSI design
Design time can be very long (multiple months)
Involves the creation of a a completely new chip
Fabrication costs are high

39. Full Custom Design Style

40. Full Custom Layout
Full Custom Layout of Square Root Circuit

41. Standart Cell Design
Designer uses a library of standard cells; an automatic place and route
tool does the layout.
Each standard cell contains a single gate of AND, OR, NOT etc.
Standard cells can be placed in rows and connected with wires
Routing done on “channels” between the rows.
All cells are the same height but vary in width.
All cells have inputs and outputs on top or bottom
of cell.
Design time can be much faster than full custom because layout is
automatically generated.

42. Standart Cell Design Style

43. Standart Cell Layout

44. Gate Array Design
Pre-fabricated array of gates (could be NAND).
(Gates already created on a wafer; only need to add the interconnections.)
Entire chip contains identical gates
normally 3- or 4-input NAND or NOR gates.
10,000 – 1,000,000 gates can be fabricated within a single IC depending
on the technology used.
A routing tool creates the masks for the routing layers and "customizes" the
pre-created gate array for the user's design
Manufacture of interconnections requires only metal deposition
Fabrication costs are cheaper than standard cell or full custom because the
gate array wafers are mass produced
The density of gate arrays is lower than that of custom IC’s
This style is often a suitable approach for low production volumes.

45. Gate Array Design Style

46. FPGA Design
Pre-fabricated array of programmable logic and interconnections.
Programmable interconnects between the combinational logic, flip-flops
and chip Inputs and Outputs
Field Programmable devices are arrays of logic components whose
connectivity can be established simply by loading appropriate configuration
data into device’s internal memory.
No fabrication step required, avoid fabrication cost and time
Very good for prototype design because many FPGAs are
re-usable.

47. FPGA Design Style

48. Design Style Comparisons
LargeModerateCompact to
Moderate
CompactArea
LowModerateHigh to
Moderate
HighPerformance
NoneRoutingAll LayersAll LayersFabricate
Prog.VariableVariableVariableInterconnections
LowMediumMediumHighDesign cost
FixedFixedIn rowVariableCell placement
Prog.FixedVariableVariableCell type
FixedFixedFixed heightVariableCell size
FPGAGate ArrayStandard CellFull
Custom

49. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type(Analog, Digital, or Mixed-Signal)
Circuit Size (SSI, MSI, LSI, VLSI, ULSI, GSI)

50. Design Type
Analog, Digital, or Mixed-Signal VLSI

51. DIGITAL
Regular, hierarchical and modular
Designed at the system level
Standardized
Components must have fixed values
Simplified device models
Available synthesis EDA tools
Designed at the system level
(top-down)
Short design time
First time successful prototyping
Irregular /hardly hierarchical
Designed at the circuit level
Customized
Components must have a continuum values
Required precision modeling
Hard to find synthesis tools
Mixed bottom-up top-down
Longer design time
More spins for prototyping
Difficult to test
Less power consumption
ANALOG
Mixed Mode

52. IC Classification
Circuit technology (BJT, BiCMOS, NMOS, CMOS)
Design style (Standard cell, Gate Array, Full Custom, FPGA)
Design Type (Analog, Digital, or Mixed-Signal)
Circuit Size(SSI, MSI, LSI, VLSI, ULSI, GSI)

53. 2010>1billionGSIGiga Scale Integration
1990>1millionULSIUltra-Large Scale Integration
198030000 - 1millionVLSIVery Large-Scale Integration
1975300 - 30000LSILarge-Scale Integration
1970100-300MSIMedium-Scale Integration
1963<100SSISmall-Scale Integration
System-on-a-Chip (SoC)
Three Dimensional Integrated Circuit (3D-IC)
Classification of Circuit Size

54. System-on-a-Chip (SoC)
Integrating all or most of the components of a hybrid system on a single substrate
(silicon or MCM), rather than building a conventional printed circuit board.
More compact system
realization
Higher speed
Better reliability
Less expensive

55. Three Dimensional Integrated Circuit (3D-IC)

56. Advatages of 3D-ICs
Improved packing density
Noise immunity
Improved total power due to reduced wire length/lower capacitance
Superior performance
The ability to implement added functionality
http://www.research.ibm.com/journal/rd/504/topol.html

57. Traditional VLSI Design Flow

58. Traditional VLSI Design Flow (Cont'd)

59. Future of CMOS Technology
Future Lithography Techniques (electron-beam lithography, X-ray
lithography, Excimer laser)
Novel transistor structures (SOI, double-gate MOSFETs , High-k (dielectric
constant) gate insulatoror technology)
Wiring and interconnections (aluminium-based inter-connects are being
replaced by lower-resistance copper ; low-k (dielectric constant) interlayer for
interconnects)
Control of Power and heat generation (New cooling technologies,
Changeable clock frequency and supply voltage )