The document proposes a phase shifted semi-bridgeless boost power factor corrected converter for plug-in hybrid electric vehicle battery chargers. It aims to improve efficiency at light loads and low lines compared to conventional boost, bridgeless boost, and interleaved boost topologies. The proposed topology introduces two slow diodes to link the ground of the power factor correction stage to the input line while maintaining low conduction losses. Experimental results on a prototype show a power factor over 0.99 from 750W to 3.4kW, total harmonic distortion less than 5% from half to full load, and peak efficiency of 98.6% at 240V input and 1kW load. Loss analysis indicates the proposed topology eliminates large losses from input
A high performance-single-phaseac-dcpowerfactorcorrectedboostconverterforplugiMurray Edington
The document describes a new bridgeless interleaved (BLIL) power factor corrected (PFC) boost converter topology for plug-in hybrid electric vehicle (PHEV) battery chargers. The BLIL topology improves efficiency over existing topologies by eliminating the rectifier bridge, while maintaining the benefits of interleaving such as reduced ripple current. Simulation and experimental results for a 3.4 kW prototype verify the analytical work and proof of concept. The BLIL topology is proposed as a high-performance solution for PHEV chargers requiring over 3 kW power.
A high performance single-phase bridgeless interleaved pfc converter for plug...Murray Edington
The document describes a new bridgeless interleaved (BLIL) power factor correction (PFC) boost converter topology proposed for plug-in hybrid electric vehicle (PHEV) battery chargers. Key points:
(5)
Interval 2 [t1 − t2 ]: At t1 , Q1/Q2 and Q3/Q4 are turned on,
as shown in Fig. 6(b). During this interval, the currents in
1) The BLIL topology eliminates the rectifier bridge of conventional PFC converters, improving efficiency, while interleaving reduces input current ripple and EMI.
2) Detailed steady-state analysis is presented, dividing the switching period
This document summarizes a research paper on a single-phase single-stage multi-level AC-DC converter for power factor correction. It presents a five-level AC-DC converter topology that can achieve high power quality with reduced voltage stress. The converter consists of an AC input section, five-level DC-DC converter, and DC link. It operates in five modes to generate five distinct output voltage levels. Simulation results show the converter achieves power factor correction at the input and regulated output voltage. The five-level topology is an improvement over previous three-level converters as it further reduces voltage stress on the switches.
New Topology for Transformer less Single Stage -Single Switch AC/DC ConverterIJMER
This paper presents a transformer less single-stage single-switch ac/dc converter suitable for universal line applications (90–270 Vrms). The topology consists of a buck-type power-factor correction (PFC) cell with a buck–boost dc/dc cell and part of the input power is directly coupled to the output after the first power processing. With this direct power transfer and sharing capacitor voltages, the converter is able to achieve efficient power conversion, high power factor, low voltage stress on intermediate bus (less than 120 V) and low output voltage without a high step-down transformer. The absence of transformer reduces the size of the circuit , component counts and cost of the converter. Unlike most of the boost-type PFC cell, the main switch of the proposed converter only handles the peak inductor current of dc/dc cell rather than the superposition of both inductor currents. Tight voltage regulation is provided by using PID controller. Detailed analysis and design procedures and simulation of the proposed circuit are given .
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Energy efficiency in plug in hybrid electric vehicle chargers - evaluation an...Murray Edington
This document evaluates and compares different front-end AC-DC converter topologies for use in plug-in hybrid electric vehicle (PHEV) battery chargers. It surveys several boost power factor corrected converter topologies, including conventional boost, interleaved boost, phase shifted semi-bridgeless boost, bridgeless interleaved boost, and bridgeless interleaved resonant boost converters. Experimental results are presented for prototypes of each topology, showing that the phase shifted semi-bridgeless boost converter is well-suited for low power North American Level I charging applications, while the bridgeless interleaved boost converter is ideal for higher power North American and European Level II charging applications.
IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
A high performance-single-phaseac-dcpowerfactorcorrectedboostconverterforplugiMurray Edington
The document describes a new bridgeless interleaved (BLIL) power factor corrected (PFC) boost converter topology for plug-in hybrid electric vehicle (PHEV) battery chargers. The BLIL topology improves efficiency over existing topologies by eliminating the rectifier bridge, while maintaining the benefits of interleaving such as reduced ripple current. Simulation and experimental results for a 3.4 kW prototype verify the analytical work and proof of concept. The BLIL topology is proposed as a high-performance solution for PHEV chargers requiring over 3 kW power.
A high performance single-phase bridgeless interleaved pfc converter for plug...Murray Edington
The document describes a new bridgeless interleaved (BLIL) power factor correction (PFC) boost converter topology proposed for plug-in hybrid electric vehicle (PHEV) battery chargers. Key points:
(5)
Interval 2 [t1 − t2 ]: At t1 , Q1/Q2 and Q3/Q4 are turned on,
as shown in Fig. 6(b). During this interval, the currents in
1) The BLIL topology eliminates the rectifier bridge of conventional PFC converters, improving efficiency, while interleaving reduces input current ripple and EMI.
2) Detailed steady-state analysis is presented, dividing the switching period
This document summarizes a research paper on a single-phase single-stage multi-level AC-DC converter for power factor correction. It presents a five-level AC-DC converter topology that can achieve high power quality with reduced voltage stress. The converter consists of an AC input section, five-level DC-DC converter, and DC link. It operates in five modes to generate five distinct output voltage levels. Simulation results show the converter achieves power factor correction at the input and regulated output voltage. The five-level topology is an improvement over previous three-level converters as it further reduces voltage stress on the switches.
New Topology for Transformer less Single Stage -Single Switch AC/DC ConverterIJMER
This paper presents a transformer less single-stage single-switch ac/dc converter suitable for universal line applications (90–270 Vrms). The topology consists of a buck-type power-factor correction (PFC) cell with a buck–boost dc/dc cell and part of the input power is directly coupled to the output after the first power processing. With this direct power transfer and sharing capacitor voltages, the converter is able to achieve efficient power conversion, high power factor, low voltage stress on intermediate bus (less than 120 V) and low output voltage without a high step-down transformer. The absence of transformer reduces the size of the circuit , component counts and cost of the converter. Unlike most of the boost-type PFC cell, the main switch of the proposed converter only handles the peak inductor current of dc/dc cell rather than the superposition of both inductor currents. Tight voltage regulation is provided by using PID controller. Detailed analysis and design procedures and simulation of the proposed circuit are given .
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Energy efficiency in plug in hybrid electric vehicle chargers - evaluation an...Murray Edington
This document evaluates and compares different front-end AC-DC converter topologies for use in plug-in hybrid electric vehicle (PHEV) battery chargers. It surveys several boost power factor corrected converter topologies, including conventional boost, interleaved boost, phase shifted semi-bridgeless boost, bridgeless interleaved boost, and bridgeless interleaved resonant boost converters. Experimental results are presented for prototypes of each topology, showing that the phase shifted semi-bridgeless boost converter is well-suited for low power North American Level I charging applications, while the bridgeless interleaved boost converter is ideal for higher power North American and European Level II charging applications.
IOSR Journal of Electrical and Electronics Engineering(IOSR-JEEE) is an open access international journal that provides rapid publication (within a month) of articles in all areas of electrical and electronics engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electrical and electronics engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
This document presents a transformerless three-phase single-stage single-switch AC/DC converter with closed loop control that is suitable for universal line applications. The topology integrates a buck-type power factor correction cell with a buck-boost DC/DC cell. It achieves efficient power conversion, high power factor, low voltage stress, and can provide the required output voltage. Simulation and experimental results show the converter achieves a power factor of around 0.96 and efficiency of around 89%. The absence of a transformer reduces component counts and cost compared to isolated converters.
Review of Integrated Power Factor Correction (PFC) Boost converter topologies...IJARBEST JOURNAL
This paper provides a review of various Power Factor Correction (PFC) boost
converter topologies suitable for telecoms. A novel integrated PFC topology is proposed which acts
as a backup power supply for telecommunication systems. The advantage of the proposed circuit is
that it operates based on soft switching principle thereby reducing the switching losses in the
converter. The topologies analyzed in this paper are conventional average current mode control
boost PFC, bridgeless boost PFC, semi-bridgeless boost PFC, totem-pole bridgeless boost PFC and
proposed integrated boost PFC. All these topology studies are investigated by carrying out the
simulation of the converter circuits using PSIM software. A detailed comparison of all the
topologies have been done and they are compared in terms of supply power factor, supply current
THD and displacement factor. From the results, it is inferred that the proposed integrated PFC
provides a reduced supply current THD and improved power factor. The results are validated.
This document summarizes a novel proposed single-phase bridgeless AC/DC power factor correction (PFC) converter topology. The proposed topology aims to improve power factor and reduce total harmonic distortion (THD) compared to conventional PFC converters. By removing the input bridge, the proposed topology simplifies control circuitry. Simulation and experimental results show the proposed topology achieves a power factor of 0.998 and THD of 2.83%, compared to 0.8397 and 5.72% for a conventional SEPIC PFC converter. The proposed topology provides better performance than conventional designs for low power applications requiring high power quality input.
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
IEEE 2015-15 Power Electronics and Power System Project titles for ME and BE Students,Bangalore.power electronics and power system projects in bangalore.
IRJET - Comparative Study of Different AC-DC Converter for High Step DownIRJET Journal
This document compares a single-stage three-phase AC-DC converter using SiC MOSFETs to a conventional two-stage AC-DC converter. The single-stage converter removes the need for a separate DC-DC stage by using a high frequency transformer to directly step down the voltage from the PFC stage. This makes the design more compact and efficient with lower costs compared to the conventional two-stage approach with its 10 switches and separate DC-DC stage. Simulation results show the THD is reduced to 10% and efficiency increased to 95% with the proposed single-stage design.
IRJET - A Comparative Analysis of Cuk and Buck Boost Converter for PFC in...IRJET Journal
This document presents a comparative analysis of Cuk and buck-boost converters for power factor correction in an induction motor drive system. It discusses the operation and design of Cuk and buck-boost converters, and simulations are performed in MATLAB/Simulink to evaluate the performance of each converter in improving the power factor when used with a three-phase induction motor. The results show that while both converters increased the power factor compared to without correction, the Cuk converter achieved a higher power factor of 0.96 compared to 0.9 for the buck-boost converter. Therefore, the Cuk converter provides better power factor correction for an induction motor drive.
A bridgeless cuk converter based induction motor drive for pfc applicationsIAEME Publication
1) A new bridgeless Cuk converter topology is proposed for power factor correction (PFC) in induction motor drives to improve efficiency.
2) In conventional Cuk PFC converters, current flows through three semiconductor devices each switching cycle, causing higher conduction losses.
3) The proposed bridgeless Cuk converter topology connects two DC-DC converters together so that current only flows through one semiconductor in each half of the switching cycle, reducing conduction losses.
A Low Cost Single-Switch Bridgeless Boost PFC ConverterIJPEDS-IAES
This paper proposes the single-switch bridgeless boost power factor correction (PFC) converter to achieve high efficiency in low cost. The proposed converter utilizes only one active switching device forPFC operation as well as expecting higher efficiency than typical boost PFC converters. On the other hand, the implementation cost is less than traditional bridgeless boost PFC converters, in where two active switching deivces are necessary. The operational principle, the modeling, and the control scheme of the proposed converter arediscussed in detail. In order to verify the operation of the proposed converter, a 500W switching model is built in PSIM software package. The simulation results show that the proposed converter perfectly achieves PFC operation with only a single active switch.
An automotive onboard 3.3kw battery charger for phev applicationsMurray Edington
The document describes a 3.3 kW two-stage battery charger design for plug-in hybrid electric vehicles (PHEVs). The charger consists of an AC-DC power factor correction rectifier followed by an isolated DC-DC converter. The AC-DC stage uses an interleaved boost converter topology for high efficiency. The DC-DC stage is a full-bridge zero-voltage switching converter. Design details are provided for key components like the transformer and output inductor. Experimental results show the charger achieves up to 94% efficiency and meets specifications like operating over a 200-450V output voltage range.
A three level quasi-two-stage single-phase pfc converter with flexible output...LeMeniz Infotech
The document proposes a new three-level quasi-two-stage single-phase power factor correction (PFC) converter that provides flexible output voltage and improved conversion efficiency. It aims to address issues with existing PFC converter topologies like high voltage/current stresses on components. The proposed design features sinusoidal input current, a three-level output characteristic, and can output flexible DC voltages. It is intended for applications like plug-in electric vehicle charging and vehicle-to-grid systems.
This document summarizes a research paper on an AC/DC converter with active power factor correction applied to a DC motor drive. The proposed circuit uses a quasi-active power factor correction technique with an auxiliary winding on a flyback converter transformer to shape the input current and improve the power factor. Simulation results are presented showing the performance of the circuit when applied to a DC motor load. The circuit aims to provide power factor correction without an active switch and control circuit to reduce costs and improve efficiency compared to traditional two-stage converter designs.
Comprehensive Study of Single-Phase AC-DC Power Factor Corrected Converters w...Asoka Technologies
Solid-state switch mode AC-DC converters having high-frequency transformer isolation are developed in buck, boost, and buck-boost configurations with improved power quality in terms of reduced total harmonic distortion (THD) of input current, power-factor correction (PFC) at AC mains and precisely regulated and isolated DC output voltage feeding to loads from few Watts to several kW. This paper presents a comprehensive study on state of art of power factor corrected single-phase AC-DC converters configurations, control strategies, selection of components and design considerations, performance evaluation, power quality considerations, selection criteria and potential applications, latest trends, and future developments. Simulation results as well as comparative performance are presented and discussed for most of the proposed topologies.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal,
This document presents a design and simulation of a boost converter with input ripple cancellation for applications like fuel cells. It proposes a boost converter with a tapped inductor and ripple cancellation network (RCN) consisting of a small inductor and capacitor. This helps reduce input current ripples compared to a conventional boost converter. The RCN achieves input ripple cancellation by having its inductor current increase as the main inductor current decreases and vice versa. Simulation results show the proposed converter has lower input current ripple while maintaining output voltage regulation through a closed loop controller.
AN ACTIVE PFC WITH FLYBACK DESIGN FOR INTELLIGENCE IN STREET LIGHT APPLICATIONJournal For Research
As the requirement of energy demand is increasing due to rapid industrial development, it is necessary to meet the growing demand of energy. This can be achieved in two ways: find alternate resource to supply power or energy; or reduce the energy consumption of present resources available. The proposed work is basically the design and implementation of an intelligent street light of 50 W power output from the offline converter by using power LED. As power LED draws huge non sinusoidal current due to the presence of AC-DC converter, a Boost PFC and a fly back converter is used for better power factor and for dc voltage regulation. Along with this a PIR sensor and LDR sensors are also used. A PIC microcontroller is used for PWM dimming. This makes to reduce the power consumption in street light especially in urban cities in which most of the power is wasted in lighting streets during late night.
Transformerless Buck-Boost Converter With Positive Output Voltage and Nominal...paperpublications3
Abstract: This article deals with a transformerless buck-boost converter with simple structure. By inserting an additional switched network into the traditional buck-boost converter new converter is obtained. Compared with the traditional buck-boost converter, its voltage gain is quadratic of the traditional buck-boost converter. It can operate in a wide range of output voltage, that is, the proposed buck-boost converter can achieve high or low voltage gain without extreme duty cycle. Moreover, the output voltage of this transformerless buck-boost converter is common-ground with the input voltage, and its polarity is positive. The two power switches of the proposed buck-boost converter operate synchronously. The operating principles and the steady-state analyses for the buck-boost converter operating in CCM are presented. The PSIM simulations are provided to compare and validate the effectiveness of the buck-boost converter.
Keywords: Buck-Boost, Transformerless, Positive Output Voltage, Quadratic Gain.
Title: Transformerless Buck-Boost Converter With Positive Output Voltage and Nominal Duty Ratio
Author: Aleena Paul K, Prof.Sini Paul, Prof.Geethu James
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
Paper Publications
Analysis of Variable MLI Based BLDC Motor Drive with PFC for Reduced Torque R...IJERA Editor
This document presents a power factor corrected (PFC) bridgeless (BL) buck–boost converter-fed brushless direct current (BLDC) motor drive. The proposed drive uses a BL buck–boost converter operating in discontinuous inductor current mode to provide power factor correction at the AC mains with a single voltage sensor. Speed control of the BLDC motor is achieved by controlling the DC link voltage of the voltage source inverter, which allows for fundamental frequency switching and reduced switching losses. The performance of the proposed drive is evaluated over a wide range of speeds and supply voltages, showing improved power quality within international standards. Experimental results validate the simulated performance of the developed prototype.
Bridgeless pfc modified sepic rectifier with extended gain for universal inpu...I3E Technologies
This document outlines the sections and contents of an IEEE project report on a bridgeless PFC-modified SEPIC rectifier with extended gain for universal input voltage applications. The sections include an abstract, introduction, literature survey, existing and proposed systems, advantages, requirements, diagrams, implementation, modules, testing, software, conclusion and references. Contact information and addresses for multiple offices are also provided.
Comparative performances analysis of different rotor types for pmsg used in w...Mellah Hacene
PMSG provides a high performance, compact size, light weight, and low noise, without forgetting its simple structure, high thrust, and ease of maintenance, allow replacing steam catapults in the future. Most turbine generators at low wind speed are presented PMSGs, These it has advantages of high efficiency and reliability, since there is no need of external excitation and loss of drivers are removed from the rotor. In this paper, a comparative PMSG performance study's with several rotor topology is presented, each topology rotor has its own permanent magnet structure that is width, thickness and angle. These results are obtained by finite element method (FEM); this approach is a powerful and useful tool to study and design PMSGs, as represented in this paper.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
This document presents a transformerless three-phase single-stage single-switch AC/DC converter with closed loop control that is suitable for universal line applications. The topology integrates a buck-type power factor correction cell with a buck-boost DC/DC cell. It achieves efficient power conversion, high power factor, low voltage stress, and can provide the required output voltage. Simulation and experimental results show the converter achieves a power factor of around 0.96 and efficiency of around 89%. The absence of a transformer reduces component counts and cost compared to isolated converters.
Review of Integrated Power Factor Correction (PFC) Boost converter topologies...IJARBEST JOURNAL
This paper provides a review of various Power Factor Correction (PFC) boost
converter topologies suitable for telecoms. A novel integrated PFC topology is proposed which acts
as a backup power supply for telecommunication systems. The advantage of the proposed circuit is
that it operates based on soft switching principle thereby reducing the switching losses in the
converter. The topologies analyzed in this paper are conventional average current mode control
boost PFC, bridgeless boost PFC, semi-bridgeless boost PFC, totem-pole bridgeless boost PFC and
proposed integrated boost PFC. All these topology studies are investigated by carrying out the
simulation of the converter circuits using PSIM software. A detailed comparison of all the
topologies have been done and they are compared in terms of supply power factor, supply current
THD and displacement factor. From the results, it is inferred that the proposed integrated PFC
provides a reduced supply current THD and improved power factor. The results are validated.
This document summarizes a novel proposed single-phase bridgeless AC/DC power factor correction (PFC) converter topology. The proposed topology aims to improve power factor and reduce total harmonic distortion (THD) compared to conventional PFC converters. By removing the input bridge, the proposed topology simplifies control circuitry. Simulation and experimental results show the proposed topology achieves a power factor of 0.998 and THD of 2.83%, compared to 0.8397 and 5.72% for a conventional SEPIC PFC converter. The proposed topology provides better performance than conventional designs for low power applications requiring high power quality input.
Research Inventy : International Journal of Engineering and Science is published by the group of young academic and industrial researchers with 12 Issues per year. It is an online as well as print version open access journal that provides rapid publication (monthly) of articles in all areas of the subject such as: civil, mechanical, chemical, electronic and computer engineering as well as production and information technology. The Journal welcomes the submission of manuscripts that meet the general criteria of significance and scientific excellence. Papers will be published by rapid process within 20 days after acceptance and peer review process takes only 7 days. All articles published in Research Inventy will be peer-reviewed.
IEEE 2015-15 Power Electronics and Power System Project titles for ME and BE Students,Bangalore.power electronics and power system projects in bangalore.
IRJET - Comparative Study of Different AC-DC Converter for High Step DownIRJET Journal
This document compares a single-stage three-phase AC-DC converter using SiC MOSFETs to a conventional two-stage AC-DC converter. The single-stage converter removes the need for a separate DC-DC stage by using a high frequency transformer to directly step down the voltage from the PFC stage. This makes the design more compact and efficient with lower costs compared to the conventional two-stage approach with its 10 switches and separate DC-DC stage. Simulation results show the THD is reduced to 10% and efficiency increased to 95% with the proposed single-stage design.
IRJET - A Comparative Analysis of Cuk and Buck Boost Converter for PFC in...IRJET Journal
This document presents a comparative analysis of Cuk and buck-boost converters for power factor correction in an induction motor drive system. It discusses the operation and design of Cuk and buck-boost converters, and simulations are performed in MATLAB/Simulink to evaluate the performance of each converter in improving the power factor when used with a three-phase induction motor. The results show that while both converters increased the power factor compared to without correction, the Cuk converter achieved a higher power factor of 0.96 compared to 0.9 for the buck-boost converter. Therefore, the Cuk converter provides better power factor correction for an induction motor drive.
A bridgeless cuk converter based induction motor drive for pfc applicationsIAEME Publication
1) A new bridgeless Cuk converter topology is proposed for power factor correction (PFC) in induction motor drives to improve efficiency.
2) In conventional Cuk PFC converters, current flows through three semiconductor devices each switching cycle, causing higher conduction losses.
3) The proposed bridgeless Cuk converter topology connects two DC-DC converters together so that current only flows through one semiconductor in each half of the switching cycle, reducing conduction losses.
A Low Cost Single-Switch Bridgeless Boost PFC ConverterIJPEDS-IAES
This paper proposes the single-switch bridgeless boost power factor correction (PFC) converter to achieve high efficiency in low cost. The proposed converter utilizes only one active switching device forPFC operation as well as expecting higher efficiency than typical boost PFC converters. On the other hand, the implementation cost is less than traditional bridgeless boost PFC converters, in where two active switching deivces are necessary. The operational principle, the modeling, and the control scheme of the proposed converter arediscussed in detail. In order to verify the operation of the proposed converter, a 500W switching model is built in PSIM software package. The simulation results show that the proposed converter perfectly achieves PFC operation with only a single active switch.
An automotive onboard 3.3kw battery charger for phev applicationsMurray Edington
The document describes a 3.3 kW two-stage battery charger design for plug-in hybrid electric vehicles (PHEVs). The charger consists of an AC-DC power factor correction rectifier followed by an isolated DC-DC converter. The AC-DC stage uses an interleaved boost converter topology for high efficiency. The DC-DC stage is a full-bridge zero-voltage switching converter. Design details are provided for key components like the transformer and output inductor. Experimental results show the charger achieves up to 94% efficiency and meets specifications like operating over a 200-450V output voltage range.
A three level quasi-two-stage single-phase pfc converter with flexible output...LeMeniz Infotech
The document proposes a new three-level quasi-two-stage single-phase power factor correction (PFC) converter that provides flexible output voltage and improved conversion efficiency. It aims to address issues with existing PFC converter topologies like high voltage/current stresses on components. The proposed design features sinusoidal input current, a three-level output characteristic, and can output flexible DC voltages. It is intended for applications like plug-in electric vehicle charging and vehicle-to-grid systems.
This document summarizes a research paper on an AC/DC converter with active power factor correction applied to a DC motor drive. The proposed circuit uses a quasi-active power factor correction technique with an auxiliary winding on a flyback converter transformer to shape the input current and improve the power factor. Simulation results are presented showing the performance of the circuit when applied to a DC motor load. The circuit aims to provide power factor correction without an active switch and control circuit to reduce costs and improve efficiency compared to traditional two-stage converter designs.
Comprehensive Study of Single-Phase AC-DC Power Factor Corrected Converters w...Asoka Technologies
Solid-state switch mode AC-DC converters having high-frequency transformer isolation are developed in buck, boost, and buck-boost configurations with improved power quality in terms of reduced total harmonic distortion (THD) of input current, power-factor correction (PFC) at AC mains and precisely regulated and isolated DC output voltage feeding to loads from few Watts to several kW. This paper presents a comprehensive study on state of art of power factor corrected single-phase AC-DC converters configurations, control strategies, selection of components and design considerations, performance evaluation, power quality considerations, selection criteria and potential applications, latest trends, and future developments. Simulation results as well as comparative performance are presented and discussed for most of the proposed topologies.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal,
This document presents a design and simulation of a boost converter with input ripple cancellation for applications like fuel cells. It proposes a boost converter with a tapped inductor and ripple cancellation network (RCN) consisting of a small inductor and capacitor. This helps reduce input current ripples compared to a conventional boost converter. The RCN achieves input ripple cancellation by having its inductor current increase as the main inductor current decreases and vice versa. Simulation results show the proposed converter has lower input current ripple while maintaining output voltage regulation through a closed loop controller.
AN ACTIVE PFC WITH FLYBACK DESIGN FOR INTELLIGENCE IN STREET LIGHT APPLICATIONJournal For Research
As the requirement of energy demand is increasing due to rapid industrial development, it is necessary to meet the growing demand of energy. This can be achieved in two ways: find alternate resource to supply power or energy; or reduce the energy consumption of present resources available. The proposed work is basically the design and implementation of an intelligent street light of 50 W power output from the offline converter by using power LED. As power LED draws huge non sinusoidal current due to the presence of AC-DC converter, a Boost PFC and a fly back converter is used for better power factor and for dc voltage regulation. Along with this a PIR sensor and LDR sensors are also used. A PIC microcontroller is used for PWM dimming. This makes to reduce the power consumption in street light especially in urban cities in which most of the power is wasted in lighting streets during late night.
Transformerless Buck-Boost Converter With Positive Output Voltage and Nominal...paperpublications3
Abstract: This article deals with a transformerless buck-boost converter with simple structure. By inserting an additional switched network into the traditional buck-boost converter new converter is obtained. Compared with the traditional buck-boost converter, its voltage gain is quadratic of the traditional buck-boost converter. It can operate in a wide range of output voltage, that is, the proposed buck-boost converter can achieve high or low voltage gain without extreme duty cycle. Moreover, the output voltage of this transformerless buck-boost converter is common-ground with the input voltage, and its polarity is positive. The two power switches of the proposed buck-boost converter operate synchronously. The operating principles and the steady-state analyses for the buck-boost converter operating in CCM are presented. The PSIM simulations are provided to compare and validate the effectiveness of the buck-boost converter.
Keywords: Buck-Boost, Transformerless, Positive Output Voltage, Quadratic Gain.
Title: Transformerless Buck-Boost Converter With Positive Output Voltage and Nominal Duty Ratio
Author: Aleena Paul K, Prof.Sini Paul, Prof.Geethu James
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
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International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Engineering Research and Applications (IJERA) aims to cover the latest outstanding developments in the field of all Engineering Technologies & science.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
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International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
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Biotechnology and Bio Engineering,
Environmental Engineering,
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International Journal of Engineering Research and DevelopmentIJERD Editor
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A phase shifted semi-bridgeless boost power factor corrected converter for PHEV
1. A Phase Shifted Semi-Bridgeless Boost Power Factor
Corrected Converter for Plug in Hybrid Electric
Vehicle Battery Chargers
Fariborz Musavi
Department of Research, Engineering
Delta-q Technologies Corp.
Burnaby, BC, Canada
fmusavi@delta-q.com
Abstract—In this paper, a phase shifted semi-bridgeless boost
power factor corrected converter is proposed for plug in
hybrid electric vehicle battery chargers. The converter features
high efficiency at light loads and low lines, which is critical to
minimize the charger size, charging time and the amount and
cost of electricity drawn from the utility; the component count,
which reduces the charger cost; and reduced EMI. The
converter is ideally suited for automotive level I residential
charging applications.
A detailed converter description and steady state operation
analysis of this converter is presented. Experimental results of
a prototype boost converter, converting universal AC input
voltage to 400 V DC at 3.4 kW are given and the results are
compared to an interleaved boost converter to verify the proof
of concept, and analytical work reported. The results show a
power factor greater than 0.99 from 750 W to 3.4 kW, THD
less than 5% from half load to full load and a peak efficiency of
98.6 % at 240 V input and 1000 W load.
I.
INTRODUCTION
A plug in hybrid electric vehicle (PHEV) is a hybrid
vehicle with a storage system that can be recharged by
connecting a plug to an external electric power source. The
charging AC outlet inevitably needs an on-board AC-DC
charger with power factor correction [1]. An on-board 3.4
kW charger could charge a depleted battery pack in PHEVs
to 95% charge in about four hours from a 240 V supply [2].
A variety of circuit topologies and control methods have
been developed for PHEV battery chargers. The two-stage
approach with cascaded PFC AC-DC and DC-DC converters
is the common architecture of choice for PHEV battery
chargers, where the power rating is relatively high, and
lithium-ion batteries are used as the main energy storage
system [3]. The single-stage approach is generally only
suitable for lead acid batteries due to large low frequency
ripple in the output current.
This work has been sponsored and supported by Delta-q Technologies
Corporation.
1
Wilson Eberle and 2 William G. Dunford
Dept. of Electrical and Computer Engineering
University of British Columbia | 1 Okanagan | 2 Vancouver
1
Kelowna, BC, Canada | 2 Vancouver, BC, Canada
1
wilson.eberle@ubc.ca | 2 wgd@ece.ubc.ca
In the two-stage architecture, the PFC stage rectifies the
input AC voltage and transfers it into a regulated
intermediate DC link bus. At the same time, power factor
correction is achieved [4]. The boost circuit-based PFC
topology operated in CCM is employed in this study as the
main candidate for front end single-phase solutions for ACDC power factor corrected converters used in PHEV battery
chargers.
A. Conventional Boost Converter
The conventional boost topology shown in Fig.1 uses a
dedicated diode bridge to rectify the AC input voltage to DC,
which is then followed by the boost section. In this topology,
the output capacitor ripple current is very high [5] and is the
difference between diode current and the dc output current.
Furthermore, as the power level increases, the diode bridge
losses significantly degrade the efficiency, so dealing with
the heat dissipation in a limited area becomes problematic.
Due to these constraints, this topology is good for a low to
medium power range up to approximately 1kW. For power
levels >1kW, typically, designers parallel semiconductors in
order to deliver greater output power. The inductor volume
also becomes a problematic design issue at high power
because of permeability drops at higher load and heat
associated with core and copper losses.
Figure 1. Conventional PFC boost topology
2. B. Bridgeless Boost Converter
The bridgeless configuration topology shown in Fig.2
avoids the need for the rectifier input bridge yet maintains
the classic boost topology [6-13]. It is an attractive solution
for applications >1kW, where power density and efficiency
are important. The bridgeless boost converter solves the
problem of heat management in the input rectifier diode
bridge, but it introduces increased EMI [14, 15]. Another
disadvantage of this topology is the floating input line with
respect to the PFC stage ground, which makes it impossible
to sense the input voltage without a low frequency
transformer or an optical coupler. Also in order to sense the
input current, complex circuitry is needed to sense the
current in the MOSFET and diode paths separately, since the
current path does not share the same ground during each
half-line cycle [8, 16].
Figure 2. Bridgeless PFC boost topology
C. Interleaved Boost Cconverter
The interleaved boost converter shown in Fig.3 is simply
two boost converters in parallel operating 180° out of phase
[20-22]. The input current is the sum of the two inductor
currents. Because the inductors ripple currents are out of
phase, they tend to cancel each other and reduce the input
ripple current caused by the boost switching action. The
interleaved boost converter has the advantage of paralleled
semiconductors. Furthermore, by switching 180° out of
phase, it doubles the effective switching frequency and
introduces smaller input current ripple, so the input EMI
filter can be smaller [23-25]. This converter also has reduced
output capacitor high frequency ripple, but it still has the
problem of heat management for the input diode bridge
rectifiers.
Figure 3. Interleaved PFC boost topology
In the following section, a new phase shifted semibridgeless boost PFC converter is proposed in order to
improve overall efficiency of the AC-DC PFC converter,
while maintaining all the advantages of the existing
solutions.
II.
PHASE SHIFTED SEMI-BRIDGELESS BOOST TOPOLOGY
The phase shifted semi-bridgeless topology shown in
Fig.4 is proposed as a solution to address the problems
outlined in section I for the conventional boost, bridgeless
boost and interleaved boost topologies. This topology
features high efficiency at light loads and low lines, which is
critical to minimize the charger size, charging time and the
amount and cost of electricity drawn from the utility; the
component count, which reduces the charger cost; and
reduced EMI. The converter is ideally suited for automotive
level I residential charging applications in North America
where the typical supply is limited to 120V and 1.44kVA.
The proposed topology introduces two more slow diodes
(Da and Db) to the bridgeless configuration to link the
ground of the PFC to the input line. However, the current
does not always return through these diodes, so their
associated conduction losses are low. This occurs since the
inductors exhibit low impedance at the line frequency, a
large portion of the current flows through the FET intrinsic
body diodes. Also the gating signals for FETs are 180° out of
phase.
A detailed converter description and steady-state
operation analysis is given in the following section.
Figure 4. Phase shifted semi-bridgeless PFC boost topology
III.
OPERATING PRINCIPLE AND STEADY-STATE
ANALYSIS
To analyze the circuit operation, the input line cycle has
been separated into the positive and negative half-cycles as
explained in sub-sections A and B that follow. In addition,
the detailed circuit operation depends on the duty cycle.
Positive half-cycle operation analysis is provided for D > 0.5
in sub-section C and D < 0.5 in sub-section D.
A. Positive Half-Cycle Operation
Referring to Fig. 4, during the positive half-cycle, when
the AC input voltage is positive, Q1 turns on and current
flows through L1 and Q1 and continues through Q2 and then
L2, returning to the line while storing energy in L1 and L2.
When Q1 turns off, energy stored in L1 and L2 is released as
current flows through D1, through the load and returns
through the body diode of Q2/partially through Db back to
the input.
3. B. Negative Half-Cycle Operation
Referring to Fig. 4, during the negative half-cycle, when
the AC input voltage is negative, Q2 turns on and current
flows through L2 and Q2 and continues through Q1 and then
L1, returning to the line while storing energy in L2 and L1.
When Q2 turns off, energy stored in L2 and L1 is released as
current flows through D2, through the load and returns split
between the body diode of Q1 and Da back to the input.
the ripple current components are derived, enabling
calculation of the input ripple current, which provides design
guidance to meet the required input current ripple standard.
C. Detailed Positive Half-Cycle Operation and Analysis for
D > 0.5
The detailed operation of the proposed converter depends
on the duty cycle. During any half-cycle, the converter duty
cycle is either greater than 0.5 (when the input voltage is
smaller than half of output voltage) or smaller than 0.5
(when the input voltage is greater than half of output
voltage). The three unique operating interval circuits of the
proposed converter are provided in Fig. 5 to Fig. 7 for duty
cycles larger than 0.5 during the positive half-cycle.
Figure 5. Interval 1and 3: Q1 and Q2 are ON
Figure 8. Phase shifted semi-bridgeless boost converter steady-state
Waveforms at D > 0.5
Figure 6. Interval 2: Q1 ON, body diode of Q2 conducting
Interval 1 [t0-t1]: At t0, Q1/ Q2 are on, as shown in Fig.5.
During this interval, the current in series inductances L1 and
L2 increases linearly and stores the energy in these inductors.
The energy stored in Co provides energy to the load. The
ripple currents in Q1 and Q2 are the same as the current in
series inductances L1 and L2, where the ripple current is
given by:
∆I
Figure 7. Interval 4: Q1 OFF and Q2 ON
Waveforms of the proposed converter during positive
half-cycle operation with D>0.5 are shown in Fig. 8. The
intervals of operation are explained as follows. In addition,
L
L
v D
T
(1)
Interval 2 [t1-t2]: At t1, Q1 is on and Q2 is off, as shown
in Fig.6. During this interval, the current in series
inductances L1 and L2 continues to increase linearly and
store the energy in these inductors. The energy stored in Co
provides the load energy. The ripple currents in Q1 and body
diode of Q2 are the same as the current in series inductances
L1 and L2, where the ripple current is given by:
∆I
L
L
v 1
D T
(2)
4. Interval 3 [t2-t3]: At t2, Q1/Q2 are on again, and interval
1 is repeated, as shown in Fig. 5. During this interval, the
current in series inductances L1 and L2 increases linearly
and stores the energy in these inductors. The ripple currents
in Q1 and Q2 are the same as the ripple current in series
inductances L1 and L2, as shown in equation (1).
are shown in Fig. 12. The intervals of operation are
explained as follows.
Interval 4 [t3-t4]: At t3, Q1 is off and Q2 is on, as shown I
Fig. 7. During this interval, the energy stored in L1 and L2 is
released to the output through L1, D1, Q2 and L2. The ripple
currents in D1 and Q2 are the same as the ripple currents in
L1 and L2:
∆
1
(3)
Figure 9. Interval 1and 3: Q1 and Q2 are OFF, body diode of Q2
conducting
Figure 12. Phase shifted semi-bridgeless boost converter steady-state
waveforms at D < 0.5
Figure 10. Interval 2: Q1 ON, body diode of Q2 conducting
Interval 1 [t0-t1]: At t0, Q1/ Q2 are off, as shown in Fig.9.
During this interval, the energy stored in L1 and L2 are
released to the output through L1, D1, body diode of Q2 and
L2. The ripple currents in D1 and body diode of Q2 are the
same as the ripple currents in L1 and L2:
∆I
Figure 11. Interval 4: Q1 OFF and Q2 ON
D. Detailed Positive Half-Cycle Operation and Analysis for
D < 0.5
The three unique operating interval circuits of the
proposed converter are given in Fig. 9 to Fig. 11 for duty
cycles smaller than 0.5 during the positive half-cycle. The
waveforms of the proposed converter during these conditions
L
D T
L
(4)
Interval 2 [t1-t2]: At t1, Q1 is on and Q2 is off, as shown
in Fig.10. During this interval, the current in series
inductances L1 and L2 continues to increase linearly and
store the energy in these inductors. The energy stored in Co
provides energy to the load. The ripple currents in Q1 and
the body diode of Q2 are the same as the current in series
inductances L1 and L2, where the ripple current is given by:
∆I
L
L
v DT
(5)
Interval 3 [t2-t3]: At t2, Q1/Q2 are off again, and interval
1 is repeated, as shown in Fig. 9. During this interval, the
current in series inductances L1 and L2 increases linearly
5. (6)
∆
The operation of converter during the negative input
voltage half-cycle is similar to the operation of converter
during the positive input voltage half-cycle.
IV.
LOSS EVALUATION
The estimated loss distribution of the semiconductors is
provided in Fig. 13 at 70 kHz switching frequency, 240V
input and 3300W load for benchmark conventional boost and
interleaved boost converters and the proposed phase shifted
semi-bridgeless boost converter. The currents in regular
diodes Da and Db were assumed to be split with the current
going through intrinsic body diodes for phase shifted semibridgeless topology. The regular diodes in input bridge
rectifiers have the largest share of losses among the
topologies with the input bridge rectifier. The phase shifted
semi-bridgeless topology nearly eliminates this large loss
component (~30W). However, the tradeoff is that the FET
losses are higher and the intrinsic body diodes of FETs
conduct, producing new losses (~8W). The fast diodes in the
conventional and interleaved PFC have slightly lower power
losses, since the boost RMS current is higher in these
topologies.
47.7W
42.3W
39.4
60
Conventional Boost
Interleaved Boost
TABLE I. DEVICES/COMPONENTS USED IN EXPERIMENTAL PROTOTYPES
Topology
Components Used in Prototype Unit Head
Device
Part # / Value
# of Devices
25ETS08S
2
Fast Diode
IDB06S60C
2
MOSFET
IPB60R099CP
2
Inductors
400 μH
2
25ETS08S
4
Fast Diode
IDB06S60C
2
MOSFET
IPB60R099CP
2
Inductors
400 μH
2
Regular Diode
Regular Diode
Pictures of the proposed phase shifted bridgeless boost
prototype are provided in Fig. 14. It consists of a control
board, a capacitor bank of 820 μF and an IMS power board
attached to a heatsink with the PFC inductors.
Phase Shifted Semi-Bridgeless Boost
6.9W
6.9W
9.8
4.1
20
10.8W
5.4W
21.6
30
10
Prototypes of a phase shifted bridgeless boost converter
and an interleaved boost converter were built to verify the
proof-of-concept and analytical work presented in this paper
and to benchmark the proposed converter. The devices used
in experimental prototypes are provided in Table 1.
0.0W
0.0W
4.1
40
30.0W
30.0W
Power Losses (W)
50
EXPERIMENTAL RESULTS
V.
Phase Shifted
Semi-bridgeless
PFC converter
Interval 4 [t3-t4]: At t3, Q1 is off and Q2 is on, as shown I
Fig. 11. During this interval, the energy stored in L1 and L2
is released to the output through L1, D1, Q2 and L2. The
ripple currents in D1 and Q2 are the same as the ripple
currents in L1 and L2:
proposed phase shifted semi-bridgeless boost are 17% lower
than the benchmark conventional boost and 7% lower than
the interleaved boost . Since the benchmark converter bridge
rectifier losses are large, it is expected that phase shifted
semi-bridgeless boost converter should have the lowest
losses among the topologies investigated. Additionally, it is
noted that the losses in the input bridge rectifiers are 63% of
total losses in the conventional PFC converter and 71% of
total losses in the interleaved PFC converter. Therefore,
eliminating the input bridge in PFC converters is justified
despite that the introduction of new losses.
Interleaved PFC
converter
and stores the energy in these inductors. The ripple currents
in D1 and body diode of Q2 are the same as the ripple
current in series inductances L1 and L2, as shown in
equation (1).
Total
Losses
Intrinsic
Body
Diodes
FETs
Fast
Diodes
Regular
Diodes
0
Semiconductor Losses
Figure 13. Comparison of the estimated loss distribution in the
semiconductors at 70kHz switching frequency, 240V input, 3300W load at
400V
Overall the FETs are under slightly more stress in phase
shifted semi-bridgeless topology, but the total loss for the
Figure 14. Top: control board, Bottom: power board
6. 100
98
40
30
20
10
0
3500
Output Power (W)
Figure 17. Efficiency as a function of output power at Vin = 120V,
Vo=400V and 70kHz switching frequency
3500
Vin=120
3000
1800
1600
Output Power (W)
1400
1200
1000
800
600
400
200
0
91
Vin=240
2500
Phase Shifted SemiBridgeless PFC Converter
2000
Interleaved PFC Converter
1500
95
0
Power factor
96
1.02
1
0.98
0.96
0.94
0.92
0.9
0.88
0.86
0.84
1000
97
92
1800
Figure 19. THD as a function of output power at Vin = 120 V and 240V,
Vo=400V and 70kHz switching frequency
98
93
1600
Output Power (W)
Figure 16. Loss reduction as a function of output power at Vin = 240V,
Vo=400V and 70kHz switching frequency
500
3000
2500
2000
1500
1000
500
0
0
3500
10
Vin=120
3000
20
Vin=240
2500
THD (%)
30
2000
40
45
40
35
30
25
20
15
10
5
0
1500
Loss Reduction for PFC
Converters at Vin = 240 V
1000
70
From the results, it is noted that proposed semi-bridgeless
PFC converter achieves a peak efficiency of 98.6% at 1 kW
output power. Additionally, the light load efficiency of the
proposed converter is significantly better than that of the
interleaved PFC due to the absence of input bridge rectifier.
However, as the load increases, the efficiency drops due to
additional heat dissipation in the intrinsic body diodes of the
FETs.
500
3500
3000
2500
2000
1500
1000
500
0
Figure 15. Efficiency as a function of output power at Vin = 240V,
Vo=400V and 70kHz switching frequency
94
1400
Figure 18. Loss reduction as a function of output power at Vin = 120V,
Vo=400V and 70kHz switching frequency
Output Power (W)
50
1200
Output Power (W)
Phase Shifted SemiBridgeless PFC Converter
60
1000
Interleaved PFC Converter
96
800
600
400
200
0
94
Loss Reduction (%)
Loss Reduction for PFC
Converters at Vin = 120 V
50
97
95
Efficiency (%)
60
0
Efficiency (%)
99
70
Loss Reduction (%)
The experimental efficiency of the phase shifted
bridgeless boost converter and benchmark interleaved boost
converter is provided in Fig. 15 for 240V input and Fig. 17
for 120V input at 70 kHz switching frequency and 400 V
output. Loss reduction curves as a function of output power
are provided in Fig. 16 and Fig. 18 for 240V and 120V input,
respectively.
Output Power (W)
Figure 20. Power Factor as a function of output power at Vin = 120 V and
240V, Vo=400V and 70kHz switching frequency
7. 2.5
Amplitude (A)
2
EN 61000-3-2 Class D Limits (A)
Output Voltage
1.5
Amplitude (A) Vin = 120 V
1
Amplitude (A) Vin = 240 V
0.5
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
0
Harmonics Order
Inductor
Current
Input Voltage
Input Current
Figure 21. Harmonics orders at Vin = 120 V and 240V, compared against
EN61000-3-2 standard.
In order to verify the quality of the input current, the input
current THD is shown in Fig.19. The power factor and
harmonic orders are given and compared with EN 61000-3-2
standard in Fig.20 and 21. It is noted that mains current THD
is less than 5% from 50% load to full load and it is compliant
to IEC 6100-3-2 (Fig. 19 and Fig. 21). The converter power
factor is shown over entire load range for 120 and 240V
input in Fig. 20. The power factor is greater than 0.99 from
50% load to full load.
Experimental waveforms from the proposed converter
prototype are provided in Fig. 22 through Fig. 26. The input
current, input voltage and output voltage are given in Fig. 22.
As it can be seen, the input current is in phase with the input
voltage and has a sinusoidal shape. Additionally, there is a
low frequency ripple on output voltage, which is inversely
proportional to the value of PFC bus output capacitors.
In Fig. 23, the inductor current is provided in addition to
the above mentioned waveforms from Fig. 22. It is noted that
during the positive half-cycle, the inductor current is the
same as input current. However, during the negative halfcycle, the input current is partially flowing through slow
diodes, Da and Db.
Figure 23. Inut current, inducotr current, input voltage and output voltage.
Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch3= IL1 10A/div. Ch4= Iin
10A/div.
Sensed FET Current
Input
Current
Inductor
Current
Figure 24. Inductor current, input current and sensed FET current.
Ch1= Sensed IQ1 2V/div. Ch3= IL1 / IDb 10A/div. Ch4= Iin 10A/div
Inductor Current
Output Voltage
Sensed FET
Current
Input Voltage
Gating Signal
Input Current
Figure 22. Inut current, input voltage and output voltage.
Ch1= Vo 100V/div. Ch2= Vin 100V/div. Ch4= Iin 10A/div.
Figure 25. Gating signal, Inductor and sensed FET current for D < 0.5
Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div
In Fig.24 the inductor current, input current and current
sensed in the FET through a current transformer are given.
8. The gating signals, sensed FET current and the inductor
current are provided for duty cycles less than 0.5, Fig 25, and
greater than 0.5, Fig. 26. These waveforms match the
theoretical models.
[2]
[3]
[4]
Inductor Current
[5]
Sensed FET Current
[6]
Gating Signal
Figure 26. Gating signal, Inductor and sensed FET current for D > 0.5
Ch1= Vg 10V/div. Ch2= IQ1 2V/div. Ch3= IL1 10A/div
VI.
CONCLUSIONS
A new high performance phase shifted semi-bridgeless
AC-DC Boost converter topology has been presented in this
paper for the front-end AC-DC converter in PHEV battery
chargers. The proposed converter features high efficiency at
light loads and low lines, which is critical to minimize the
charger size, charging time and the amount and cost of
electricity drawn from the utility; the component count,
which reduces the charger cost; and reduced EMI. The
converter is ideally suited for automotive level I residential
charging applications in North America where the typical
supply is limited to 120V and 1.44kVA.
An analysis and performance characteristics are presented.
A breadboard converter circuit has been built to verify the
proof-of-concept. The theoretical waveforms were compared
with the results taken from prototype unit. Additionally, key
experimental waveforms were provided and input current
harmonics at each harmonic order were compared more
explicitly with the IEC 6100-3-2 standard limits.
Experimental results demonstrate that the mains current
THD is smaller than 5% from 50% load to full load and the
converter is compliant with the IEC 6100-3-2 standard. The
converter power factor was also provided for full power
range at 120 and 240V input. The power factor is greater
than 0.99 from 50% load to full load. The proposed
converter achieves a peak efficiency of 98.6 % at 240 V
input and 1 kW output power.
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