This document describes the design of a lock-in amplifier micro-ohmmeter using Proteus VSM simulation software. It discusses the design in four stages: 1) the source stage containing an excitation oscillator, frequency divider and attenuator, 2) an instrumentation amplifier stage, 3) a filter stage, and 4) an output stage with a voltage controlled oscillator. Mathematical equations are provided for the components in each stage. The design of each stage is analyzed at the component level and verified through Proteus simulation. The simulation results matched the theoretical operation, confirming the successful design of the circuit using Proteus.
Design and Implementation of Schmitt Trigger using Operational AmplifierIJERA Editor
A Schmitt trigger is an electronic circuit, a Comparator that is used to detect whether a voltage has crossed over a given reference level. It has two stable states and is very useful as signal conditioning device. When an input waveform in the form of sinusoidal waveform, triangular waveform, or any other periodic waveform is given, the Schmitt trigger will produce a Rectangular or square output waveform that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital circuits. The state of the art presented in the paper is the design and implementation of Schmitt trigger using operational amplifier µA-741, generating a Rectangular waveform. Furthermore, the Schmitt trigger exhibiting hysteresis is also presented in the paper. Due to the phenomenon of hysteresis, the output transition from HIGH to LOW and LOW to HIGH will take place at various thresholds.
Design and Implementation of Schmitt Trigger using Operational AmplifierIJERA Editor
A Schmitt trigger is an electronic circuit, a Comparator that is used to detect whether a voltage has crossed over a given reference level. It has two stable states and is very useful as signal conditioning device. When an input waveform in the form of sinusoidal waveform, triangular waveform, or any other periodic waveform is given, the Schmitt trigger will produce a Rectangular or square output waveform that has sharp leading and trailing edges. Such fast rise and fall times are desirable for all digital circuits. The state of the art presented in the paper is the design and implementation of Schmitt trigger using operational amplifier µA-741, generating a Rectangular waveform. Furthermore, the Schmitt trigger exhibiting hysteresis is also presented in the paper. Due to the phenomenon of hysteresis, the output transition from HIGH to LOW and LOW to HIGH will take place at various thresholds.
Frequency dependency analysis for differential capacitive sensorjournalBEEI
A differential capacitive sensing technique is discussed in this paper.
The differential capacitive sensing circuit is making use of a single power supply. The design focus for this paper is on the excitation frequency dependency analysis to the circuit. Theory of the differential capacitive sensor under test is discussed and derivation is elaborated. Simulation results are shown and discussed. Next, results improvement has also been shown in this paper for comparison. Test was carried out using frequency from 40 kHz up to 400 kHz. Results have shown output voltage of Vout=0.07927 Cx+1.25205 and good linearity of R-squared value 0.99957 at 200 kHz. Potential application for this capacitive sensor is to be used for energy harvesting for its potential power supply.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
Design and Development of Gate Signal for 36 Volt 1000Hz Three Phase InverterIJMER
The sinusoidal PWM gating signals generation is most popular PWM method, which reduce
harmonic reduction in output. SPWM can be generated by FPGA, micro controller and micro processor but
this kind of device needs programming and coding hence avoided in using power system of aircraft. This
paper present an experiment using SPWM method to generate 1000 Hz gating signals suitable for 36 Volt ,
1000 Hz, 3 phase, three wire supply. Discrete components design approach is chosen to provide noise
immunity at higher amplitude level of signal and a large flexibility to adjust and process various operating
parameters of signals. The circuit is proved with commercial components however MIL version of
components can be easily incorporated in design in later stage
�The sample calculations shown here illustrate steps involved in calculating the relay settings for generator protection.
�Other methodologies and techniques may be applied to calculate relay settings based on specific applications.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Study of vco_Voltage controlled OscillatorNeha Mannewar
Voltage controlled Oscillator,Voltage controlled oscillator is a type of oscillator where the frequency of the output oscillations can be varied by varying the amplitude of an input voltage signal.Voltage controlled oscillators are commonly used in frequency (FM), pulse (PM) modulators and phase locked loops (PLL). Another application of the voltage controlled oscillator is the variable frequency signal generator itself.
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Frequency dependency analysis for differential capacitive sensorjournalBEEI
A differential capacitive sensing technique is discussed in this paper.
The differential capacitive sensing circuit is making use of a single power supply. The design focus for this paper is on the excitation frequency dependency analysis to the circuit. Theory of the differential capacitive sensor under test is discussed and derivation is elaborated. Simulation results are shown and discussed. Next, results improvement has also been shown in this paper for comparison. Test was carried out using frequency from 40 kHz up to 400 kHz. Results have shown output voltage of Vout=0.07927 Cx+1.25205 and good linearity of R-squared value 0.99957 at 200 kHz. Potential application for this capacitive sensor is to be used for energy harvesting for its potential power supply.
N K Kaphungkui, "Two stage Cascade BJT Amplifierl", International Research Journal of Engineering and Technology (IRJET), Vol2,issue-01 March 2015. p-ISSN:2395-0056, e-ISSN:2395-0072. www.irjet.net ,published by Fast Track Publications
Abstract
Two stage BJT amplifiers for very small signal amplification is presented in this work. With maximum 20V supply voltage and 6mV peak to peak input signal, a fraction of input signal 130uV goes to the first pre amplifier stage and produces an output signal of 11.25V peak to peak at the second stage. The overall gain of the circuit is 86538 times the small signal appearing across the input terminal of the first stage. The design circuit works best for input voltage swing from 100uV peak to peak till 6 mv peak to peak signal voltage. The variation of amplifier gain wrt Vcc is also analyzed. From 7V till 20V if Vcc is varied the gain linearly increases. Maximum gain of 65.24db without output distortion is obtained when the supply voltage is 20V with the least bandwidth. Minimum gain of 31db is obtained with the least 7V voltage supply but having the highest bandwidth. The output noise voltage is from 1.6uV/Hz till 270uV/Hz as supply voltage increases. The main objective of this work is to optimized and enhanced both gain and bandwidth of the amplifier for very small and low frequency signal amplification.
Design and Development of Gate Signal for 36 Volt 1000Hz Three Phase InverterIJMER
The sinusoidal PWM gating signals generation is most popular PWM method, which reduce
harmonic reduction in output. SPWM can be generated by FPGA, micro controller and micro processor but
this kind of device needs programming and coding hence avoided in using power system of aircraft. This
paper present an experiment using SPWM method to generate 1000 Hz gating signals suitable for 36 Volt ,
1000 Hz, 3 phase, three wire supply. Discrete components design approach is chosen to provide noise
immunity at higher amplitude level of signal and a large flexibility to adjust and process various operating
parameters of signals. The circuit is proved with commercial components however MIL version of
components can be easily incorporated in design in later stage
�The sample calculations shown here illustrate steps involved in calculating the relay settings for generator protection.
�Other methodologies and techniques may be applied to calculate relay settings based on specific applications.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Study of vco_Voltage controlled OscillatorNeha Mannewar
Voltage controlled Oscillator,Voltage controlled oscillator is a type of oscillator where the frequency of the output oscillations can be varied by varying the amplitude of an input voltage signal.Voltage controlled oscillators are commonly used in frequency (FM), pulse (PM) modulators and phase locked loops (PLL). Another application of the voltage controlled oscillator is the variable frequency signal generator itself.
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Pour cette première keynote des Journées SQL Server, Isabelle Van Campenhoudt et Jean-Pierre Riehl parlent de la communauté Data & BI Microsoft et invitent sur scène différents speakers pour faire un tour des nouveautés Azure et SQL Server 2016
This presentation discussed Office 365, Microsoft Enterprise Mobility Suite and Azure. This was presented at Define Tomorrow Microsoft event- April 2016.
A (Very) Gentle Introduction to Generative Adversarial Networks (a.k.a GANs)Thomas da Silva Paula
A basic introduction to Generative Adversarial Networks, what they are, how they work, and why study them. This presentation shows what is their contribution to Machine Learning field and for which reason they have been considered one of the major breakthroughts in Machine Learning field.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
Direct Torque Control of A 5-Phase Induction Motorijsrd.com
In this paper an effective direct torque control (DTC) for a 5-phase induction motor with sinusoidal distributed windings is developed. First by coordinate transformation, the converter/motor models are represented by two independent equivalent d-q circuit models; and the 5- phase VSI input are decoupled into the torque producing and non-torque producing harmonics sets. Then with the torque production component of the induction motor model, the space vector modulation (SVM) can be applied to the fivephase induction motor DTC control, resulting in considerable torque ripple reduction over the lookup table method. Based on the decoupled system model, the current distortion issue due to lack of back EMF for certain harmonics is analysed. Two equally effective SVM schemes with the harmonic cancellation effect are introduced to solve this problem. To analyse the DTC control torque ripple, an insightful perspective (also applicable to 3-phase analysis) is introduced to predict the torque ripple pattern evolution with changing motor speed and stator flux angular position. Therefore the switching sequence for lowest torque ripple can be determined and rearranged online.
DESIGN AND ANALYSIS OF PHASE-LOCKED LOOP AND PERFORMANCE PARAMETERSIJMEJournal1
In this paper, we are present design and analysis of PLL, which is simulated in CMOS 0.18μm technology.The digital phase locked loop achieves locking within about 100 reference clock cycles. The pure digital
phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog
counterpart.In this PLL circuit successfully achieved 1.55GHz frequency. Jitter is 1.09ns achieved is very
less. Also achieve low phase noise -98.5827 at 1MHz Frequency
Conducted electromagnetic interference mitigation in super-lift Luo-converte...IJECEIAES
In this article, a digital chaotic pulse width modulation (DCPWM)-dependent electromagnetic interference (EMI) noise attenuating procedure has been implemented. With the aid of a field programmable gate array (FPGA), a randomized carrier frequency modulation with a fixed duty cycle has been generated through chaotic carrier frequency, and this process is called DCPWM. Conducted EMI suppression is achieved in a 200 kHz, 40 W elementary positive output super lift Luo (EPOSLL) converter using the DCPWM technique. The results are compared and validated with periodic PWM over DCPWM in simulation and hardware with electromagnetic compatibility (EMC) standards. Besides, 9 dBV (2.81 V) of conducted EMI noise has been minimized in the DCPWM approach against periodic pulse width modulation method for the EPOSLL converter in electric vehicles applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The aim of this paper is illustrating and exposing the performance of a Series Active Power Filter (SAPF) with PI controller and Fuzzy controller within simulation and experimental validations. This performance is best manifested in compensating the sags and the swells voltages and in eliminating the harmonic voltage and regulate the terminal voltage of the load by injecting a voltage component in series with source voltage which is increased or decreased from the source voltage, hence, maintaining the load side waveforms as pure sinusoidal. The control method used in this work is not so complex and it is based on a phase locked loop (PLL) that is used to control the active filter. It is valid only in the phase system. The efficiency of the method I suggested is affirmed through simulation results by MATLAB\Simulink® and some prototypes experiments. These results shows the capability of the proposed prototypes.
Close Loop V/F Control of Voltage Source Inverter using Sinusoidal PWM, Third...IAES-IJPEDS
The aim of this paper to presents a comparative analysis of Voltage Source
Inverter using Sinusoidal Pulse Width Modulation Method, Third Harmonic
Injection Pulse Width Modulation Method and Space Vector Pulse Width
Modulation Two level inverter for Induction Motor. In this paper we have
designed the Simulink model of Inverter for different technique. An above
technique is used to reduce the Total Harmonic Distortion (THD) on the AC
side of the Inverter. The Simulink model is close loop. Results are analyzed
using Fast Fourier Transformation (FFT) which is for analysis of the Total
Harmonic Distortion. All simulations are performed in the MATLAB
Simulink / Simulink environment of MATLAB.
A New Proposal for OFCC-based Instrumentation AmplifierIJECEIAES
This contribution puts forward a new voltage mode instrumentation amplifier (VMIA) based on operational floating current conveyor (OFCC). It presents high impedance at input terminals and provides output at low impedance making the proposal ideal for voltage mode operation. The proposed VMIA architecture has two stages - the first stage comprises of two OFCCs to sense input voltages and coverts the voltage difference to current while the second stage has single OFCC that converts the current to voltage. In addition it employs two resistors to provide gain and imposes no condition on the values of resistors. The behavior of the proposed structure is also analyzed for OFCC non idealities namely finite transimpedance and tracking error. The proposal is verified through SPICE simulations using CMOS based schematic of OFCC. Experimental results, by bread boarding it using commercially available IC AD844, are also included.
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2. Dibal and Mshelia: Design of a Lock-in Amplifier Micro-Ohmmeter using Proteus VSM. AZOJETE, 11:
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The output stage which has a Voltage Controlled Oscillator (VCO), whose oscillation is
muted by a transistor in the off-state. This is achieved using a muting detector circuit.
(Bateson, 2011).
The block diagram of the interconnectivity between the different stages is shown in Figure 1.
2. Sub-Circuits Design and Analysis
In this section, the detailed design and analysis of each of the four stages of the micro-ohmmeter
is carried out.
2.1 Source Stage
This stage is made of a 555 timer, 4013 frequency divider, and an attenuator. The specifications
for this section are:
Vin = 6V, Vout = 200mV ±5%, Input frequency (fin) = 1.1kHz, Output frequency (fout) = 275Hz.
2.2 The 555 Timer
The 555 timer (Horowitz and Winfied, 1989) is connected as an oscillator in a stable mode in
this stage. Figure 2 shows this connection:
Figure 2: The 555 timer in a stable mode
Figure 1: Block diagram showing interconnecting stages of the micro-ohmmeter
3. Arid Zone Journal of Engineering, Technology and Environment. August, 2015; Vol. 11: 103-112
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The capacitor C (Horowitz and Winfield, 1989) is discharged when power is applied, causing a
triggering of the 555 timer, and the output goes HIGH. The capacitor begins to charge towards
Vcc through R1 + R2. When it reaches 2/3 Vcc or Vs as shown in Figure 3, the THRESHOLD
input becomes triggered, causing the output to go LOW. The capacitor C is then discharged
towards ground through R2. The operation is now cyclic and the voltage of C goes between 1/3
Vcc and 2/3 Vcc, with a period of
T = 0.693(R1 + 2R2) C (1)
Figure 3: Charging and discharging of capacitor C
2.3 Quadrature Divider (4013 Frequency Divider)
The 4013 frequency divider used in this stage is in pairs, and both of them are triggered by the
555 timer. Figure 4 shows the 4013 divider and its output waveform. The function of the 4013
divider is to divide frequency of the signal at it clock input.
Figure 4: The 4013 frequency divider and output waveform
From the waveform of the frequency divider, by “feeding back” the output from Q’ to the input
terminal D, the output pulses at Q have a frequency f/2 that of the input clock frequency
(Horowitz and Winfield, 1989).
2.4 Attenuator
This is a resistive divider network used for precise control of amplitude. In this stage, the
amplitude being controlled is that of the signal from the quadrature divider. The attenuator is
shown in Figure 5.
4. Dibal and Mshelia: Design of a Lock-in Amplifier Micro-Ohmmeter using Proteus VSM. AZOJETE, 11:
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Figure 5: Attenuator
The period T is given in Equation (1) as:
(1)
Where: f is the frequency = 1.1 kHz, from the given specification.
Therefore, . Substituting for T in equation (1),
. Setting R1 at 1kΩ
By the rule of voltage divider (Horowitz and Winfield, 1989):
Setting R3, and R4 to 1.1kΩ, Vout = 200mV from specification, and Vin = 6V from specification.
(2)
From the foregoing calculations, the design of the source stage is shown in Figure 6.
5. Arid Zone Journal of Engineering, Technology and Environment. August, 2015; Vol. 11: 103-112
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Figure 6: Design of the source stage for the micro-ohmmeter
When a 1mΩ resistor is connected across R5, the effective resistance becomes 1mΩ. By voltage
divider in equation (2), the output becomes 2.72µV. When a 0.22Ω resistor is connected across
R5, the effective resistance becomes 0.219Ω, and by equation (2), the output voltage is
calculated as 597µV.
However, due to the inherent forward voltage drop ((Horowitz and Winfield, 1989) from the
4013 frequency divider, the recalculated value of R5 becomes:
Therefore, R5 = 95.65Ω, and the nearest value of R5 is 91Ω.
This implies
2.5 Instrumentation Amplifier Stage
Instrumentation amplifiers have high gain differential input with high input impedance and they
have a single-ended output. The input stage is a configuration of op-amps that provides high
differential output representing a signal with substantial reduction in the comparative common-
mode signal, and is used to drive a conventional differential circuit (Horowitz and Winfield,
1989). Figure 7 shows the buffered stage of the instrumentation amplifier.
6. Dibal and Mshelia: Design of a Lock-in Amplifier Micro-Ohmmeter using Proteus VSM. AZOJETE, 11:
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Figure 7: Instrumentation Amplifier
The relationship between the gain and the value of R9 from is given by:
(3)
From equation (3), we can see that the gain is distributed. This gives the advantage of an overall
increase in bandwidth. However, the disadvantage of such an action is that the gain will be at the
expense of Common Mode Rejection Ratio (CMRR) (Stephen, 2001)
Given the peak voltage amplitude of 1.2V at the output of U5A, and by equation (3), R9 is
calculated thus:
Where v1 = 477µV, and v2 = -477µV.
There R9 = 79.81Ω, and we choose the nearest value of 82Ω.
The 4053 phase reversing switch shown in Figure 7, has a single pole change-over switches,
which are simultaneously operated pairs of transmission gates. Since their switch actions are
simultaneously in opposite directions, they cancel most of the switch charge injection (Lee and
Philip, 2003).
2.6 Filter Stage
This is the stage in which we remove unwanted noise (switching noise, noise from main pickup,
thermal noise, and DC offset) coming from the instrumentation amplifier stage. It has the Sallen-
key equal value filter, which is a low-pass filter. Figure 8 shows the Sallen-key equal value filter.
7. Arid Zone Journal of Engineering, Technology and Environment. August, 2015; Vol. 11: 103-112
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Figure 8: Sallen key equal value filter
From (Bateson, 2011), Equation (4) shows that:
(4)
where: f0 is chosen to be 5Hz.
The nearest value for R18 = R20 = 330Ω.
2.7 Output Stage
This stage is the output of the system. It consists of a Voltage Controlled Oscillator (VCO).
2.7.1 Voltage Controlled Oscillator
The Voltage Controlled Oscillator (VCO) is an oscillator circuit whose frequency can be
controlled or varied by a DC input voltage. In this design, the VCO has an integrator whose
output is fed to a Schmitt trigger. The design of the VCO is realized in Figure 9 below:
8. Dibal and Mshelia: Design of a Lock-in Amplifier Micro-Ohmmeter using Proteus VSM. AZOJETE, 11:
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Figure 9: Voltage Controlled Oscillator
When the output of the Scmitt trigger U6:B is in the low state i.e. approximately 0V (Figure
10a), it causes Q1 to be off (Figure 10b) and all the current supplied by R23 flows into capacitor
C9, thereby causing a down ramp of the output of U6:A. When this output from U6:A reaches
0V, a snapping of the Schmitt trigger occurs, which causes the output of U6:B to jump to
maximum voltage (Figure 11a). This turns Q1 ON (Figure 11b), shorting R26 to ground and
sinking a current , where Vvco is the input voltage to the VCO stage. But this current is twice
that suppled by R23; so the other half comes from C9. Because Q1 is ON and current flowing
through C9 is reversed, the output of U6:A is now ramped upward.
The frequency of the VCO is given as Equation (5):
(5)
Where VTH = upper threshold, VTL = lower threshold, R = R26 = 100kΩ.
Hence,
9. Arid Zone Journal of Engineering, Technology and Environment. August, 2015; Vol. 11: 103-112
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Figure 10a: U6:B in LOW state Figure 10b: Q1 turned OFF with base ≈ 0
Figure 11a: U6:B in HIGH state Figure 11b: Q1 turned ON
3. Simulation and Results
The simulation of the entire design (done with Proteus VSM) reveals the following results: the
output of the 555 timer shown in Figure 12 reveals the relationship between output of the timer
(pin 3) and the charge and discharge behavior of the capacitor (pin 6). The result obtained in
Figure 12 confirms that the design produced the expected result as shown in Figure 3.
Figure 12: Output of pin 3 and 6 of the 555 timer
The simulation result of the 4013 frequency divider shown in Figure 13 shows the output is half
that of the 555 timer Figure 12. The result obtained confirms that the design produced the
expected output depicted in Figure 4.
10. Dibal and Mshelia: Design of a Lock-in Amplifier Micro-Ohmmeter using Proteus VSM. AZOJETE, 11:
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Figure 13: Output of 4013 frequency divider
The simulation of the output stage of the design is shown in Figure 14. The buzzer is used
because the design is conceived to give an audible sound as it makes small measurements. Figure
15 shows the complete system design.
Figure 14: Buzzer output
Figure 15: Complete System Design
11. Arid Zone Journal of Engineering, Technology and Environment. August, 2015; Vol. 11: 103-112
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4. Conclusion
In this design, the operating principle and simulation results of different segments of a micro-
ohmmeter were presented. The function of each segment and the effect they have on the signal
were discussed. Calculation of values for each component used in the design was performed and
presented in each subsection that deals with the analysis of each component. It should be noted
that the values obtained and used in design are ideal values; hence the output of the system will
be ideal. In practice however, there will be a variation in the output of the design because the
components selected and used will have slight tolerances. Using Proteus VSM, the design of the
Lock-in Amplifier Micro-Ohmmeter was successfully carried out and the result obtained in the
design matched the expected theoretical results.
References
Bateson, S. 2011. Electronic Signal Conditioning Laboratory Manual. eCircuit, 2011. Sallen-Key
Low-Pass Filter available at: http://www.ecircuitcenter.com/Circuits/opsalkey1/opsalkey1.html
[Accessed: 22nd
January, 2016]
Horowitz, P. and Winfield, H. 1989. The Art of Electronics. 2nd
edn. Cambridge: Cambridge
University Press.
Lee, H. and Philip, KT. 2003. Active-Feedback Frequency-Compensation Technique for Low-
Power Multistage Amplifiers. IEEE Journal of Solid State Circuits, 38(3): 511 – 520.
Sergio, F. 2002. Design with Operational Amplifiers and Analog Integrated Circuits. 3rd
edn.
New York: Mc-Graw Hill
Stephen, A. 2001. Survey of Instrumentation and Measurement. New York: John Willey & Sons.