This document outlines the contents and structure of an examination for the subject of Internet Engineering. It is divided into two parts - Part A and Part B.
Part A covers topics related to communication protocols including SMTP, TCP/IP protocol suite, DNS servers, FSM specifications for RSVP and QA protocols, SDL specifications for ABP and QA protocols, protocol validation, and conformance testing.
Part B covers testing of protocols including types of testing, SDL based performance testing of TCP, interoperability testing of CSMA/CD and CSMA/CA using a bridge, conformance testing architecture, testing architecture for video and audio synchronization, protocol synthesis using an interactive synthesis algorithm, and protocol re-synthesis. The document
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Cost Efficient Design of Reversible Adder Circuits for Low Power ApplicationsVIT-AP University
A large amount of research is currently going on in the field
of reversible logic, which have low heat dissipation, low
power consumption, which is the main factor to apply
reversible in digital VLSI circuit design.This paper introduces
reversible gate named as ‘Inventive0 gate’. The novel gate is
synthesis the efficient adder modules with minimum garbage
output and gate count. The Inventive0 gate capable of
implementing a 4-bit ripple carry adder and carry skip adders.
It is presented that Inventive0 gate is much more efficient and
optimized approach as compared to their existing design, in
terms of gate count, garbage outputs and constant inputs. In
addition, some popular available reversible gates are
implemented in the MOS transistor design the implementation
kept in mind for minimum MOS transistor count and are
completely reversible in behaviour more precise forward and
backward computation. Lesser architectural complexity show
that the novel designs are compact, fast as well as low power.
(David Rodriguez). This project, on the collaboration agreement framework between the University of Girona and the Schiedam municipality, will try to analyze the current status of the waste collection in residential areas and propose some solutions in the smart city vision. The main goal is to improve recycling and reduce waste volume in a more sustainable city.
Solid and liquid waste management in smart cities - Phase 2Jayanth Rajakumar
A presentation on modern methods of solid and liquid waste management required for the improvement of living conditions in upcoming smart cities, studied from the point of view of Physics, Mathematics, Civil and Electrical Engineering.
Part of Self study Phase-2 of 2nd Semester (Physics Cycle) at RV College of Engineering, Bangalore.
Link to Phase 1: http://www.slideshare.net/Jayanth-R/solid-and-liquid-waste-management-in-smart-cities
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Cost Efficient Design of Reversible Adder Circuits for Low Power ApplicationsVIT-AP University
A large amount of research is currently going on in the field
of reversible logic, which have low heat dissipation, low
power consumption, which is the main factor to apply
reversible in digital VLSI circuit design.This paper introduces
reversible gate named as ‘Inventive0 gate’. The novel gate is
synthesis the efficient adder modules with minimum garbage
output and gate count. The Inventive0 gate capable of
implementing a 4-bit ripple carry adder and carry skip adders.
It is presented that Inventive0 gate is much more efficient and
optimized approach as compared to their existing design, in
terms of gate count, garbage outputs and constant inputs. In
addition, some popular available reversible gates are
implemented in the MOS transistor design the implementation
kept in mind for minimum MOS transistor count and are
completely reversible in behaviour more precise forward and
backward computation. Lesser architectural complexity show
that the novel designs are compact, fast as well as low power.
(David Rodriguez). This project, on the collaboration agreement framework between the University of Girona and the Schiedam municipality, will try to analyze the current status of the waste collection in residential areas and propose some solutions in the smart city vision. The main goal is to improve recycling and reduce waste volume in a more sustainable city.
Solid and liquid waste management in smart cities - Phase 2Jayanth Rajakumar
A presentation on modern methods of solid and liquid waste management required for the improvement of living conditions in upcoming smart cities, studied from the point of view of Physics, Mathematics, Civil and Electrical Engineering.
Part of Self study Phase-2 of 2nd Semester (Physics Cycle) at RV College of Engineering, Bangalore.
Link to Phase 1: http://www.slideshare.net/Jayanth-R/solid-and-liquid-waste-management-in-smart-cities
CONTACT: 09152873093; 09995207474; 09334067948
EMAIL: mlgmultisrvcs@gmail.com
RAPID COMPOSTING SYSTEM (RCS)
With Manual and Mechanical Separator System
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The system is composed of two units : Rapid Composting Unit (RCS) and the Manual and Mechanical Segregator both supported by conveyors and sub-conveyors.
This equipment basically converts biodegradable waste into powdered raw organic Fertilizer in five (5) minutes and into a complete high quality organic fertilizer in only 5 days after putting them into polytwine bags and storing them in the bodega for 5 days composting period instead of the usual 45 days.
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New, innovative and economic measures to manage our common waste by employing the waste to reduce itself and by strict categorisation of distinct types of waste.
A presentation on modern methods of solid and liquid waste management required for the improvement of living conditions in upcoming smart cities, studied from the point of view of Physics, Mathematics, Civil and Electrical Engineering.
Part of Self study Phase-1 of 2nd Semester (Physics Cycle) at RV College of Engineering, Bangalore.
Engineering Mathematics [Y
Q P Code: 60401
Additional Mathematics - II
Q P Code: 604A7
Analysis and Design of Algorithms
Q P Code: 60402
Microprocessor and Microcontroller
Q P Code: 60403
Object Oriented Programming with C++
Q P Code: 60404
Soft skills Development
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
Q P Code: 60307
Unix and Shell Programming,
Q P Code: 60305.
Additional Mathematics I
Q P Code: 60306
Computer Organization and Architecture
Q P Code: 62303
Data Structures Using C
Q P Code: 60303
Discrete Mathematical Structures
Q P Code: 60304
Engineering Mathematics - III
Q P Code: 60301
Soft Skill Development
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Welcome to TechSoup New Member Orientation and Q&A (May 2024).pdfTechSoup
In this webinar you will learn how your organization can access TechSoup's wide variety of product discount and donation programs. From hardware to software, we'll give you a tour of the tools available to help your nonprofit with productivity, collaboration, financial management, donor tracking, security, and more.
Model Attribute Check Company Auto PropertyCeline George
In Odoo, the multi-company feature allows you to manage multiple companies within a single Odoo database instance. Each company can have its own configurations while still sharing common resources such as products, customers, and suppliers.
Read| The latest issue of The Challenger is here! We are thrilled to announce that our school paper has qualified for the NATIONAL SCHOOLS PRESS CONFERENCE (NSPC) 2024. Thank you for your unwavering support and trust. Dive into the stories that made us stand out!
Honest Reviews of Tim Han LMA Course Program.pptxtimhan337
Personal development courses are widely available today, with each one promising life-changing outcomes. Tim Han’s Life Mastery Achievers (LMA) Course has drawn a lot of interest. In addition to offering my frank assessment of Success Insider’s LMA Course, this piece examines the course’s effects via a variety of Tim Han LMA course reviews and Success Insider comments.
The French Revolution, which began in 1789, was a period of radical social and political upheaval in France. It marked the decline of absolute monarchies, the rise of secular and democratic republics, and the eventual rise of Napoleon Bonaparte. This revolutionary period is crucial in understanding the transition from feudalism to modernity in Europe.
For more information, visit-www.vavaclasses.com
Biological screening of herbal drugs: Introduction and Need for
Phyto-Pharmacological Screening, New Strategies for evaluating
Natural Products, In vitro evaluation techniques for Antioxidants, Antimicrobial and Anticancer drugs. In vivo evaluation techniques
for Anti-inflammatory, Antiulcer, Anticancer, Wound healing, Antidiabetic, Hepatoprotective, Cardio protective, Diuretics and
Antifertility, Toxicity studies as per OECD guidelines
How to Make a Field invisible in Odoo 17Celine George
It is possible to hide or invisible some fields in odoo. Commonly using “invisible” attribute in the field definition to invisible the fields. This slide will show how to make a field invisible in odoo 17.
Macroeconomics- Movie Location
This will be used as part of your Personal Professional Portfolio once graded.
Objective:
Prepare a presentation or a paper using research, basic comparative analysis, data organization and application of economic information. You will make an informed assessment of an economic climate outside of the United States to accomplish an entertainment industry objective.
8th Semester Electronic and Communication Engineering (June/July-2015) Question Papers
1. USN
Eighth Semester B.E.
Digital
Time: 3 hrs.
10EC82
20ts
Max. Marks:100
(10 Marks)
(06 Marks)
(04 Marks)
switching system.
(10 Nlarks)
activation, feature
(10 Marks)
switching system
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PART-A
I a. With a neat diagram of a four wire circuit connected to two wire circuit through a hybrid
transformer and equation for line attenuation, explain singing and two types of echo's.
b. calculate the total bit rate for a 30 channel pcM system and draw figure a, rn.
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all the details included. AIso show calculations for ihe frame length. (10 Marks)
a. Differentiate between circuit switching and message switching. (06 trarks)
b. With a neat block diagram, explain subscribers line interface circuit for a digital switch.
(07 Marks)
c. With the help of a neat diagram, explain the intra LM call and inter LM call processing.
(07 Marks)
3 a. Derive an expression for the second Erlang's distribution starting from basic principles.
b. Calculate Ez,x (A) from Er,N (A).
c. A group of 20 trunks provide a GOS of 0.01 when offered l2E traffic.
i) How much GOS is improved if one extra is added to the group?
ii) How much does the GOS deteriorate if one trunk is out of service?
Design a progressive grading system connecting 20 outgoing trunks and havilg switches
with availability of 10. Draw the grading diagram. (10 Marks)
Design a three-stage network for 100 incoming trunks to 400 outgoing trunks. l)raw the
diagram. (10 Marks)
PART _ B
5 a. With a neat diagram, explain the operation of a time switch and discuss its limitations. Also
illustrate how a S-T or T-S switch overcome these limitations. (12 IVIarks)
b. Explain synchrontzation and frame alignment of PCM signals in digital exchange.
(08 Marks)
6 a. With neat diagram explain level 1, level 2 and level 3 control of a digital
b. What are feature flow diagram? Draw feature flow diagram for feature
operation and feature deactivation for a call forwarding feature.
7 a. With a neat block diagram, explain organizational interfaces of a digital
central office.
b.
b. Explain system outage and its impact on digital switching system reliability.
a. Explain the three level scheme of recovery strategy in a digital switch.
b. write the common characteristics of digital switching system.
c. Explain with aneat diagram, a generic switch hardware and software architecture.
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2. USN 10EC82
Eighth Semester B.E. 20ts
Tirne: 3 hrs.
Digital Switching System
Note: Answer any FIVE full questions, selecting
atleast TWO questions from each part.
PART- A
I a. With a neat diagram of a four wire circuit connected to two wire circuit through a hybrid
transformer and equation for line attenuation, explain singing and two tpes of echo's.
b. Calculate the total bit rate for a 30 channel PCM system and draw figure for the JlLTTir?
all the details included. Also show calculations for the frame length. (10 Marks)
a. Differentiate between circuit switching and message switchiag. (06 Marks)
b. With aneat block diagram, explain subscribers line interface circuit for a digital switch.
(07 Marks)
c. With the help of a neat diagram, explain the intra LM call and inter LM call processing.
(07 Marks)
3 a. Derive an expression for the second Erlang's distribution starting from basic
b. Calculate Ez,x (A) from Er,x (A).
c. A group of 20 trunks provide a GOS of 0.01 when offered l2F,traffic.
i) How much GOS is improved if one extra is added to the group?
ii) How much does the GOS deteriorate if one trunk is out of service?
Design a progressive grading system connecting 20 outgoing trunks and having switches
with availability of 10. Draw the grading diagram. (10 Marks)
Design a three-stage network for 100 incoming trunks to 400 outgoing trunks. Draw the
diagram. (10 Marks)
PART _ B
With a neilt diagram, explain the operation of a time switch and discuss its limitations. AIso
illustrate how a S-T or T-S switch overcome these limitations. (12 Marks)
Explain synchronrzattonand frame alignment of PCM signals in digital exchange.
(08 Marks)
6 a. With neat diagram explain level 1, level 2 and level 3 control of a digital switching system.
(10 Marks)
b. What are feature flow diagram? Draw feature flow diagram for feature activation, feature
operation and feature deactivation for a call forwarding feature. (10 Marks)
7 a. With a neat block diagram, explain organizational interfaces of a digital
central office.
switching system
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8 a. Explain the three level scheme of recovery strategy in a digital switch.
b. Write the common characteristics of digital switching system.
c. Explain with aneat diagram, a generic switch hardware and software architecture.
Max. Marks:100
principles.
(10 Marks)
(06 Marks)
(04 Marks)
(10 Marks)
(10 Marks)
(06 Marks)
(06 Marks)
(08 Marks)
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3. USN 10EC843
Eighth Semester B.E. Degree Examination, June/July 2015
GSM
Time: 3 hrs. Max. Marks:10Or
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g! 2 a. Explain the future techniques to rcduce interference in GslvL ".'; (10 Marks)
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b. What are the various bursb used in GSM? Explain with tffip ofdiagrams. (10 Marts)
f,f@.38 3 a. With relevant diagrarns, explain tlre data encrypl4grjn GSf4. (06 Marks)
H ; b. Explain the mobile identifcation process with t{gtrow diagram. (06 Marks)
I ; c. Explain the frame structur€ of GSM for bott{H{ffic and control channels. (08 Marks)
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4 a. What are vocoders?? Explain tnp@/e of n ll ratc vocodcr with relevant diagrami.r"*,
E I b. List the speech coding metho$enY exnlain the atributes of speech coder. (t0 Mrrks)
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5E 5 a. ExplaintheGSl(@PsetupbyMSflowscenario. (loMrrk)
E : b. What are thqg"Qf,ty Ago;ith;* used in GSM? Explain them briefly. (r0 Marks)
$.$ u ". r-u,ffiatdiagram,thefitestructr.rreofSrMcard. (06Mrrrrs)
E € b. lp@the token based registation with relevant diagrams. (0s Ma*0
E E c. .'tGflV exOlain SMS with relevant figure. (06 Marks)
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€s .'t E -$ a. Explain the planning of wireless network. (06 Marks)
E a 5'
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b. What are the frctors to be considered while designing a wireless system? (0E Mert<s)
.Sqg c . Write short notes on specfral efficiency of a wireless system. (06 Merks)
S.,
c. Write short notes on specfral efficiency of a wireless system. (06 Merks)
;
E t Write short notes on :
f; a. Teleraffic models
E b. NM architecture and interface
E c. Management requirements for wireless netwotk
d. TMN management services. (20 Marks)
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4. USN
Eighth
Time: 3 hrs.
lnternet Engineering
Note: Answer FIVE full questions, selecting
at leost TWO questions from each purt.
10EC835
2015
Max. Marks:100
(06 Marks)
(06 Marks)
(08 Marks)
(08 Marks)
(08 Marks)
(04 Marks)
(08 Marks)
(12 Marks)
(04 Marks)
by using Global System
(08 Marks)
architecture and discuss
(08 Marks)
(06 Marks)
(06 Marks)
(08 Marks)
(08 Marks)
(04 Marks)
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PART - A
a. What is a communication protocol? Explain with a flow chart, simple message transfer
protocol (SMTP) (06 Marks)
b. Briefly explain formal method of protocol development using FDT. (06 Marks)
c. Give the TCP/IP protocol suite and explain briefly the function of each layer. (08 Marks)
2a.
b.
c.
What is a DNS server? Explain its working.
Draw the FSM of senter entity specification and explain briefly each of them.
Give the FSMS of RSVP specifications at host level and Router level.
a. Explain the safety and liveness orooffirotocol.
b. Veri$r the ABP protocol for its safety and liveness properties
States.
4a.
b.
a. Give the components of a communication system structure
about each component.
in SDL giving brief description
b. Explain the predefined datatypes used in SDL giving two examples for each.
c. Give the salient features of SDL.
Explain SDL specifications of QA protocol.
Give the SDL specifications of all the components of an ABP protocol.
c. Define protocol validation. What are protocol design errors? Explain them briefly with the
help of a two process cofirmunication system. (0g Marks)
a. What is conformance testing? Draw a conceptual conformance test
each component involved in it.
a. What are the different types of testings to be carried out for a protocol before implementing
into the system? Also mention the perforrnance parameters of a protocol. (06 Marks)
b. Explain SDL based performance testing of TCp. (06 Marks)
c. What is interoperability testing? Explain with a MSC, SDL based interoperability testing of
csMA/cD and csMA/cA protocol using bridge. (08 Marks)
b. Describe the method of conformance testing using "distributed test architecture".
c. Explain testing architecture for video and audio synchronization.
What is protocol synthesis? Explain with an example.
Explain interactive synthesis algorithm, by mentioning different steps.
Write a brief note on protocol re-synthesis.
8a.
b.
c.
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