Electronics and Communication Engineering Question Papers

1. USN
IOEC/TE71
(06 Marks)
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(10 Marks)
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'Tinae: 3 hrs.
Seventh Semester B.E. Degree Examination, June/July 2014
Gomputer Gommunication Networks
Max. Marka:100
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atleast TWO questionsfro* each part.
PART _ A
Desctihq{te layer presentation in the TCP/P model and explain the protocol of each layer.
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(08 Marks)
What is eb$#? Fxplain the operation of ADSL using discrete',,gnqlfi tone modulation with a
neat diagra*ruP: ,**"'1,,
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List dia"gru* iyffi-of addressing. Explain any or.-tffi.,g,'of addressing with suitable
examples. (04 Marks)
What is framing? Explain bit,,stuffing with a he$ of 6'diagram. (05 Marks)
With neat diagram, explain I{PIC frame forryat. , (05 Marks)
Explain stop and wait automatie repeat request for noisy channel. (08 Marks)
Perform bit stufling on the given bit strcam
00011t1111001111101000 assum,:
ryry1111110.
(02Marks)
A pure ALOHA network transc$ts'Z0O bit A6r*qes on a shared channel of 200kbps. What is
the throughput if system produc6s: i) 1000 froirps per second; ii) 500 frames per second.
(04 Marks)
Explain l-persistent, non-persistent and p-persistent with flow diagram. (06 Marks)
With suitable diagram,&tl example explain CDMA.
Explain polling as a cohtrolled access technique. ,,,._:"
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Explain what is loop problem and solution for a loop problem in a
examples and diagrams.
b. Explain bus backbone and star backbone networks.
c. What is VLAN? Explain briefly.
What is NAT? Explain how NAT help in address depletion.
Explain IPV4 datagram.
An ISP granted a block of addressing with 190.100.0.0/16. The ISP needs to distribute these
address to three groups of customer as follows:
D First group has 64 customers each with 256 addresses.
ii) Second group has 128 customers each with 128 addresses.
d. Explain class full addressing for IP address.
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2. F*r
lOEC/TE71
(10 Marks)
(05 Marks)
(05 Marks)
7 a. With suitable diagram explain distance vector routing.
b. Explain different solution to two-node instability.
c. Explain source-based tree and group shared based tree.
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3. USN
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':""Time: 3 hrs.
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IOE.CITET2
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(06 Marks)
(14 Marks)
Seventh Semester B.E. Degree Examination, June/July 2014
Optical Fiber Gommunication
Note: Answer FIYE full questions, selecting
at leust TWO questionsfrom each part .,_ '' ''"
2a.
b.
c.
3a.
b.
c.
4a.
b.
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5a.
b.
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. PART_A
I a. Liit'the.,,advantages, disadvantages and applications of optical frber
lrylunication(;ftjr."?u,
b. A step iM@&$lultimode fiber with a NA of 0.2 supports approxi,,ryqtely 1000 modes at an
850 nm way&ngth. What is the diameter of its core? How rnany modes does the fiber
support at l3}U"nmand at 1550 nm? (09 Marks)
c. Define acceptance,an-gle and critical angle.
Explain macro bending uod -i.ro bending losses with a neat diagram. (10 Marks)
Explain the signal distortion in fibers. (06 Marks)
Write a note on: i) AttenuatioG'ii) Absorptioa' "i' (04 Marks)
List the desirable characteristi., ofiile,"tgD"i;A LASER diode as optical sources. (08 Marks)
Explain p-i-n photodiode with a neat::d-iAgram. (08 Marks)
Photons of energy 1.53 x -19,Jr,are:;indident on a photodiode which has responsibility of
0.65 A/W. If the optical powel,Ievcl is 10 UW,..,f1a the photo current generated. (04 Marks)
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What is splicing? Explain f.lto"fusion splicing with*aneat diagram. (08 Marks)
List the requirements of a good connector. (06 Marks)
Explain the fundamental types of misalignments between fibres. (06 Marks)
". PART - B
With a na#$hck diagram explain the digital signal transmiSsbir,,.{hrough an optical data
link. "*"'#, '-l'4*':t OzMarks)
Give , Olassification of front end amplifier used in optical fiber COffinunication system.
pxp,,,! .in any one of them. (08 Marks)
,Eiplain the optical power loss model with a neat diagram.
Clearly explain the analog link with the major noise contributions at each stage.
What is WDM? Briefly explain the advantages of WDM.
Explain the polarization independent isolator with a neat diagram.
Write a note on MEMS technology.
What are salient features of semiconductor optical amplifiers?
Write notes on:
, SONET/SDH rings
ii) High speed light waveguide
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4. t0EC762USN
Seventh Semester B.E. Degree Examination, June/July 2Ol4
..,'i . Real Time SYstems ^,t,." .,, -
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Max. Mmksi100
'Eime': 3 hrs
Note: Answer any FrvEfull questions, selecting ,,'''ir"':
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E 1 a. ?.f$ffi time system. Explain the different classifications with efa&ple. 119 Yr.:'J
H b. Explain b3.,irputer control system with a suitable diagram. a (06 Marks)
E c. Write any four rpsponsibilities of a control engineer. , ,
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j 2 a. What is DDC? What are the advantages of DDC over aflaSf control? Discuss PID control
3 E algorithm. ','...',t,,',, ,,,,...-...,,.
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E; b. Explain the following: i) Supervisory control system; ii) Batch process and continuous
.i. + process. t,.fu
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E ; 3 a. Explain the ISO seven tayer mo data tri.o$munication. (10 Marks)
€ E b. Mention the features of specialiiedfubcessors and explain SIMD and MIMD with a neat
E E diagram. .- .,. (lo Marks)
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; E 4 ?. Explain simple table-driven apqrOaroh used forppplication oriented software. (10 Marks)
E f b. Define the following with restr1t#t to real time ffngqamming:
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8, E ii) Global and local variables.rE id
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€ * iv) Data types. (10 Marks)
-2. B
'E e !.to. PART - B4a
a E 5 a. With a neqt block diagram, explain the typical structure of RTOS. (10 Marks)
5 i b. What is tack management? List the functions of task managemerit-."1{ith a neat diagramE 5 b. What ip,1ack management? List the functions of task management-r"'Yith a neat dngram
d.E discuss different states. (10 Marks)
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E E 6 a. Explain with a suitable diagram the multi-user and multi-tasking operating trr*1q*uru.;
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g. A b. What are the two scheduling strategies? Explain briefly. (r0..d[arks)
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E t 7 a. Explain the different phasor involved in the design of a RTS. 110 Mar J,,,,,,,,rr
: i b. Explain software design for RTS using software module. (10 Marks)
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- 8 a. With a general arrangement for drying overn, explain its requirements. (10 Marks)
E b. Write short notes on: i) Software -od.lirrg; ii) Yourdon methodology. (10 Marks)
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5. 10EC73USN
t',,
Seventh Semester B.E. Degree Examination, June / July 201,4
Power Electronics
Time: 3 hrs. Max. Marks:100
Note: Answer FIVEfull questions, selecting :+:r
, at reast TWO qu"riioorfrom each pirt. ,,,. ,,,,
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't.'t " PART-A "-""""'""'':"
I ";,,a. _.,,Yith the help of a block diagram, explain the working of a converter system..Also explain
', hw thyristor converters are classified. _ .- __!01
Marks)
b. GiV,e symbol, characteristic features of the following devices: i) GTO ,, "D"'' TRIAC iii)
MOSFEII iv) DIAC. r..,,,,,,, (08 Marks)
c. What'ffiJhe peripheral effects caused by power electronic coa ers? What are the
remedieS''fu.=thcm? o5 Marks)
2 a. In the circuii of Eig. Q2 (a), the BJT is specified to ha,:*eftts"'in th" range of 8 to 40. If
Vcc : 200 V, Rc *;1-1 O, Ve : 10 V, Vce(.uq : I V and Vnnt*ir : 1.5 V. Find (i) the value of
Re that results in satudon with an ODF of 5, (ii) tlre.foreed Prand (iii) the power loss Pr
= (09 Marks)in the transistor.
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rifui circuit shown in Fig. Q3 (b), the SCR has a latching:.g,uqrent of 50 mA and is
fulse of length 50 p sec. Show that without the resistor ryi,thettrnistor will fail to
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(04 Marks)
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dv .di-' and = orotection. A SCR circuit
dt dt'
rating : 100 V/ps, { rating : 50'dt
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Explain the need for
dv
voltage : 200 r,
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has the following data: Supply
A/psec. Calculate the snubber
(08 Marks)c ircuit element s using approximate expressio ns.
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b;'With the help of a neat circuit diagram and relevant waveforms, explain thehw.otking of a
sf@le phase dual converter with inductive load. * '''',',,.,"' (10 Marks)
"'..,:":,'"""'.,.r.. PART - B
a. Calcu conduction time of SCR and the peak SCR currentSftt flows in the circuit
shown in f'td QS (a) employing self commutation if the supply-,rolirge is 300 V, C : 1 prf,
L: 5 mH anb.'fty: 100 O. Assume that the circuit is initially,gelaxed. (08 Marks)
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6 a. With the help of a neefldircuit diagram and the relevarit*avcforms, explain the working of a
single phase AC .v, ge controller with RL load. Derive an expression for the RMS output
voltage. "" (loMarks)
b. Find the Sly$P,aird average current flowing through the heaier strown in Fig. Q6 (b). The
delay angle of both the thyristors is 45o. (10 Marks)-- --J -- Q-
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a. What will be the average power in the load for the halfirave controlled rectifier circuit
shown in Fig. Q4 (a), when o : . Assume the SCR to be ideal. Supply voltage is
4
330 sin 314t. Also calculate the RMS power and the rectification efficiency. (10 Marks)
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Fig. Q6 (b)
Derive an expression for the peak to peak ripple current AI for a stepdown chopper with RL
load. (10 Marksi
What is a switching mode regulator? With the help of circuit diagrams and waveforms, il'
explain the working of a Boost regulator with continuous current il. (10 Marks)
8 a. Explain the principle of operation of a single phase full bridge inverter with suitable circuit
diagram and waveforms. (10 Marks)
b. Explain briefly the various voltage control techniques in single phase inverters. (10 Marks)
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b.
b.

7. l0EC751USN
Seventh Semester B.E. Degree Examination, June/July 2014
DSP Algorithms and Architecture
ring
Max' Uutklw'
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+ I a. What is Digital Signal Processing? E.pl"i, the issues to be considerod in designing and
F
: implementing a DSP system. (09 Marks)
i b. Write a h{ATLAB code for design an FIR filter using Parks-McCleHpn'method. (05 Marks)
E c. Explain the decimation and interpolation processes with an exaulple. (06 Marks)
;i,(jx
H= 2 a. What is role oiu rmt.. in DSP? Explain the implementalioniif 4-bit shift right barrel shifter
v5
t ; with a diagram. (06 Marks)
T" ? b. Identifu the addressing rpdes of the operands in each"qf,the following instructions and their
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E : (i) ADD B (ii) ADD 567,8 (iii) ADDrt;TBddrE Y (i) ADD B (ii) ADD 5678h (iii) ADD.+ *addrreg (iv) ADD *addrreg, offsetreg -
E il (08 Marks)
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E g c. Explain the purpose of a program iequBncer With a block diagram. (06 Marks)
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g ! 3 a. Describe the multiplier / adder unit ofi-mS:2}C54xprocessor with a neat block diagram.
A E (06 Marks)
E f b. Describe any four data addressing rtrodes of TMS320C54XX DSP with examples.
E ! (0s Marks)e
$E c. Assuming current contents of ARr to be 200h, rVhat will be its contents after each of the
; E following TMs320c54x,'hddressing modes is used? Assrrme that the contents of ARO are
€ € 2oh.
F i (i) x AR: +0 (ii) x AR: * (iii) *+ARs(40h) t06 Marks)
5ii
?-* 4 a. Describe the operation of the following instructions of TMS320C54x processor with an
S : example :"
E € (i) MAC (ii) RPT (iii) MPY ,!i',,, ...1' (06 Marks)
E f b. Write i program to find the sum of a series of signed numbers stored at iuceessive locations
i E .;a the daia memory and place the result in the accumulator A ''"^ ,.." ,,
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g.e ie., A- ldmad(i) ',(o'6.Marks)
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b. Describe the operation of hardware timer with a neat diagram. (0S Mqd{,s)
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(.,< PART_B
: oi 5 a. Describe the importance of q-notution ln OSf algorithm implementation, with examples.
g b. What are the values represented by 16-bit fixed point number N : 4000h in Q15, Q10, Q7
7 notations? (10 Marks)
g c. Explain how the FIR filter algorithms can be implemented using TMS320C54XX
3 processor. (10 Marks)
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108C751
6 a. Explain a general DITFFT butterfly in place computation structure. (04 Marks)
b. Determine the no. of stages and number of butterflies in each stage and the total number of
butterflies needed for the entire computation of 512 point FFT. (06 Marks)
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tp_ c. Explain how the bit-reserved index generation can be done in 8-point FFT. Also w6[q@
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TMS320C54XX program for S-point DITFFT bit reversed index generation
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7 '5.
#*f.plain the memory interface block diagram for the TMS320C54XX procesqQ (06 Marks)
b.
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the I/O interface timing diagram for read-write-read sequence of opeffin. (06 Marks)
c. U . -temrpts? How int-emrpts are handled by the C54XX DSP prdhessors. (08 Marks)
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8 a. Draw the bryk1diagram of PCM3002 CODEC and explain abffih* (10 Marks)
b. With the hept";-15tock diagram, explain the image compffii8ir and reconstruction using
JPEG encoder anffioder. #+* (l0Marks)
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