The document summarizes the 80486 and Pentium microprocessors. It describes the key features and architecture of the 80486, including its on-chip cache, integrated floating point unit, and support for memory segmentation and paging. It then discusses the Pentium, noting it has a superscalar architecture, dynamic branch prediction, separate code and data caches, and a 64-bit data bus. The document provides pin diagrams and overviews of the architectures and workings of both processors.

1. 80486 MICROPROCESSOR
AND
PENTIUMBY,
NITISHKANT DUBEY (150860107007)
FEBA DANIEL (150860107008)
VIKSHIT GANJOO (150860107009)
PRACHI GETAI (150860107010)
ANJINI HALPATI (150860107011)
DIPANSHU JHA (150860107012)

2. INTRODUCTION TO 80486
• The Intel 80486, also known as the i486 or 486.
• The 80486 was introduced in 1989.
• The 80486 microprocessor is an improved version of the 80386
microprocessor that contains an 8K-byte cache and an 80387
arithmetic co processor. it executes many instructions in one
clocking period.

3. NEED OF 80486 OVER 80386
80386 80486
Date 1985 1989
CPU speed 12-40 MHz 16-100 MHz
Cores 1 1
Registers(Programmer) 16,? 16,?
RAM 4GB 4GB
Functional units 6 9
Pipeline stages 3 5
Cache off chip Yes (support) Yes (support)
Cache on chip 0 8 kb
Transistors 2,75,000 >1,00,000

4. FEATURES OF 80486
• On-chip 8 KB Level 1 Cache
• Integrated FPU
• Improved MMU performance
• Memory segmentation and paging are supported
• Address management and memory-space protection mechanisms
• Tightly coupled pipelining
• Fetching, decoding, address translation overlapped
• => Single Cycle Execution
• A 50 MHz 80486 executes around 40 million instructions per second
on average

5. ARCHITECTURE AND WORKING OF 80486

7. PIN DIAGRAM OF 80486

9. COMMON UNITS OF ARCHITECTURE FROM 80386
• Code Prefetch Unit
• Program look ahead func.
• 16-byte Code Queue
• Instruction Decode Unit
• Takes from Prefetch Queue
• Translates instructions into microcode
• Stores in 3-deep instruction queue for EU
• Segmentation Unit
• Translates logical address into linear addresses
• Checks for bus-cycle segmentation violations
• Linear addr. -> Paging unit
• Paging Unit
• Translates linear addr. to physical addr.

10. NEW UNITS INCLUDED IN 80486
• Cache Unit
• 4-way set associative
• Closely coupled with IPU
• Control Unit
• Interprets instructions from IDU ○ Controls IU, FPU, SU
• Integer (datapath) Unit
• Identifies where data is
• Performs arithmetic & logic operations, in 386 instruction set
• Floating-point Unit

11. INTRODUCTION TO PENTIUM
• A 32-bit microprocessor introduced by Intel in 1993. It contains 3.3
million transistors, nearly triple the number contained in its
predecessor, the 80486 chip. Though still in production, the
Pentium processor has been superseded by the Pentium
Pro and Pentium II microprocessors. Since 1993, Intel has
developed the Pentium III and more recently the Pentium 4
microprocessors.

12. FEATURES OF PENTIUM
• Introduced in 1993 with clock frequency ranging from 60 to 66 MHz
• The primary changes in Pentium Processor were:
– Superscalar Architecture
– Dynamic Branch Prediction
– Pipelined Floating-Point Unit
– Separate 8K Code and Data Caches
– Writeback MESI Protocol in the Data Cache
– 64-Bit Data Bus
– Bus Cycle Pipelining

13. PIN DIAGRAM

14. PENTIUM ARCHITECTURE AND WORKING

16. PENTIUM ARCHITECTURE
• It has data bus of 64 bit and address bus of 32-bit
• There are two separate 8kB caches – one for code
and one for data.
• Each cache has a separate address translation TLB
which translates linear addresses to physical.
• Code Cache:
– 2 way set associative cache
– 256 lines b/w code cache and prefetch buffer, permitting
prefetching of 32 bytes (256/8) of instructions

17. • Prefetch Buffers:
• Four prefetch buffers within the processor works as two
independent pairs.
• When instructions are prefetched from cache, they are placed into
one set of prefetch buffers.
• The other set is used as when a branch operation is predicted.
• Prefetch buffer sends a pair of instructions to instruction
decoder
• Instruction Decode Unit:
• It occurs in two stages – Decode1 (D1) and Decode2(D2)
• D1 checks whether instructions can be paired
• D2 calculates the address of memory resident operands

18. • Control Unit :
• This unit interprets the instruction word and microcode entry
point fed to it by Instruction Decode Unit
• It handles exceptions, breakpoints and interrupts.
• It controls the integer pipelines and floating point sequences
• Microcode ROM :
• Stores microcode sequences
• Arithmetic/Logic Units (ALUs) :
• There are two parallel integer instruction pipelines: u-pipeline
and v-pipeline
• The u-pipeline has a barrel shifter
• The two ALUs perform the arithmetic and logical operations
specified by their instructions in their respective pipeline

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