The document details the architecture of the 8086 microprocessor, including its components such as the bus interface unit and execution unit, and describes its segmented memory addressing scheme. It explains how physical and logical addresses are calculated, as well as the distinction between overlapping and non-overlapping segments. Additionally, the document highlights the advantages of the segmented memory scheme and provides information about the 8086's specifications and capabilities as the first 16-bit microprocessor.

1. MICROPROCESSORS AND MICROCONTROLLERS

2. 8086 Architecture
The 8086 architecture supports
• a 16-bit ALU.
• a set of 16 bit registers
• provides segmented memory addressing scheme
• a rich instruction set.
• Powerful interrupt structure
• Fetched instruction queue for overlapped fetching and
execution step.

3. 8086 Architecture

4. 8086 Architecture
CS305
MODULE 1
• The architecture of 8086 can be divided into two parts
• Bus Interface unit (BIU)
• Execution unit (EU)
Bus Interface Unit contains:
• Segment Registers
• Instruction Pointer
• 6-Byte Instruction Queue
Execution Unit contains:
• General Purposes Registers
• Stack Pointer
• Base Pointer
• Index Registers
• ALU
• Flag Register
• Instruction Decoder
• Timing & Control Unit

5. 8086 Architecture
The bus interface unit is responsible for
• physical address calculations
• predecoding instruction byte queue ( 6 bytes long).
• making the system bus signal available for external devices.
• The 8086 addresses a segmented memory.
• The complete physical address which is 20-bits long is
generated using segment and offset registers, each 16-bits long
Generating a physical address:
1. The content of segment register (segment address) is shifted left
bit-wise four times.
2. The content of an offset register (offset address) is added to the
result of the previous shift operation.
• These two operations together produce a 20-bit physical address.
Address + Offset Address = Physical Address(Left Shifted)

6. 8086 Architecture
Logical address is in the form of: Base Address: Offset->
Offset is the displacement of the memory location from the
starting location of the segment.
To calculate the physical address of the memory, BIU uses the
following formula:
Physical Address = Base Address of Segment * 10 + Offset

7. Hexadecimal number
8421
Decimal (D) Hexa(H) Binary
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B
12 C
13 D
14 E
15 F
16 10

8. Physical Address calculation
● Segment Address = 1005H = 0001 0000 0000 0101
● Offset Address =5555H = 0101 0101 0101 0101
● Physical Address = Segment Address(Left Shifted 4 Times) + Offset Address
● = 0001 0000 0000 0101 0000 +
● 0101 0101 0101 0101
● --------------------------------------------
● 0001 0101 0101 1010 0101 = 155A5(H)

9. Logical Address
● CS:IP
● DS:BP
● SS:SP
● DS:SI
● ES:DI

10. Find physical address
● DS:SI  10A2 H:0F10H
● SS:SP  1C2B : 1006 H

11. 8086 Architecture
MODULE 1
Segment Address
Offset Address
=
=
0001 0000 0000 0101 0000 (Left Shifted 4 times)
5555H = 0101 0101 0101 0101
Segment Address +Offset Address (Left Shifted 4
Times)
Physicial Address = 0001 0000 0000 0101 0000 + 0101 0101 0101 0101
= 0001 0101 0101 1010 0101
= 155A5
Eg : If Segment address is 1005H and offset address is 5555H then
the physical address will be generated as
Segment Address = 1005H = 0001 0000 0000 0101

12. 8086 Architecture
Segment addressed by the segment value 1005H can have
offset value from 0000H to FFFFH within it i.e maximum 64K
locations can be allocated for segment
Segment Address : base address of a particular segment
Offset Address : indicates the distance of required memory
locations in the segment from base address
Offset is a 16-bit number, each segment can have a maximum
of 216 (64K) locations
BIU has a separate adder to perform physical address
calculation by adding segment and offset address.
• Segment address value is content of code,data,stack,
or extra segment register.
• Offset may be the content of IP,BX,SI,DI,SP,BP or an
immediate 16-bit value.

13. 8086 Architecture
• Once the opcode is fetched and decoded, the external bus
becomes free while the Execution Unit is executing the
instruction.
• While the fetched instruction is executed internally, the
external bus is used to fetch the machine code of the next
instruction and arrange it in a queue called as predecoded
instruction byte queue.
• This is a 6 byte long queue, works in first-in first-out policy.
• While the opcode is fetched by the bus interface unit (BIU),
the execution unit (EU) executes the previously decoded
instruction concurrently.

14. 8086 Architecture
MODULE 1
Instruction Queue:
• BIU gets upto 6 bytes of next instructions and stores them in
the instruction queue.
• When EU executes instructions and is ready for its next
instruction, then it simply reads the instruction from this
instruction queue resulting in increased execution speed.
• Fetching the next instruction while the current instruction
executes is called pipelining.( based on FIFO) .
• This is much faster than sending out an addresses to the
system memory and waiting for memory to send back the
next instruction byte or bytes .

15. 8086 Architecture
MODULE 1
Execution Unit
• Contains the register set of 8086 except segment register and IP
• It has a 16-bit ALU, which performs arithmetic and logic functions.
• It has 16-bit flag register reflects the result of execution.
• The decoding unit decodes the opcode bytes issued from the
instruction byte queue.
• The timing and control circuit unit derives necessary control
signals to execute instruction opcode received from the queue,
depending upon the information from the decoding circuit.
• The EU may pass the results to the BIU for storing them in memory.

16. 8086 Architecture
MODULE 1
MEMORY SEGMENTATION IN 8086
• In segmentation memory scheme ,the complete physically available
memory may be divided into a number of logical segments .
• Each segment is 64k Bytes in size and is addressed by one of the
segment registers.
• The 16 bit contents of the segment register actually point to the
starting location of a particular segments.
• An offset address is needed to address a specific memory location
within the segments.
• The offset address is 16 bit long so that maximum offset value can
be FFFF H.
• The CPU 8086 is able to address 1M bytes of physical memory .
• The complete 1M bytes of memory can be divided into 16 segments
, each of 64K bytes size .
• Addresses of the segments maybe assigned as 0000H to F000H .
• Offset address values are from 0000H to FFFFH .
• Physically address range 00000H to FFFFFH .

17. 8086 Architecture
MODULE 1
In 8086, memory has four different types of
segments. These are:
• Code Segment
• Data Segment
• Stack Segment
• Extra Segment

18. 8086 Architecture
CS305
MODULE 1
Types Of Segmentation
1. Overlapping Segment
• A segment starts at a particular address and its maximum size
can go up to 64kilobytes.
• if another segment starts along with this 64kilobytes location of
the first segment, then the two are said to be Overlapping Segment
2. Non-Overlapped Segment
• A segment starts at a particular address and its maximum size
can go up to 64kilobytes.
• if another segment starts before this 64kilobytes location of the
first segment, then the two segments are said to be Non-
Overlapped Segment.

19. 8086 Architecture
CS305
MODULE 1

20. 8086 Architecture
MODULE 1
Advantages of segmented memory scheme
1. Allows the memory capacity to be 1MB although the actual
addresses to b e handled are of 16 bit size.
2. Allows the placing of code,data and stack portions of the same
program in different parts(segments) of memory each time the
program is executed i.e provision for relocation is done.
3. Permits a program and data to be put into different area of
memory each time the program is executed i.e. provision for
relocation is done

21. Signal Description of 8086
CS305
MODULE 1
• Intel 8086 was launched in 1978.
• It was the first 16-bit microprocessor.
• This microprocessor had major improvement over the execution
speed of 8085.
• It is available as 40-pin and Dual-Inline-Package (DIP).
• It is available in three versions:
• 8086 (5 MHz)
• 8086-2 (8 MHz)
• 8086-1 (10 MHz)
• It consists of 29,000 transistors.
• It has a 16 line data bus and 20 line address bus.
• It could address up to 1 MB of memory.
• It has more than 20,000 instructions.
• It supports multiplication and division.

22. Signal Description of 8086
MODULE 1

23. THANK YOU