An 1.2V 440-MS/s 0.13-µm CMOS Pipelined       Analog-to-Digital Converter With 5-8bit Mode                         Selecti...
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  1. 1. An 1.2V 440-MS/s 0.13-µm CMOS Pipelined Analog-to-Digital Converter With 5-8bit Mode Selection Tero Nieminen and Kari Halonen Aalto University School of Science and Technology Department of Micro- and Nanosciences P.0 Box 11000, FIN-00076 Aalto, Finland Email: Telephone: +358 9 470 22275 Abstract—In this paper, an 8-bit (with 5-8bit mode selection), CLKIN CLOCK GENERATION440-MS/s pipelined Analog-to-Digital Converter (ADC) is pre-sented. The ADC utilizes double-sampling in order to relaxthe operational amplifier (opamp) settling time requirements. VIN PL PL PL PL PL PL Flash S/H stage stage stage stage stage stage stageRedundant sign digit (RSD) correction compensates offset errors 2b 1.5b 1.5b 1.5b 1.5b 1.5b 1.5bof the comparators. The ADC is designed with a 0.13-µm CMOSprocess. In the 8-bit mode, measured effective number of bits VREF 2 2 2 2 2 2 2(ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while DELAY ALIGNMENTthe current drawn from 1.2V supply is 83mA. 2 2 2 2 2 2 2 I. I NTRODUCTION RSD correction 8 In modern Synthetic Aperture Radar (SAR) systems, wide- DOUTband data transform is needed. An ADC with medium res- Fig. 1. Block diagram of the ADC.olution, high sampling rate and good dynamic performanceis thus required. Recently, with reduced process linewidthsand supply voltages, opamp design in ADCs has become even stages. Current consumption of the amplifiers of stages 4-6 aremore critical due to decreased signal headroom and moderate reduced by factor of two, resulting in lower power dissipation.gain of the transistors. In order to achieve sufficient gain and Channel mismatches (gain, offset and timing mismatch)signal swing with such a low supply voltage (1.8V and 1.2V), are traditional drawbacks of parallel pipelined ADCs. It istwo-stage [1], [2], [3], [4], [5], [6], [7] or three-stage amplifiers assumed that the capacitor values used in the design satisfy[8], [9], [10], [7] have been preferred in medium-resolution (8- the matching accuracy for 8 bits. To reduce the gain mismatch,10 bits) pipelined ADCs. some margin (10dB) is reserved for the open-loop gain of the In this work, two parallel 8-bit 220-MS/s ADCs with shared designed opamps. Thus, only RSD correction is utilized in theopamps and comparators are utilized in order to meet the design.requirements of the SAR system. The paper is organized as All clock signals are generated internally from 80mV si-follows. In Section II the ADC architecture is presented. Sec- nusoidal clock input. By using small-amplitude clock input,tion III presents the circuit description. Measured performance coupling of the clock signal via bonding wires can be shown in Section IV and conclusions in V. III. C IRCUIT D ESCRIPTION II. S YSTEM DESCRIPTION SH circuit and a single 1.5-bit multiplying digital-to-analog The top level block diagram of the ADC is shown in Fig. 1. converter (MDAC) are presented in Figs 3 and 2, respectively.It consists of a sample/hold (SH) front-end stage, six 1.5-bit The MDAC is conventional 1.5-bit implementation. Double-pipeline stages and a 2-bit flash back-end stage. To achieve sampling is realized by adding switches S1 and S2 [2] andsampling rate of 440MS/s with 220MHz sampling clocks, the duplicating every switch and capacitor for the both phases.SH and the pipeline stages utilize double-sampling. Scaling The sub-ADC output Q controls the switches connected todown of the back-end stage amplifiers and capacitors is done the reference voltages. For simplicity, the MDAC is presentedto save power and chip area. The SH and pipeline stage single-ended, although all structures in the design are differ-sampling capacitor values are determined by sampling noise ential.( kT -noise) requirements. The capacitors of pipeline stages 2-6 C In the SH and MDAC design, there are two critical designare halved, due to relaxed noise requirements of the back-end issues. First, the SH front-end stage amplifier must satisfy 8-978-1-4244-8971-8/10$26.00 c 2010 IEEE
  2. 2. 2 Vdd SIN1 CF 2 M11 Vcmfb2 M7 M8 Vcmfb2 M12 1 S1 1 Vcs SIN2 1 0.4pF 100Ω M5 M6 100Ω 0.4pF CS 2 Vo+ Vcasp Vo- M3 M4 Q VREF+ Q −gm VOUT VREF- VIN ADC Vcasn VCM + CL M9 Vin+ M1 M2 Vin- M10 1 CS SIN3 2 Vcmfb1 M0 2 2 1 S2 SIN4 CF 1 Fig. 4. Two-stage Miller-compensated opamp Fig. 2. 1.5-bit double-sampling MDAC settling time of the MDAC output. To achieve fast operation, a dynamic differential pair comparator [11] [13] is utilized in 1 S3 the pipeline and the flash stages. RSD correction relaxes the S4 comparator offset requirements. In this case, offset voltage of Cs 0.2pF ±VREF S1 2 2 4 can be tolerated [11]. To avoid the memory effect, 2 the comparator is reset at the other half of the latching clock 1 0.2pF 1 signal. Like the opamps, comparators are also shared, which,Vin+ − Vo+ due to the double-sampling, means that the latching clock 2 + 1 2 0.2pF - signal must operate at twice speed compared to the MDAC 1 + Vo- clocks. S2 Cs 0.2pF Vin- The SH and the pipeline stages need two non-overlapping =signal ground (0.6V) Load (front-end PL-stage) clock signals at 220-MHz, whereas the comparators and flip- flops operate at 440-MHz. Square signal is created by am- Fig. 3. Double-sampling fliparound SH circuit plifying the 440-MHz small-amplitude sinusoidal clock input (80mV) with an open-loop amplifier (two differential pair stages with resistive loads) and cross-coupled inverters. 220-bit settling accuracy, which leads to opamp open-loop gain MHz clocks are obtained by customized flip-flop [14] -requirement >50dB, while large gain-bandwidth GBW (several based frequency divider. Nonoverlapping clocks for the SHtimes of the clock frequency) should be achieved. To obtain and MDACs are created with clock generator constructed ofsufficient gain and signal headroom, the design utilizes a inverters and NOR gates. The digital logic required for thetwo-stage Miller-compensated amplifier, with input telescopic mode selection (5-8 bits) is not shown in detail. Low-voltageand output common-source rail-to-rail stage, as depicted in differential signal (LVDS) [15] drivers are used to collect theFig 4. Simulated open-loop gain of the opamp is 60dB, output clock and data.GBW 3.0GHz (with 0.4pF load) and phase margin (PM) 60o .Each amplifier has same topology, but some scaling is done IV. M EASUREMENTSfor power saving. In three back-end stages, in addition of The chip was fabricated in 1P6M 130nm CMOS process,halving the opamp currents, the NMOS cascode transistors are and bonded directly to 4-layer PCB. The ADC microphoto-removed in order to have more saturation margin for the input graph is shown in Fig 5. The ADC core occupies approxi-differential pair. Common-mode feedback (CMFB) circuits are mately 0.4 mm2 , but required amount of IO-pads determinerealized by switched capacitors (SC) [11]. the total area to be 2.0 mm2 . A critical issue in low-voltage and high-speed designs arises Measured parameters of the ADC are differential non-from linearity of the input switches. In this work, bootstrapped linearity/integral non-linearity DNL/INL in static performanceswitches [12] [11] are employed in the SH (switches S1 -S4 ) measurements. Dynamic properties of the ADC include effec-and the first pipeline stage input (switches SIN1 -SIN4 ), whereas tive number of bits (ENOB), effective resolution bandwidthother switches are implemented as transmission gates. (ERBW) and spurious-free dynamic range (SFDR). In the utilized pipelined stages, comparator settling time has Measured DNL and INL in 8-bit mode are presented into be short (in order of 0.2ns), so that it would not restrict the Fig 6 and the averaged (ten sample vectors with the length
  3. 3. DNL plot INL plot 0.08 0.25 0.06 0.2 0.04 0.15 0.02 0.1 DNL[LSB] INL[LSB] 0 0.05 −0.02 0 −0.04 −0.05 −0.06 −0.1 Fig. 5. The ADC chip microphotograph −0.08 −0.15 DNL plot INL plot 0 10 20 30 40 0 10 20 30 40 0.4 1.5 Code Code 0.3 Fig. 7. Measured DNL and INL, 5b-mode 1 0.2 Power spectrum 0 0.1 0.5 −10 0DNL[LSB] INL[LSB] 0 −20 −0.1 −30 Relative Power [dBc] −0.2 −0.5 −40 −0.3 −1 −50 −0.4 −60 −0.5 −1.5 0 100 200 300 0 100 200 300 Code Code −70 Fig. 6. Measured DNL and INL, 8b-mode −80 −90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Frequency [Hz] 8of 8192) output spectrum in Fig 8. Fig 7 and 9 present the x 10static measurement results and the output spectrum in 5-bit Fig. 8. Measured ADC output spectrum, 8b-modemode, respectively. From the figures it can be seen that themeasured DNL and INL in 8-bit mode are -0.41/+0.37LSBand -1.03/+1.02LSB, respectively. From the dynamic mea- shortcoming is likely originated from disturbances coupledsurements, SFDR is 46.5dBc and ENOB 6.10-bits. In the into the external references. Furthermore, since the references5-bit mode, DNL/INL are 0.08/0.2LSB and the ENOB is have to charge signal-dependent amount of capacitance (de-calculated to be 4.75-bits. Fig 10 presents measured ENOB pending on amount of MDACs connected to the reference),in all ADC modes at frequencies from DC to 160MHz, which voltage drops occur over the bondwire inductances, degradingis the desired bandwidth of the ADC. 7- and 8-bit modes the performance particularly at high clock frequencies. Thus,have ERBW of approximately 200MHz, whereas 5- and 6- when using external references, large on-chip capacitors arebit modes it was measured to be as high as 850MHz (the needed to stabilize the reference voltages. According to theoutput is of course folded, but measured ENOB with 850MHz measurements, lack of these capacitors is emphasized in 8-bitinput is 4.90, which is 0.5-bits lower than maximum 5.40) mode (of course, when using lower bit modes, switchings andThe performance is summarized and the results are collected thus voltage drops in references are reduced).in Table I. It is pointed out that in 8-bit mode, there is some short- V. C ONCLUSIONcoming in the ADC performance (ENOB does not increase An 8-bit (with selection of 5-8 bit modes) pipelined ADCas much as it should from 7b- to 8b-mode). After some in 0.13µm CMOS process was introduced. Architecture, im-post-measurement simulations, it was figured out that the plementation and most important circuit design issues were
  4. 4. Power spectrum 0 discussed. Measurements show that with full-scale 160-MHz input, ENOB of 6.10, 5.95, 5.30 and 4.75-bits in 8, 7, 6 −10 and 5-bit modes, respectively, can be achieved. In the future, relatively large on-chip reference capacitors should be used, −20 particularly if the voltages are taken externally. −30 ACKNOWLEDGMENTRelative Power [dBc] This work is supported by the European Space Agency −40 (ESA). −50 R EFERENCES [1] C. Peach, A. Ravi, R. Bishop, K. Soumyanath, and D. J. Allstot, “A 9bit −60 400 Msample/s Pipelined Analog-to-Digital Converter in 90nm CMOS,” in Proc. European Solid-State Circuits Conf., 12-16Sep. 2005, pp. 535– 538. −70 [2] J. Li, M. Leboeuf, M. Courcy, and G. Manganaro, “A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration,” in −80 Proc. Custom Integrated Circuits Conf., 16-19Sep. 2007, pp. 317–320. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Frequency [Hz] 8 [3] B. Hernes, A. Briskemyr, T. N. Andersen, F. Telsto, T. E. Bonnerud, x 10 and O. Moldsvor, “A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13µm Digital CMOS,” in Proc. IEEE Intl. Solid-State Circuits Conf., Fig. 9. Measured ADC output spectrum, 5b-mode Digest of Technical Papers, 15-19Feb. 2004. [4] S. K. Gupta, M. A. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC With Signal frequency vs ENOB 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable 6.4 Time-Interleaved Architecture,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2650–2657, Dec. 2006. 6.2 [5] L. Picolli, P. Malcovati, L. Crespi, F. Chaahoub, and A. Baschirotto, “A 90nm 8b 120Ms/s-250Ms/s Pipeline ADC,” in Proc. European Solid- 6 State Circuits Conf., 15-19Sep. 2008, pp. 266–269. [6] T.-H. Oh, H.-Y. Lee, H.-J. Park, and J.-W. Kim, “A 1.8V 8-bit 250Msam- ple/s Nyquist-Rate CMOS Pipelined ADC,” in Proc. International 5.8 Symposium on Circuits and Systems, 23-26May 2004, pp. I–9–I–12. [7] S.-C. Lee, Y.-D. Jeon, K.-D. Kim, J.-K. Kwon, J. Kim, J.-W. Moon,ENOB[bits] 8b 5.6 7b and W. Lee, “A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for 6b Flat-Panel Display Applications,” in Proc. IEEE Intl. Solid-State Circuits 5b 5.4 Conf., Digest of Technical Papers, 11-15Feb. 2007, pp. 458–615. [8] Y.-J. Kim, H.-C. Choi, K.-H. Lee, G.-C. Ahn, S.-H. Lee, J.-H. Kim, K.-J. Moon, M. Choi, K.-H. Moon, H.-J. Park, and B.-H. Park, “A 5.2 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC Based on Multi-Stage Amplifiers,” in Proc. Custom Integrated Circuits Conf., 13-16Sep. 2009, 5 pp. 271–274. [9] S.-C. Lee, K.-D. Kim, J.-K. Kwon, J. Kim, and S.-H. Lee, “A 10-bit 400- MS/s 160-mW 0.13-µm CMOS Dual-Channel Pipeline ADC Without 4.8 Channel Mismatch Calibration,” IEEE J. Solid-State Circuits, vol. 41, 10 0 10 1 2 10 Jul. 2006. Signal frequency[MHz] [10] S.-C. Lee, Y.-D. Jeon, J.-K. Kwon, and J. Kim, “A 10-bit 205MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat-Panel Display Applications,” Fig. 10. Measured signal frequency vs ENOB IEEE J. Solid-State Circuits, vol. 42, Dec. 2007. [11] L. Sumanen, M. Waltari, and K. A. I. Halonen, “A 10-bit 200-MS/s TABLE I CMOS Parallel Pipeline A/D Converter,” IEEE J. Solid-State Circuits, T HE ADC SUMMARY vol. 36, no. 7, pp. 1048–1055, Jul. 2001. [12] M. Dessouky and A. Kaiser, “Input switch configuration suitable for rail-to-rail operation of switched opamp circuits,” Electronics Letters, Process 130nm CMOS vol. 35, Jan. 1999. [13] J. Riikonen, M. Aho, V. Hakkarainen, L. Sumanen, and K. Halonen, Resolution 5-8 bits “A 10-bit 400-MS/s 170mW 4-Times Interleaved A/D Converter in Sampling rate 440-MS/s 0.35-µm BiCMOS,” in Proc. International Symposium on Circuits and Supply voltage 1.2V Systems, 23-26 May 2005, pp. 4622–4625. Input range 0.8Vppdiff [14] J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Area (core+IOs) 2.0 mm2 Circuits, vol. 32, Jan. 1997. [15] M. Chen, J. Silva-Martinez, M. Nix, and M. E. Robinson, “Low-Voltage Mode 8 7 6 5 Low-Power LVDS Drivers,” IEEE J. Solid-State Circuits, vol. 40, Feb. Power[mW] 100 83 66 50 2005. DNL/INL[LSB] 0.41/1.03 0.50/0.64 0.24/0.36 0.08/0.2 SFDR@162MHz 46.5 47.5 45.5 43 ENOB@162MHz 6.10 5.95 5.30 4.75 ENOB@80MHz 6.30 6.20 5.40 4.80 ERBW[MHz] 200 200 850 >850