3DD 1e SyCers
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The document describes SyCERS, a SystemC-based framework for modeling and simulating dynamically reconfigurable systems on chip (RSoCs). It aims to allow design space exploration and validation of reconfigurable architectures and systems. SyCERS uses SystemC to model hardware and software components and their communication. It proposes a methodology using three abstraction levels and supports modeling reconfiguration through function pointers and mutexes. The document presents a case study using SyCERS to model and simulate two applications mapped to the Caronte RSoC architecture.
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This document discusses Altera's FPGA strategy for reconfigurable hardware in industry applications. It defines reconfigurable hardware as an architecture that does not require on-the-fly timing analysis because product qualification is extensively done through temperature and cycle testing without hardware architecture changes. It then shows how programmable solutions have evolved from single CPU and DSP cores to multi-core processors and coarse-grained arrays with FPGAs moving to fine-grained, massively parallel arrays with embedded hard IP blocks. Future trends include challenges of scaling CPUs due to physical limits and the benefits of parallelism through hardware reconfiguration.
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AI 101: An Introduction to the Basics and Impact of Artificial Intelligence
AI 101: An Introduction to the Basics and Impact of Artificial Intelligence
3DD 1e SyCers
- 1. SyCERS a SystemC Design Exploration Framework for SoC Reconfigurable Architecture Monte Carlo Resort, Lav Vegas - Nevada June 29th, 2006 Carlo Amicucci: carlo.amicucci@microlab-mi.net Fabrizio Ferrandi: ferrandi@elet.polimi.it Marco D. Santambrogio: marco.santambrogio@polimi.it Donatella Sciuto: donatella.sciuto@elet.polimi.it
- 11. Reconfiguration Control Interfaces Status: .:: Intro > Problem > Objectives > SoA > SystemC .:: SyCERS > Methodology > Structure .:: Case Study > Caronte > SyCERS mod. > Aps > SyCERS perf. .:: Conclusions
- 13. Reconfigurable component behavior Status: .:: Intro > Problem > Objectives > SoA > SystemC .:: SyCERS > Methodology > Structure .:: Case Study > Caronte > SyCERS mod. > Aps > SyCERS perf. .:: Conclusions
- 16. Caronte Models Control Code (SystemC) Compiler GCC Configurations BlackBox (SystemC) Configuration Control Process Scheduler and Controller Memory Model Cross Compiler GCC Control Code (C/C++) Status: .:: Intro > Problem > Objectives > SoA > SystemC .:: SyCERS > Methodology > Structure .:: Case Study > Caronte > SyCERS mod. > Aps > SyCERS perf. .:: Conclusions Modello Memoria BlackBoxes Model CoreConnect PowerPC ISS Open SystemC PowerPC core models
- 17. Caronte Functional View Status: .:: Intro > Problem > Objectives > SoA > SystemC .:: SyCERS > Methodology > Structure .:: Case Study > Caronte > SyCERS mod. > Aps > SyCERS perf. .:: Conclusions
- 22. Questions