Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An fpga implementation of the lms adaptive filter eSAT Journals
Abstract This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects. Index Terms: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Brief Explanation about the Tau-Leaping Process, Parallel Processing and NVIDIA's CUDA architecture
And the use of cuTau - Leaping for simulation of Biological systems
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An fpga implementation of the lms adaptive filter eSAT Journals
Abstract This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects. Index Terms: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Brief Explanation about the Tau-Leaping Process, Parallel Processing and NVIDIA's CUDA architecture
And the use of cuTau - Leaping for simulation of Biological systems
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJCER (www.ijceronline.com) International Journal of computational Engineeri...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJCER, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, research and review articles, IJCER Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathematics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer review journal, indexed journal, research and review articles, engineering journal, www.ijceronline.com, research journals,
yahoo journals, bing journals, International Journal of Computational Engineering Research, Google journals, hard copy of Certificate,
journal of engineering, online Submission
Multilevel Hybrid Cognitive Load Balancing Algorithm for Private/Public Cloud...IDES Editor
Cloud computing is an emerging computing
paradigm. It aims to share data, resources and services
transparently among users of a massive grid. Although the
industry has started selling cloud-computing products,
research challenges in various areas, such as architectural
design, task decomposition, task distribution, load
distribution, load scheduling, task coordination, etc. are still
unclear. Therefore, we study the methods to reason and model
cloud computing as a step towards identifying fundamental
research questions in this paradigm. In this paper, we propose
a model for load distribution on cloud computing by modeling
them as cognitive systems and using aspects which not only
depend on the present state of the system, but also, on a set of
predefined transitions and conditions. The entirety of this
model is then bundled to cater the task of job distribution
using the concept of application metadata. Later, we draw a
qualitative and simulation based summarization for the
proposed model. We finally evaluate the results and draw up
a series of key conclusions in cloud computing for future
exploration.
FIR Filter Implementation by Systolization using DA-based DecompositionIDES Editor
In this paper we present 1D and 2D systolic
Distributed Arithmetic (DA) based structures that are designed
for the implementation of Finite Impulse Response (FIR) filters.
The paper compares the 1D DA based systolic structure with
1D systolic DA based decomposition method. The filters are
implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using
HDL and system metrics like Area, Gate Count, Maximum
Usable Frequency and Power consumption are estimated for
different filter orders and address lengths. The 1D systolic
decomposition structure is also compared with the existing
system generator implementation of DA FIR.. Results for an
exemplary implementation are presented.
Design and Implementation of Low Power DSP Core with Programmable Truncated V...ijsrd.com
The programmable truncated Vedic multiplication is the method which uses Vedic multiplier and programmable truncation control bits and which reduces part of the area and power required by multipliers by only computing the most-significant bits of the product. The basic process of truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. These results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision vedic multiplier is implemented, but the active section of the truncation is selected by truncation control bits dynamically at run-time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a high speed Vedic truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. On comparison with the previous parallel multipliers Vedic should be much more fast and area should be reduced. Programmable truncated Vedic multiplier (PTVM) should be the basic part implemented for the arithmetic and PTMAC units.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Digital Implementation of Artificial Neural Network for Function Approximatio...IOSR Journals
: The soft computing algorithms are being nowadays used for various multi input multi output
complicated non linear control applications. This paper presented the development and implementation of back
propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA
(Field Programmable Gate Array) for neural network implementation provides flexibility in programmable
systems. For the neural network based instrument prototype in real time application. The conventional specific
VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network
design, FPGA have higher speed and smaller size for real time application than the VLSI design. The
challenges are finding an architecture that minimizes the hardware cost, maximizing the performance,
accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA.
Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description
Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for
training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design
was tested on a FPGA demo board
A simplified design of multiplier for multi layer feed forward hardware neura...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGcscpconf
Parallel computing systems compose task partitioning strategies in a true multiprocessing
manner. Such systems share the algorithm and processing unit as computing resources which
leads to highly inter process communications capabilities. The main part of the proposed
algorithm is resource management unit which performs task partitioning and co-scheduling .In
this paper, we present a technique for integrated task partitioning and co-scheduling on the
privately owned network. We focus on real-time and non preemptive systems. A large variety of
experiments have been conducted on the proposed algorithm using synthetic and real tasks.
Goal of computation model is to provide a realistic representation of the costs of programming
The results show the benefit of the task partitioning. The main characteristics of our method are
optimal scheduling and strong link between partitioning, scheduling and communication. Some
important models for task partitioning are also discussed in the paper. We target the algorithm
for task partitioning which improve the inter process communication between the tasks and use
the recourses of the system in the efficient manner. The proposed algorithm contributes the
inter-process communication cost minimization amongst the executing processes.
ModelicaML Value Bindings for Automated Model CompositionDaniele Gianni
Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJCER (www.ijceronline.com) International Journal of computational Engineeri...ijceronline
Call for paper 2012, hard copy of Certificate, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJCER, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, research and review articles, IJCER Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathematics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer review journal, indexed journal, research and review articles, engineering journal, www.ijceronline.com, research journals,
yahoo journals, bing journals, International Journal of Computational Engineering Research, Google journals, hard copy of Certificate,
journal of engineering, online Submission
Multilevel Hybrid Cognitive Load Balancing Algorithm for Private/Public Cloud...IDES Editor
Cloud computing is an emerging computing
paradigm. It aims to share data, resources and services
transparently among users of a massive grid. Although the
industry has started selling cloud-computing products,
research challenges in various areas, such as architectural
design, task decomposition, task distribution, load
distribution, load scheduling, task coordination, etc. are still
unclear. Therefore, we study the methods to reason and model
cloud computing as a step towards identifying fundamental
research questions in this paradigm. In this paper, we propose
a model for load distribution on cloud computing by modeling
them as cognitive systems and using aspects which not only
depend on the present state of the system, but also, on a set of
predefined transitions and conditions. The entirety of this
model is then bundled to cater the task of job distribution
using the concept of application metadata. Later, we draw a
qualitative and simulation based summarization for the
proposed model. We finally evaluate the results and draw up
a series of key conclusions in cloud computing for future
exploration.
FIR Filter Implementation by Systolization using DA-based DecompositionIDES Editor
In this paper we present 1D and 2D systolic
Distributed Arithmetic (DA) based structures that are designed
for the implementation of Finite Impulse Response (FIR) filters.
The paper compares the 1D DA based systolic structure with
1D systolic DA based decomposition method. The filters are
implemented on a Xilinx Virtex II Pro (XC2VP30) FPGA using
HDL and system metrics like Area, Gate Count, Maximum
Usable Frequency and Power consumption are estimated for
different filter orders and address lengths. The 1D systolic
decomposition structure is also compared with the existing
system generator implementation of DA FIR.. Results for an
exemplary implementation are presented.
Design and Implementation of Low Power DSP Core with Programmable Truncated V...ijsrd.com
The programmable truncated Vedic multiplication is the method which uses Vedic multiplier and programmable truncation control bits and which reduces part of the area and power required by multipliers by only computing the most-significant bits of the product. The basic process of truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. These results in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision vedic multiplier is implemented, but the active section of the truncation is selected by truncation control bits dynamically at run-time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analyzed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a high speed Vedic truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. On comparison with the previous parallel multipliers Vedic should be much more fast and area should be reduced. Programmable truncated Vedic multiplier (PTVM) should be the basic part implemented for the arithmetic and PTMAC units.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Digital Implementation of Artificial Neural Network for Function Approximatio...IOSR Journals
: The soft computing algorithms are being nowadays used for various multi input multi output
complicated non linear control applications. This paper presented the development and implementation of back
propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA
(Field Programmable Gate Array) for neural network implementation provides flexibility in programmable
systems. For the neural network based instrument prototype in real time application. The conventional specific
VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network
design, FPGA have higher speed and smaller size for real time application than the VLSI design. The
challenges are finding an architecture that minimizes the hardware cost, maximizing the performance,
accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA.
Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description
Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for
training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design
was tested on a FPGA demo board
A simplified design of multiplier for multi layer feed forward hardware neura...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DYNAMIC TASK PARTITIONING MODEL IN PARALLEL COMPUTINGcscpconf
Parallel computing systems compose task partitioning strategies in a true multiprocessing
manner. Such systems share the algorithm and processing unit as computing resources which
leads to highly inter process communications capabilities. The main part of the proposed
algorithm is resource management unit which performs task partitioning and co-scheduling .In
this paper, we present a technique for integrated task partitioning and co-scheduling on the
privately owned network. We focus on real-time and non preemptive systems. A large variety of
experiments have been conducted on the proposed algorithm using synthetic and real tasks.
Goal of computation model is to provide a realistic representation of the costs of programming
The results show the benefit of the task partitioning. The main characteristics of our method are
optimal scheduling and strong link between partitioning, scheduling and communication. Some
important models for task partitioning are also discussed in the paper. We target the algorithm
for task partitioning which improve the inter process communication between the tasks and use
the recourses of the system in the efficient manner. The proposed algorithm contributes the
inter-process communication cost minimization amongst the executing processes.
ModelicaML Value Bindings for Automated Model CompositionDaniele Gianni
Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
Validation of Spacecraft Behaviour Using a Collaborative ApproachDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Collaborative engineering solutions and challenges in the development of spac...Daniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Workshop presentation in DSim Day, research event on Distributed Simulation, Rome, Italy, March, 2010.
Please visit:
https://sites.google.com/site/simulationarchitecture/
for further information.
A framework for distributed control and building performance simulationDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Automated Performance Analysis of Business ProcessesDaniele Gianni
Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Collaborative modeling and co simulation with destecs - a pilot studyDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Modules for reusable and collaborative modeling of biological mathematical sy...Daniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
A vision on collaborative computation of things for personalized analysesDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
jEQN a java-based language for the distributed simulation of queueing networksDaniele Gianni
Presentation at the ISCIS 2006 Conference in Istanbul, Turkey.
Simulation language for Extended Queueing Networks on IEEE HLA infrastructures.
For further info, please visit:
https://sites.google.com/site/simulationarchitecture/
SysML to Discrete-event Simulation to Analyze Electronic Assembly SystemsDaniele Gianni
Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
The increasing demand for computing power in fields such as biology, finance, machine learning is pushing the adoption of reconfigurable hardware in order to keep up with the required performance level at a sustainable power consumption. Within this context, FPGA devices represent an interesting solution as they combine the benefits of power efficiency, performance and flexibility. Nevertheless, the steep learning curve and experience needed to develop efficient FPGA-based systems represents one of the main limiting factor for a broad utilization of such devices.
In this talk, we present CAOS, a framework which helps the application designer in identifying acceleration opportunities and guides through the implementation of the final FPGA-based system. The CAOS platform targets the full stack of the application optimization process, starting from the identification of the kernel functions to accelerate, to the optimization of such kernels and to the generation of the runtime management and the configuration files needed to program the FPGA.
AFFECT OF PARALLEL COMPUTING ON MULTICORE PROCESSORScscpconf
Our main aim of research is to find the limit of Amdahl's Law for multicore processors, to make number of cores giving more efficiency to overall architecture of the CMP(Chip Multi
Processor a.k.a. Multicore Processor). As it is expected this limit will be in the architecture of Multicore Processor, or in the programming. We surveyed the architecture of the Multicore
processors of various chip manufacturers namely INTEL™, AMD™, IBM™ etc., and the various techniques there followed in, for improving the performance of the Multicore
Processors. We conducted cluster experiments to find this limit. In this paper we propose an alternate design of Multicore processor based on the results of our cluster experiment.
Affect of parallel computing on multicore processorscsandit
Our main aim of research is to find the limit of Amdahl's Law for multicore processors, to make
number of cores giving more efficiency to overall architecture of the CMP(Chip Multi
Processor a.k.a. Multicore Processor). As it is expected this limit will be in the architecture of
Multicore Processor, or in the programming. We surveyed the architecture of the Multicore
processors of various chip manufacturers namely INTEL™, AMD™, IBM™ etc., and the
various techniques there followed in, for improving the performance of the Multicore
Processors.
We conducted cluster experiments to find this limit. In this paper we propose an alternate design
of Multicore processor based on the results of our cluster experiment.
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxfaithxdunce63732
CS 301 Computer Architecture
Student # 1
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Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
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1. Introduction
High-performance processor design has recently taken two distinct approaches. One approach is to increase the execution rate by increasing the clock frequency of the processor or by reducing the execution latency of the operations. While this approach is important, much of its performance gain comes as a consequence of circuit and layout improvements and is beyond the scope of this research. The other approach is to directly exploit the instruction-level parallelism (ILP) in the program and to issue and execute multiple operations concurrently. This approach requires both compiler and microarchitecture support.
Traditional processor designs that issue and execute at most one operation per cycle are often called scalar designs. Static and dynamic scheduling techniques have been used to achieve better-than scalar performance by issuing and executing more than one operation per cycle. While Johnson[7] defines a superscalar processor as a design that achieves better-than scalar performance, popular usage of this term refers exclusively to those processors that use dynamic scheduling techniques. For clarity, we use instruction-level parallel processors to refer to the general class of processors that execute more than one operation per cycle of the computer both at the personal level, or the level of a small network of computers to do not require more of these types.
The primary static scheduling technique uses the compiler to determine sets of operations that have their source operands ready and have no dependencies within the set. These operations can then be scheduled within the same instruction subject only to hardware resource limits. Since each of the operations in an instruction is guaranteed by the compiler to be independent, the hardware is able to is- sue and execute these operations directly with no dynamic analysis. These multi-operation instructions are very long in comparison with traditional single-operation instructions and processors using .
Concurrent Matrix Multiplication on Multi-core ProcessorsCSCJournals
With the advent of multi-cores every processor has built-in parallel computational power and that can only be fully utilized only if the program in execution is written accordingly. This study is a part of an on-going research for designing of a new parallel programming model for multi-core architectures. In this paper we have presented a simple, highly efficient and scalable implementation of a common matrix multiplication algorithm using a newly developed parallel programming model SPC3 PM for general purpose multi-core processors. From our study it is found that matrix multiplication done concurrently on multi-cores using SPC3 PM requires much less execution time than that required using the present standard parallel programming environments like OpenMP. Our approach also shows scalability, better and uniform speedup and better utilization of available cores than that the algorithm written using standard OpenMP or similar parallel programming tools. We have tested our approach for up to 24 cores with different matrices size varying from 100 x 100 to 10000 x 10000 elements. And for all these tests our proposed approach has shown much improved performance and scalability
SPEED-UP IMPROVEMENT USING PARALLEL APPROACH IN IMAGE STEGANOGRAPHY cscpconf
This paper presents a parallel approach to improve the time complexity problem associated with sequential algorithms. An image steganography algorithm in transform domain is considered for implementation. Image steganography is a technique to hide secret message in an image. With the parallel implementation, large message can be hidden in large image since it does not take much processing time. It is implemented on GPU systems. Parallel programming is done using OpenCL in CUDA cores from NVIDIA. The speed-up improvement
obtained is very good with reasonably good output signal quality, when large amount of data is processed
Reconfiguration Strategies for Online Hardware Multitasking in Embedded SystemsCSEIJJournal
An intensive use of reconfigurable hardware is expected in future embedded systems. This means that the
system has to decide which tasks are more suitable for hardware execution. In order to make an efficient
use of the FPGA it is convenient to choose one that allows hardware multitasking, which is implemented by
using partial dynamic reconfiguration. One of the challenges for hardware multitasking in embedded
systems is the online management of the only reconfiguration port of present FPGA devices. This paper
presents different online reconfiguration scheduling strategies which assign the reconfiguration interface
resource using different criteria: workload distribution or task’ deadline. The online scheduling strategies
presented take efficient and fast decisions based on the information available at each moment. Experiments
have been made in order to analyze the performance and convenience of these reconfiguration strategies.
An Adaptive Load Balancing Middleware for Distributed SimulationGabriele D'Angelo
The simulation is useful to support the design and performance evaluation of complex systems, possibly composed by a massive number of interacting entities. For this reason, the simulation of such systems may need aggregate computation and memory resources obtained by clusters of parallel and distributed execution units. Shared computer clusters composed of available Commercial-Off-the-Shelf hardware are preferable to dedicated systems, mainly for cost reasons. The performance of distributed simulations is influenced by the heterogeneity of execution units and by their respective CPU load in background. Adaptive load balancing mechanisms could improve the resources utilization and the simulation process execution, by dynamically tuning the simulation load with an eye to the synchronization and communication overheads reduction. In this work it will be presented the GAIA+ framework: a new load balancing mechanism for distributed simulation. The framework has been evaluated by performing testbed simulations of a wireless ad hoc network model. Results confirm the effectiveness of the proposed solutions.
Softmax function is an integral part of object detection frameworks based on most deep or shallow neural
networks. While the configuration of different operation layers in a neural network can be quite different,
softmax operation is fixed. With the recent advances in object detection approaches, especially with the
introduction of highly accurate convolutional neural networks, researchers and developers have suggested
different hardware architectures to speed up the overall operation of these compute-intensive algorithms.
Xilinx, one of the leading FPGA vendors, has recently introduced a deep neural network development kit for
exactly this purpose. However, due to the complex nature of softmax arithmetic hardware involving
exponential function, this functionality is only available for bigger devices. For smaller devices, this operation is
bound to be implemented in software. In this paper, a light-weight hardware implementation of this function
has been proposed which does not require too many logic resources when implemented on an FPGA device.
The proposed design is based on the analysis of the statistical properties of a custom convolutional neural
network when used for classification on a standard dataset i.e. CIFAR-10. Specifically, instead of using a brute
force approach to design a generic full precision arithmetic circuit for SoftMax function using real numbers, an
approximate integer-only design has been suggested for the limited range of operands encountered in realworld
scenario. The approximate circuit uses fewer logic resources since it involves computing only a few
iterations of the series expansion of exponential function. However, despite using fewer iterations, the function
has been shown to work as good as the full precision circuit for classification and leads to only minimal error
being introduced in the associated probabilities. The circuit has been synthesized using Hardware Description
Language (HDL) Coder and Vision HDL toolboxes in Simulink® by Mathworks® which provide higher level
abstraction of image processing and machine learning algorithms for quick deployment on a variety of target
hardware. The final design has been implemented on a Xilinx FPGA development board i.e. Zedboard which
contains the necessary hardware components such as USB, Ethernet and HDMI interfaces etc. to implement a
fully working system capable of processing a machine learning application in real-time.
Simulation assisted elicitation and validation of behavioral specifications f...Daniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Collaborative development and cataloguing of simulation and calculation model...Daniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
A package system for maintaining large model distributions in vle softwareDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
A collaborative environment for urban landscape simulationDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
System model optimization through functional models execution methodology and...Daniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Validation of Service Oriented Computing DEVS Simulation ModelsDaniele Gianni
Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
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Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
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Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
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Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
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Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
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Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
(held within the SCS/IEEE Symposium on Theory of Modeling and Simulation part of SpringSim 2012)
Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
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Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
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Presentation at the 2nd International Workshop on Model-driven Approaches for Simulation Engineering
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Please see: http://www.sel.uniroma2.it/mod4sim12/ for further details
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Please visit
https://sites.google.com/site/simulationarchitecture/
for further information
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Calibration of Deployment Simulation Models - A Multi-Paradigm Modelling Approach
1. Karel de Grote-Hogeschool
TERA-Labs
www.kdg.be
Universiteit Antwerpen
ANSYMO
www.ua.ac.be
Calibration of Deployment
Simulation Models
A Multi-Paradigm Modelling Approach
Joachim Denil
Hans Vangheluwe
Paul De Meulenaere
Serge Demeyer
2. Introduction
• Problem Statement
– MDE has advantages
– Simulation is used often
• For example: early deployment space
exploration
www.teralabs.org
2
http://Ansymo.ua.ac.be
3. m of user static scheduling policy is defined here.current */ }
software. However, in the E.g. RMA version of SystemC (2.0),
1600 processor. Due to the structure of the problem, dynamic or
e_policy(vector<rt_task*> &tasks,sc_time %t) we propose in this
this feature is still missing [3]. Therefore,
preemptive scheduling does not lead to better results. So, since
of user online scheduling policy is defined here. E.g. EDF */ } extension to work on
paper the scheduling simulation capability
this robot is not a highly safe-critical application, event driven
SystemC models aiming to extend of its usage for real-timeis considered as the most feasible strategy in this
Examples
8.scheduling assessment.Port basic approach of [7] is mapped to
Re-scheduling by The Binding scheduling
case. One comes up to this result from high-level analysis of
SystemC by extending the scope considerably to this embedded information system. allow for a
Flow to Experiment Results scheduling simulation into the
complete integration of HW/SW
ionembedded system co-design flow. proposed
demonstrates the feasibility of the Table 1. Simulation Performance Results
embedded systems design by means of an BCET ACET WCET
ample. Simulation Framework Overview
3. As an example we exploit an autonomous Time triggered 540 ms 540 ms 540 ms
d with ultrasound distance sensors, lev camera, and
sy s t e m
a el Event Driven 331 ms 357 ms 431 ms
ta link subsystem, where its entire specification
S y st e m C Priority-based Ordering 335 ms 361 ms 435 ms
m odel
17 tasks is captured os a task graph along with a n d Preemptive Scheduling
e v e nts
335 ms 361 ms 435 ms
HW Model
properties (estimated max-min execution times). d a t a re ce pt io n
6. Conclusions and Future Work
ow starts with the allocated specification model.g in g a n d p re s e n t a t io n
lo g
m design,che d ule a s A dd -In
u s e r s the functional specification is then
s che du ling In this paper, a SystemC based scheduling simulator along
lo g f ile s
s im u lat ion e ng ine
nto multiple processing elements (PEs). In this with its integrated environment is presented. It provides a
envisaged generic hardware architecture for the G U I framework for assessing scheduling algorithms options, while
s t a t ic o ff-lin e
a lg o rit h m
s e ctio n
ocessing of this robot is a multi-processor system the bulk of the design is modeled in SystemC at a high
d y n a m ic u t abstraction level. It is thus possible to exercise both hardware
m a set of Pes,lgi.e.,ma co-processornon e PCI FPGA csotmralaeif
a o rit h
o -lin
a o g
nd a microcontroller attached tose ctio n the mobile robot. and real-time software modules of system-level allowing early
e rro r
municate throughn a PCI bus (between PC and system performance assessment as well as verification and
in je c t io
a a set of wirelessf oRS232 modems (between rC ult analys is validation of different implementation alternatives and
a lg o rit h m r es
bot and PC). r in je c t io nto the inherently sequential
e rro
Due scheduling strategies. Application scenarios for modeling
PE, tasks mappedProposed Simulationto be
Figure 1. to the same PE need Framework distributed system is a challenging subject for future work in
then scheduled statically orKlaus, andIn case Huss; Anto extend theSystemC framework for real-
TheHastono, S. dynamically. S. integrates functional
P. proposed simulation framework A. order integrated simulation methodology for global
scheduling scheduling assessments is system on
time implementation, scheduler on scheduling analysis.
c validation with architectural aand scheduling explorationlevel; in Proceedings of IEEE Int. Real-
re in the proposed framework isengine along with software code
system level. The simulation a customizable
Time Systems Symposium, 2004. 7. References
scheduling simulator module. [1] C. M. Harmonosky, Simulation-Based Real-Time Scheduling:
e process of generating SystemC models of the Review of Recent Developments, In Proc. of the 1995 Winter
ormation processing of the robot is based on
www.teralabs.org the Simulation Conference, December 1995. 3
odel of the specification. This generated model
http://Ansymo.ua.ac.be [2] SystemC, http://www.systemc.org.
4. Examples
S. Becker, H. Koziolek, and R. Reussner; The Palladio component model for
model-driven performance prediction, Journal of Systems and Software, vol.
82, no. 1, pp. 3-22, Jan. 2009.
www.teralabs.org
4
http://Ansymo.ua.ac.be
5. Examples
J. Denil, H. Vangheluwe, P. Ramaekers, P. De Meulenaere, and S. Demeyer;
DEVS for AUTOSAR platform modelling; in Proceedings of the 2011 SpringSim
Multi-Conference: DEVS/TMS, 2011.
www.teralabs.org
5
http://Ansymo.ua.ac.be
6. Introduction
• Problem Statement
– MDE has advantages
– Simulation is used often
– PROBLEM: Calibration of simulation
models
• Solution:
– Use MDE techniques (generative) to
calibrate models
www.teralabs.org
6
http://Ansymo.ua.ac.be
7. Calibration?
• Estimate model parameters to reflect
reality
• For example:
– Physical model: Gain of a motor
– Queuing system: Distribution of arrival
times
– In Previous examples:
• WCET
• Distribution of Execution Times
www.teralabs.org
7
http://Ansymo.ua.ac.be
8. Calibration?
• State of Art:
– Instrument Source Code
– Make test programs (trace driven)
– Execute on Target or Cycle-true
Simulator
• Cyber-Physical Systems:
– Input not only from environment but
also from feedback!
www.teralabs.org
8
http://Ansymo.ua.ac.be
10. windowPos
<
CInitAngularVelocity CInitPositionWindow
0.0 100.0
motorSignal
MPM Design of+ the Power Window
goingUp
SWC windowPos
CAtTop joinedUpDown
AngularVelocity FAV
Control_Passenger X
+
m
0.0
goingDown
AtTop
MotorGain <
motorSignal AngularVelocity
SWC 0.0
UP
>
SWC 50.0
Logic SWC +
Multi-Paradigm Modelling (MPM):
Control_Driver 1.0
friction >
DC_Motor
PsgrButtons AtBottom
CAtBottom
DOWN Cfriction
X
0.0 10.0
UP
“Model Everything
invFriction
windowPos
DriverButtons TopOrBottom
SWC
ObjectIn
at the right level(s) of abstraction,
DOWN FeedBack
Sensor_Load
motorSignal + + =
DrvChildLock ObjectDetected
Controller
using (an) appropriate formalism(s)”
noObject
0.0
DrvIgnition
ToMotor
PsgrButton
ForceDetect
ObjectInWindow
www.teralabs.org
10
http://Ansymo.ua.ac.be
11. Problem Revisited
SWC
Control_Passenger
SWC
SWC
Logic SWC
Control_Driver
DC_Motor
Deploy
SWC
Sensor_Load
DrvDoor BodyLogic PsgDoor
MPC5567 MPC5567 MPC5567
Performance
Characteristics
Body
CAN
www.teralabs.org
11
http://Ansymo.ua.ac.be
12. Architecture
• Use target hardware for SW
• Use host for simulation
Input Values and Triggers
Output Values and Traces
Host Target Platform
www.teralabs.org
12
http://Ansymo.ua.ac.be
25. Figure 7. The combined model using generic links to conn
invFriction
TopOrBottom
Results
= +
FeedBack
our generated infrastructure match the values obtained by th
noObject
ObjectDetected
hardware instrumentation.
Execution Time (µs) Childlock Off ChildLock On
SWC
SWC
Logic
Control_Passenger
SWC
DC_Motor
20.375 12500 12000
19.875 2500 3000
SWC
SWC
Table 1. Results for the Control Driver runnable.
SWC
Logic
Control_Driver
DC_Motor
Execution Time (µs) Childlock Off ChildLock On
SWC
Sensor_Load
11.375 9000 10000
10.875 6000 5000
ities in the different formalisms.
Table 2. Results for the Control Passenger.
Execution Time (µs) Childlock Off ChildLock On
Execution Time (µs) Childlock Off ChildLock On
20.000 7500 4999
7.625 15000 15000
20.500 0 10001
Table 3. Results for the Sensor Load runnable.
20.875 7499 0
21.375 1 0 The obtained values from the different runnables can b
DrvDoor
Table 4. Results for the Logic runnable. The strange result MPC5567
used as input parameters for the system performance simula
f the last row is because of a special condition thattion models.
Validated using hardware measurements! only can
ccur in the first execution round.
Execution Time (µs) Childlock Off
www.teralabs.org ChildLock On
6. DISCUSSION
http://Ansymo.ua.ac.be On the tooling side of this approach a problem25 occu
can
8.00 6000 3000
26. Discussion
• Tooling: Combining different
formalisms?
– Super-meta-model
• More HW platforms, other
performance measure?
– Use other template
• Limitation:
– Caching, pipelines, …
www.teralabs.org
26
http://Ansymo.ua.ac.be
27. Conclusion
• Problem Statement
– Calibration of simulation models
• Solution:
– Use MDE techniques (generative) to
calibrate models
www.teralabs.org
27
http://Ansymo.ua.ac.be