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Removing Uninteresting Bytes in Software FuzzingAftab Hussain
Imagine a world where software fuzzing, the process of mutating bytes in test seeds to uncover hidden and erroneous program behaviors, becomes faster and more effective. A lot depends on the initial seeds, which can significantly dictate the trajectory of a fuzzing campaign, particularly in terms of how long it takes to uncover interesting behaviour in your code. We introduce DIAR, a technique designed to speedup fuzzing campaigns by pinpointing and eliminating those uninteresting bytes in the seeds. Picture this: instead of wasting valuable resources on meaningless mutations in large, bloated seeds, DIAR removes the unnecessary bytes, streamlining the entire process.
In this work, we equipped AFL, a popular fuzzer, with DIAR and examined two critical Linux libraries -- Libxml's xmllint, a tool for parsing xml documents, and Binutil's readelf, an essential debugging and security analysis command-line tool used to display detailed information about ELF (Executable and Linkable Format). Our preliminary results show that AFL+DIAR does not only discover new paths more quickly but also achieves higher coverage overall. This work thus showcases how starting with lean and optimized seeds can lead to faster, more comprehensive fuzzing campaigns -- and DIAR helps you find such seeds.
- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
1. Device Modeling Report
COMPONENTS: DARLINGTON TRANSISTOR
PART NUMBER: 2SD986
MANUFACTURER: NEC CORPORATION
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004
2. BIPOLAR JUNCTION TRANSISTOR MODEL
PSpice
model Model description
parameter
IS Saturation Current
BF Ideal Maximum Forward Beta
NF Forward Current Emission Coefficient
VAF Forward Early Voltage
IKF Forward Beta Roll-off Knee Current
ISE Non-ideal Base-Emitter Diode Saturation Current
NE Non-ideal Base-Emitter Diode Emission Coefficient
BR Ideal Maximum Reverse Beta
NR Reverse Emission Coefficient
VAR Reverse Early Voltage
IKR Reverse Beta Roll-off Knee Current
RE Emitter Resistance
RB Base Resistance
RC Series Collector Resistance
CJE Zero-bias Emitter-Base Junction Capacitance
VJE Emitter-Base Junction Potential
MJE Emitter-Base Junction Grading Coefficient
CJC Zero-bias Collector-Base Junction Capacitance
VJC Collector-base Junction Potential
MJC Collector-base Junction Grading Coefficient
TF Forward Transit Time
TR Reverse Transit Time
XTB Forward Beta Temperature Coefficient
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004
3. DIODE MODEL
PSpice model
Model description
parameter
IS Saturation Current
RS Series Resistance
CJO Zero-bias Junction Capacitance
BV Reverse Breakdown Voltage(a positive value)
IBV Reverse Breakdown Current(a positive value)
TT Transit Time
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004
4. Ic-hFE Characteristics
Simulation result
Evaluation Circuit
V2
0Vdc
Simulation
U1 2(C)
V3
3(B)
0Vdc
R1 R2
V1
Q2SD986 1(E) 2Vdc
I1
0.15Adc
0
Peak of hFE Measurement Simulation % Error
IC(A) 1 1.0489 -4.890
hFE 10 10.489 k -4.890
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004
5. Vce(sat) Voltage & Vbe(sat) Voltage Characteristics
Simulation result
Evaluation Circuit
U1 2(C)
3(B)
R1 R2
Vbe(sat) Voltage/Simulation
I2
Q2SD986 1(E) 1Adc
Vce(sat) Voltage/Simulation
I1
1mAdc
0
Measurement Simulation % Error
Vce(sat) 0.8 V 0.798 V 0.25
Vbe(sat) 1.25 V 1.23 V 1.6
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004
6. Output Characteristics
Simulation result
Ib=200u Ib=180u Ib=160u
u u u Ib=140u
u
Ib=120u
u
Ib=100u
Evaluation Circuit
U1 2(C)
3(B)
R1 R2
V1
Q2SD986 1(E) 5Vdc
I1
220uAdc
0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2004