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2004 Product Guide

Alliance Semiconductor's clock and timing products include EMI reduction devices, zero delay buffers (ZDB), and frequency multipliers. The portfolio addresses requirements for various applications including PCs, displays, memory modules, consumer devices, networking, and wireless. The products are available in industrial, automotive, and commercial temperature ranges and various package options.

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DISCLAIMER Alliance Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an Alliance Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Alliance Semiconductor Corporation. LIFE SUPPORT POLICY Alliance Semiconductor Corporation products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of Alliance Semiconductor. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Copyright 2004. All rights reserved NTD™ is a trademark of Alliance Semiconductor Corporation. HyperTransport™ is a trademark of the HyperTransport Technology Consortium.
Table of Contents ANALOG AND MIXED SIGNAL PRODUCTS ................................................................................ 3 ANALOG AND MIXED SIGNAL PRODUCTS ......................................................................................... 4 CLOCK AND TIMING PRODUCTS ...................................................................................................... 5 Clock and Timing Product Selector Guide Alpha-Numeric Listing.......................................... 6 Clock and Timing Product Selector Guide Function and Configuration Listing ...................... 9 Zero Delay Buffers (ZDB) and Specialty Clock Management Cross Reference Guide........ 12 EMI Reduction Products Cross Reference Guide................................................................. 13 POWER AND SYSTEMS MANAGEMENT PRODUCTS .......................................................................... 14 CPU Supervisor Product Selector Guide .............................................................................. 15 CPU Supervisor Cross Reference Guide.............................................................................. 22 SYSTEM SOLUTIONS PRODUCTS............................................................................................. 27 CONNECTIVITY ............................................................................................................................. 29 HyperTransport™ Bridges Product Selector Guide .............................................................. 29 AS90L10204 HyperTransport™-to-PCI/PCI-X Bridge .......................................................... 30 AS90L10208 HyperTransport™-to-PCI/PCI-X Bridge .......................................................... 31 JTAG Controllers Product Selector Guide ............................................................................ 32 AS91L1001 JTAG Test Controller......................................................................................... 33 AS91L1002 JTAG Test Sequencer....................................................................................... 34 AS91L1003U 3-Port JTAG Gateway..................................................................................... 35 AS91L1006BU 6-Port JTAG Gateway .................................................................................. 36 NETWORKING .............................................................................................................................. 37 RPR Controllers Product Selector Guide.............................................................................. 37 AS95L210x Family of Resilient Packet Ring Controllers ...................................................... 38 MEMORY PRODUCTS.................................................................................................................. 43 SRAM PRODUCTS ....................................................................................................................... 44 Synchronous SRAM .............................................................................................................. 45 Asynchronous SRAM ............................................................................................................ 49 Synchronous SRAM Cross Reference Guide ....................................................................... 51 Fast Asynchronous SRAM Cross Reference Guide ............................................................. 56 Synchronous Dual Port SRAM Cross Reference Guide ....................................................... 58 www.alsc.com Product Guide 2004 1 Notice: The information in this document is subject to change without notice.
2 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
ANALOG AND MIXED SIGNAL PRODUCTS www.alsc.com Product Guide 2004 3 Notice: The information in this document is subject to change without notice.
Analog and Mixed Signal Products Alliance Semiconductor is a worldwide supplier of Analog and Mixed Signal Products in two main categories: Power and Systems Management, and Clock and Timing. • The Power and Systems Management Portfolio includes CPU Supervisor Products. These include products that feature POR (Power On Reset), WDT (Watch Dog Timers), LVS (Low Voltage Sense), BB (Battery Backup), brownout detect and control, and many more system and device level key functions. • The Clock and Timing Portfolio includes Frequency Synthesizers and Generators, Multipliers, Zero Delay Buffers, Distribution and Fan-out buffers. The EMI Reduction family of devices, a sub-segment of Clock and Timing, are made up of Frequency Synthesizer and Generators which are widely used in many designs today to reduce radiated emissions towards regulatory compliance. The EMI reduction family is noted for low cost, very low power consumption, very small package size options, and overall timing accuracy and performance. Fabricated in Low Voltage CMOS technologies, the Analog and Mixed Signal Product portfolio offers a full range of coverage, functions, options, and configurations, that provide flexibility in design and low cost. Power-On Reset PD MOD LF (ext loop filter) Application XIN/CLKIN Xtal Freq VDD OSC Divide XOUT PD Filter VCO DIV FBK uP Divider MOD_OUT ASM 809 RESET EMI Clock Synthesizer REF_OUT GND GND 4 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Clock and Timing Products Alliance Semiconductor provides in-depth coverage and support in Clock Management with cost effective, low power, Clock and Timing solutions that cater to the requirements for PC/Data processing applications and handhelds, high resolution LCD displays, DDR memory modules, consumer applications (MP3 players/recorders, games, etc.), networking, wireless, mobile applications and others. The Clock Management Solution family encompasses Clock and Frequency Generators, Frequency Multipliers, Zero Delay Buffers, and specific specialty solutions. High precision frequency multipliers provide 2x or 4x outputs of the input frequency up to 312 MHz, with higher frequencies to be offered in the near future. The depth of modulation, the profile (sinusoidal, triangular, non-linear), type of modulation and direction (center or down) are selectable from these Clock and Timing products. In addition, both modulated and unmodulated outputs are available. Many of the devices (single, dual and triple PLL based designs) feature a selection of output frequency derived from the input reference, along with the depth of modulation, type of modulation profile, and frequency of modulation through programming via I2C. A broad family of Zero Delay Buffers (ZDB) provide multiple low skew outputs of an input clock suitable for clock distribution applications, such as clocks to multiple PCI slots in a PC motherboard or SDRAM bank clocks. Available in 1:5 and 1:9 configurations with internal feedback or 1:4 and 1:8 configurations with external feedback, these Zero Delay Buffers provide relative skew among various outputs under controlled load conditions. Various drive options are also available to support one or two 50-ohm transmission lines. Clock and Timing products are designed to work with 2.5V, 3.3V, and 5V applications. Clock and Timing devices are found in applications such as workstations, servers, RAID arrays, notebook PCs, LCD high-resolution displays, PDA and hand held devices, automotive electronics, battery-driven entertainment systems, and others. www.alsc.com Product Guide 2004 5 Notice: The information in this document is subject to change without notice.
Clock and Timing Product Selector Guide Alpha-Numeric Listing Industrial Automotive Other PKG Part Number SOIC TSSOP Product Description (-40°C to +85°C) (-40°C to +125°C) options AS80M2180 YES - YES YES - EMI REDUCTION ASM3P1819N YES - YES YES - EMI REDUCTION ASM3P2180A-D YES - YES YES - EMI REDUCTION ASM3P2182A-D YES - YES YES - EMI REDUCTION ASM3P2183A-D YES - YES YES - EMI REDUCTION ASM3P2184A-D YES - YES YES - EMI REDUCTION ASM3P2185A-D YES - YES YES - EMI REDUCTION Very Low Power EMI ASM3P2779A YES - YES YES 6 TSOT23 REDUCTION ASM3P2811A YES - YES YES - EMI REDUCTION ASM3P2812A YES - YES YES - EMI REDUCTION ASM3P2814A YES - YES YES - EMI REDUCTION ASM3P2821B YES - YES YES - EMI REDUCTION ASM3P5821A YES - YES YES - EMI REDUCTION ASM3X2105A YES YES YES YES - EMI REDUCTION DDR I REGISTER - ASM4SSTVF16857 Extended Commercial* - - YES TVSOP PLANAR DDR I REGISTER - ASM4SSTVF16859 Extended Commercial* - - YES MLF TVSOP STACKED DDR I REGISTER - ASM4SSTVF32852 Extended Commercial* - - - LFBGA STACKED ASM5CVF857 Extended Commercial* - - YES MLF/BGA DDR I (to DDR 400) ZDB ASM5P2304A-1 YES - YES YES - ZDB 15-133 MHz ASM5P2304A-1H YES - YES YES - ZDB 15-133 MHz ASM5P2304A-2 YES - YES YES - ZDB 15-133 MHz ASM5P2304A-2H YES - YES YES - ZDB 15-133 MHz ASM5P2304A-5H YES - YES YES - ZDB 15-133 MHz ASM5P2304B-1 YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2304B-1H YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2304B-2 YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2304B-2H YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2305A-1 YES - YES YES - ZDB 15-133 MHz All products are available in Commercial (0°C to +70°C). * Extended Commercial = 0°C to +85°C 6 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Clock and Timing Product Selector Guide Alpha-Numeric Listing Industrial Automotive Other PKG Part Number SOIC TSSOP Product Description (-40°C to +85°C) (-40°C to +125°C) options ASM5P2305A-1H YES - YES YES - ZDB 15-133 MHz ASM5P2308A-1 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-1H YES - YES YES - ZDB 15-133 MHz ASM5P2308A-2 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-3 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-4 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-5H YES - YES YES - ZDB 15-133 MHz ASM5P2309A-1 YES - YES YES - ZDB 15-133 MHz ASM5P2309A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-2 YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-2H YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-5H YES - YES YES - ZDB 15-133 MHz ASM5P23S05A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S05A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-2 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-3 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-4 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-5H YES - YES YES - ZDB 15-133 MHz ASM5P23S09A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S09A-1H YES - YES YES - ZDB 15-133 MHz L2042A YES - YES YES - EMI REDUCTION (Low Voltage) P1707A YES - YES YES - EMI REDUCTION P1708C YES - YES YES - EMI REDUCTION P1817A-B YES - YES YES - EMI REDUCTION P1819A-B YES - YES YES - EMI REDUCTION All products are available in Commercial (0°C to +70°C). www.alsc.com Product Guide 2004 7 Notice: The information in this document is subject to change without notice.
Clock and Timing Product Selector Guide Alpha-Numeric Listing Industrial Automotive Other PKG Part Number SOIC TSSOP Product Description (-40°C to +85°C) (-40°C to +125°C) options P2005A YES YES YES YES - EMI REDUCTION P2005S YES YES YES YES - EMI REDUCTION P2008A YES - YES YES - EMI REDUCTION P2010A YES YES YES YES - EMI REDUCTION P2027A YES - YES YES - EMI REDUCTION P2040A YES - YES YES - EMI REDUCTION P2040C YES - YES YES - EMI REDUCTION P2041A YES - YES YES - EMI REDUCTION P2042A YES - YES YES - EMI REDUCTION P2082A YES - YES YES - FREQUENCY MULTIPLIER P2084A YES - YES YES - FREQUENCY MULTIPLIER P2160A YES - YES YES - EMI REDUCTION P2681A YES - YES YES - EMI REDUCTION P2779A YES - YES YES - EMI REDUCTION P2781A YES - YES YES - EMI REDUCTION P2782A YES - YES YES - EMI REDUCTION P2784A YES - YES YES - EMI REDUCTION P2811A YES - YES YES - EMI REDUCTION P2812A YES - YES YES - EMI REDUCTION P2814A YES - YES YES - EMI REDUCTION All products are available in Commercial (0°C to +70°C). 8 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Clock and Timing Product Selector Guide Function and Configuration Listing Frequency Output Fout_MAX Reference ModOut Xtal Supply Part Number Range (Fin) in Frequency Package in MHz Output Scaling Osc Voltage MHz Deviation (%) Input Frequency Range 6 MHz to 210 MHz 8 SOIC AS80M2180 6-30 30 -1.25% or 4.0% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P1819N 20-40 40 -1.25% YES 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2180A-D 6-36 36 +/-0.625 to -3.5% - 1X - 3.0 to 3.6 8 TSSOP +/-0.13 to 8 SOIC ASM3P2182A-D 25-210 210 - 1X - 3.0 to 3.6 +/-1.24% 8 TSSOP 8 SOIC ASM3P2183A-D 6-103 103 +/-0.625 to -3.6% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2184A-D 10-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP +/-0.625 to 8 SOIC ASM3P2185A-D 25-50 50 - 1X - 3.0 to 3.6 -1.25% 8 TSSOP 8 SOIC ASM3P2779A 15-30 38 +/-1% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2811A 10-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2812A 10-40 80 +/-0.625 to -3.5% - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2814A 10-40 160 +/-0.625 to -3.5% - 4X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2821B 15-27 27 -2.5% YES 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P5821A 20-40 34 -1.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3X2105A 6-10 10 +/-1% - 1X, ½X YES 3.0 to 3.6 8 TSSOP +/-1.25 to 8 SOIC P1817A-B 10-32 32 YES 1X YES 3.0 to 3.6 +/-1.50% 8 TSSOP 8 SOIC P1819A-B 20-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2005A 8-32 32 +/-1.0 to +/-3.0% - 1X, ½X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2005S 8-32 32 +/-0.6 to +/-1.8% - 1X, ½X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2008A 4-32 32 +/-0.8 to +/-3.2% YES 1X, ½X YES 2.9 to 5.5 8 TSSOP +/-1.25 to 8 SOIC P2010A 10-35 35 - 1X YES 3.0 to 3.6 +/-2.5% 8 TSSOP 8 SOIC P2027A 10-30 30 +/-0.2 to +/-0.6% - 1X YES 3.0 to 3.8 8 TSSOP +/-0.50 to 8 SOIC P2041A 25-60 60 - 1X - 2.7 to 5.5 +/-2.50% 8 TSSOP 8 SOIC P2681A 6-20 20 +/-0.4 to +/-5% - 1X, ½X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2811A-B 10-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2812A-B 10-40 80 +/-0.625 to -3.5% - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2814A-B 10-40 160 +/-0.625 to -3.5% - 4X YES 3.0 to 3.6 8 TSSOP Input Frequency Range 30 MHz to 175 MHz +/-0.50 to 2.25 to 8 SOIC L2042A 30-75 75 - 1X - +/-2.00% 3.7 8 TSSOP +/-0.25 to 8 SOIC P1708C 60-175 175 - 1X - 3.0 to 3.6 +/-2.00% 8 TSSOP www.alsc.com Product Guide 2004 9 Notice: The information in this document is subject to change without notice.
Clock and Timing Product Selector Guide Function and Configuration Listing Frequency Output Fout_MAX Reference ModOut Xtal Supply Part Number Range (Fin) in Frequency Package in MHz Output Scaling Osc Voltage MHz Deviation (%) Input Frequency Range 30 MHz to 175 MHz (Continued) 8 SOIC P2040A 30-110 110 +/-0.7 to +/-2.0% - 1X - 3.0 to 3.6 8 TSSOP +/-0.20 to 8 SOIC P2042A 30-110 110 - 1X - 3.0 to 3.6 +/-2.00% 8 TSSOP Wide Input Frequency Range Devices +/-0.5 to 8 SOIC P1707A 60-175 175 - 1X - 3.0 to 3.6 +/-2.50% 8 TSSOP 8 SOIC P2040C 50-175 175 +/-0.4 to +/-2.2% - 1X - 3.0 to 3.6 8 TSSOP +/-0.50 to 8 SOIC P2160A 40-166 166 - 1X - 3.0 to 3.6 +/-1.00% 8 TSSOP 8 SOIC P2781A-B 3-78 78 +/-0.25 to +/-5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2782A-B 3-78 156 +/-0.25 to +/-5% - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2784A-B 3-78 312 +/-0.25 to +/-5% - 4X YES 3.0 to 3.6 8 TSSOP High Precision Frequency Multipliers 8 SOIC P2082A 3-78 156 - - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2084A 3-78 312 - - 4X YES 3.0 to 3.6 8 TSSOP Specialty Clock Management DDR 1 JEDEC 48 TSSOP ASM4SSTVF16857 Compliant 14-bit 250 - - - - 2.3 to 2.7 TVSOP Register - Planar DDR 1 JEDEC 64 TSSOP ASM4SSTVF16859 Compliant 13/26-bit 250 - - - - 2.3 to 2.7 56 MLF Register - Stacked DDR 1 JEDEC 114 ASM4SSTVF32852 Compliant 14/28-bit 250 - - - - 2.3 to 2.7 LFBGA Register - Stacked DDR 1 – DDR 333 48 TSSOP – DDR 400 ASM5CVF857 250 -0.5% YES 1X - 2.3 to 2.7 40 MLF JEDEC Compliant 56 BGA ZDB Zero Delay Buffers 8 SOIC ASM5P2304A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P2304A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304A-2 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304A-2H 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 8 SOIC ASM5P2304B-1 4-25 25 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P2304B-1H 4-25 25 - - 1X - 3.0 to 3.6 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304B-2 4-25 50 - - - 3.0 to 3.6 ½X 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304B-2H 4-25 50 - - - 3.0 to 3.6 ½X 8 TSSOP 10 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Clock and Timing Product Selector Guide Function and Configuration Listing Frequency Output Fout_MAX Reference ModOut Xtal Supply Part Number Range (Fin) in Frequency Package in MHz Output Scaling Osc Voltage MHz Deviation (%) 8 SOIC ASM5P2305A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P2305A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 16 SOIC ASM5P2308A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2308A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 1X, 2X, 16 SOIC ASM5P2308A-2 15-133 133 - - - 3.0 to 3.6 ½X 16 TSSOP 16 SOIC ASM5P2308A-3** 15-133 133 - - 2X, 4X - 3.0 to 3.6 TSSOP 16 SOIC ASM5P2308A-4 15-133 133 - - 2X, 2X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2308A-5H 15-133 133 - - ½X, ½X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2309A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2309A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 8 SOIC ASM5P23S04A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P23S04A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 1X, 2X, 8 SOIC ASM5P23S04A-2 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 1X, 2X, 8 SOIC ASM5P23S04A-2H 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 8 SOIC ASM5P23S04A-5H 15-133 133 - - ½X, ½X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P23S05A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P23S05A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 16 SOIC ASM5P23S08A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S08A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 1X, 2X, 16 SOIC ASM5P23S08A-2 15-133 133 - - - 3.0 to 3.6 ½X 16 TSSOP 16 SOIC ASM5P23S08A-3** 15-133 133 - - 2X, 4X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S08A-4 15-133 133 - - 2X, 2X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S08A-5H 15-133 133 - - ½X, ½X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S09A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S09A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP ** Output phase is indeterminant from INPUT REF. If needed in phase, use the –2 version. www.alsc.com Product Guide 2004 11 Notice: The information in this document is subject to change without notice.
Zero Delay Buffers (ZDB) and Specialty Clock Management Cross Reference Guide Alliance TI Cypress ICS IDT Pericom ASM4SSTVF16857 SN74SSTVF16857 CY2SSTV16857 ICSSSTVF16857 IDT74SSTV16857 PI74SSTVF16857 ASM4SSTVF16859 SN74SSTVF16859 CY2SSTV16859 ICSSSTVF16859 IDT74SSTV16859 PI74SSTVF16859 ASM4SSTVF32582 SN74SSTVF32852 CY2SSTV32852 ICSSSTVF32852 IDT74SSTV32852 PI74SSTVF32852 ASM5PCVF857 CDCVF857 CY2SSTV857-32 ICS95V857 IDTCSPT857C PI6CVF857 ASM5P2304A-1 - CY2304-1 - - - ASM5P2304A-2 - CY2304-2 - - - ASM5P2304B-1 - CY2304-1 - - - ASM5P2304B-2 - CY2304-2 - - - ASM5P2305A-1 - CY2305-1 - IDT2305-1 PI6C2408-1 ASM5P2305A-1H - CY2305-H1 - IDT2305-1H PI6C2408-1H ASM5P2308A-1 - CY2308-1 MK2308S-1 IDT2308-1 PI6C2408-1 ASM5P2308A-1H - CY2308-1H MK2308S-1H IDT2308-1H PI6C2408-1H ASM5P2308A-2 - CY2308-2 - IDT2308-2 PI6C2408-2 ASM5P2308A-3 - CY2308-3 - IDT2308-3 PI6C2408-3 ASM5P2308A-4 - CY2308-4 - IDT2308-4 PI6C2408-4 ASM5P2308A-5H - CY2308-5H - IDT2308-5H - ASM5P2309A-1 - CY2309 - IDT2309 - ASM5P2309A-1H - CY2309-1H - IDT2309-1H - ASM5P23S05A-1 - CY23S05 - IDT23S05 PI6C2405A-1 ASM5P23S05A-1H - CY23S05-1H - IDT23S05-1H PI6C2405A-1H ASM5P23S08A-1 - CY23S08-1 - IDT23S08-1 PI6C2408-1 ASM5P23S08A-1H - CY230S8-1H - IDT23S08-1H PI6C2408-1H ASM5P23S08A-2 - CY23S08-2 - IDT23S08-2 PI6C2408-2 ASM5P23S08A-3 - CY23S08-3 - IDT23S08-3 PI6C2408-3 ASM5P23S08A-4 - CY23S08-4 - IDT23S08-4 PI6C2408-4 ASM5P23S08A-5H - CY23S08-5H - IDT23S08-5H - ASM5P23S09A-1H - CY23S09-1H - IDT23S09-1H PI62409-1H ASM5P23S09A-1 - CY23S09-1 - IDT23S09 PI62409-1 Note: Alliance offers both SOIC & TSSOP, industrial or commercial temperature grades, and STD or lead-free package options for all devices listed. 12 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
EMI Reduction Products Cross Reference Guide Alliance Input Frequency Cypress Output Frequency Mobile Modulation Frequency Selection Part Frequency Selection Graphic Part Number Type (in MHz) Needed Number (in MHz) Needed Frequency AS80M2180 6-30 NO Down, Center W180/180i 8-28 4 ranges 27 MHz Source ASM3P1819N 20-40 NO Down, Center CY25819 20-40 - 27 MHz Source ASM3P2779A 20-38 NO Center - - - 27 MHz Source ASM3P2811A 10-40 2 ranges Down, Center CY25811 10-40 3 ranges - ASM3P2812A 10-40 2 ranges Down, Center CY25812 20-80 3 ranges - ASM3P2814A 10-40 2 ranges Down, Center CY25814 40-160 3 ranges - ASM3P2821B 15-27 NO Down CY25811 4-32 3 ranges - ASM3P5821A 20-40 NO Down CY25811 4-32 3 ranges - LVDS Frequencies 65 MHz (XGA), P1707A 60-175 NO Center SM561 54-166 10 ranges 108 MHz (SXGA), and 162 MHz (UXGA) LVDS Frequencies P1708C 50-110 NO Center SM560 25-108 10 ranges 65 MHz (XGA), 108 MHz (SXGA) P1819A-H 20-40 NO Down, Center CY25819 16-32 4 ranges 27 MHz Source LVDS Frequencies 65 MHz (XGA), P2040C 60-175 NO Center - - - 108 MHz (SXGA), and 162 MHz (UXGA) P2781A 3-78 4 ranges Center FS781 SOIC 6-82 4 ranges 25 MHz Source FS781 P2781B 3-78 4 ranges Center TSSOP 6-82 4 ranges 27 MHz Source P2782A 3-78 4 ranges Center FS782 SOIC 6-66 4 ranges - FS782 P2782B 3-78 4 ranges Center TSSOP 6-66 4 ranges - P2784A 3-78 4 ranges Center FS784 SOIC 6-32 4 ranges - FS784 P2784B 3-78 4 ranges Center TSSOP 6-32 4 ranges - www.alsc.com Product Guide 2004 13 Notice: The information in this document is subject to change without notice.
Power and Systems Management Products CPU Supervisor Products Alliance Semiconductor provides cost effective, low power, Supervisor products that are an essential part of the 5V/3.3V/3V system providing active low and active high reset inputs to microprocessors, microcontrollers, ASICs, ASSPs, and digital systems. These Supervisor products initialize the systems into a known state and avoid malfunctioning of systems during power-up, power-down, power control, and brownout conditions, thus eliminating the possibility of code corruption. The CPU Supervisor Products also feature edge triggered and level triggered manual reset inputs. These enable the users to connect an external contact switch to generate a reset. This typically would be used as an alternative to operator intervention in systems that require reset. An early warning to the system controller about the impending system power failure, provided through the power fail input, enables the saving of essential system parameters. A Watch Dog Timer (WDT) is another useful feature that monitors and restarts a system processor. These are typically used as time out devices to force a system out of software “endless loop”. The reset outputs on the CPU Supervisor Products are available in Open Drain (OD) or Push Pull (PP) configurations to suit the user requirements. Various threshold voltage options are available on the supervisor devices, 4.63V, 4.38V, 4.00V, 3.08V, 2.93V, and 2.63V, which support 5%, 10%, and 20% system voltage tolerances. Reset timeout period options such as 140ms, 300 ms, and 800 ms cater to different system requirements. Dual power supply monitoring is a highly useful feature that is essential in the design of one core supply and IO supply systems. This system architecture is gaining wide acceptance. The CPU and System Supervisor Products are available in industry standard, space saving packages such as SOT-23, SOT-143, SO-8, and Micro SO in commercial and industrial temperature range. Supervisor devices are found in computers, embedded systems, portable and battery operated systems, notebook PCs, cellular phones, safety systems, automotive systems, wireless communication systems, PDAs, printers, set top boxes, intelligent systems and others. 14 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP CPU Supervisors with Selectable Trip-point Tolerance, Watchdog timer with POR ASM1232LP 4.5-5.5 Vt1 T1 - X - X X L X X 8P-DIP ASM1232LPCMA 4.5-5.5 Vt1 T1 - X - X X L X X 8-MicroSO ASM1232LPEMA 4.5-5.5 Vt1 T2 - X - X X L X X 8-MicroSO ASM1232LPN 4.5-5.5 Vt1 T2 - X - X X L X X 8P-DIP ASM1232LPS 4.5-5.5 Vt1 T1 - X - X X L X X 16-SO ASM1232LPS-2 4.5-5.5 Vt1 T1 - X - X X L X X 8-SO ASM1232LPSN 4.5-5.5 Vt1 T2 - X - X X L X X 16-SO ASM1232LPSN-2 4.5-5.5 Vt1 T2 - X - X X L X X 8-SO ASM1832 1.0-5.5 Vt1 T2 - X - X X L - X 8P-DIP ASM1832EMA 1.0-5.5 Vt1 T2 - X - X X L - X 8-MicroSO ASM1832S 1.0-5.5 Vt1 T2 - X - X X L - X 8-SO CPU Supervisors with POR, Edge Triggered MR ASM161JEUS 1.1-5.5 4 T2 - - - X - ↓ X - 4L-SOT143 ASM161LEUS 1.1-5.5 4.63 T2 - - - X - ↓ X - 4L-SOT143 ASM161MEUS 1.1-5.5 4.38 T2 - - - X - ↓ X - 4L-SOT143 ASM161REUS 1.1-5.5 2.63 T2 - - - X - ↓ X - 4L-SOT143 ASM161SEUS 1.1-5.5 2.93 T2 - - - X - ↓ X - 4L-SOT143 ASM161TEUS 1.1-5.5 3.08 T2 - - - X - ↓ X - 4L-SOT143 ASM162JEUS 1.1-5.5 4 T2 - - - - - ↓ - X 4L-SOT143 ASM162LEUS 1.1-5.5 4.63 T2 - - - - - ↓ - X 4L-SOT143 ASM162MEUS 1.1-5.5 4.38 T2 - - - - - ↓ - X 4L-SOT143 ASM162REUS 1.1-5.5 2.63 T2 - - - - - ↓ - X 4L-SOT143 ASM162SEUS 1.1-5.5 2.93 T2 - - - - - ↓ - X 4L-SOT143 ASM162TEUS 1.1-5.5 3.08 T2 - - - - - ↓ - X 4L-SOT143 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. www.alsc.com Product Guide 2004 15 Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP Low Power CPU Supervisors ASM1233DZ-10 1.2-5.5 4.375 T2 - - - X - - X - 4L-SOT223 ASM1233AZ-15 1.2-5.5 2.72 T2 - - - X - - X - 4L-SOT223 ASM1233DZ-15 1.2-5.5 4.125 T2 - - - X - - X - 4L-SOT223 ASM1233DZ-5 1.2-5.5 4.625 T2 - - - X - - X - 4L-SOT223 ASM1233MS-3 1.2-5.5 2.72 T2 - - - X - - X - 8-SO ASM1233MS-5 1.2-5.5 4.375 T2 - - - X - - X - 8-SO ASM1233MS-55 1.2-5.5 4.625 T2 - - - X - - X - 8-SO ASM1810R-10 1.2-5.5 4.37 T2 - - - X - - - X 3L-SOT23 ASM1810R-15 1.2-5.5 4.12 T2 - - - X - - - X 3L-SOT23 ASM1810R-5 1.2-5.5 4.62 T2 - - - X - - - X 3L-SOT23 ASM1811R-10 1.2-5.5 4.35 T2 - - - X - - X - 3L-SOT23 ASM1811R-15 1.2-5.5 4.13 T2 - - - X - - X - 3L-SOT23 ASM1811R-5 1.2-5.5 4.62 T2 - - - X - - X - 3L-SOT23 ASM1812R-10 1.2-5.5 4.35 T2 - - - - X - - X 3L-SOT23 ASM1812R-15 1.2-5.5 4.13 T2 - - - - X - - X 3L-SOT23 ASM1812R-5 1.2-5.5 4.62 T2 - - - - X - - X 3L-SOT23 ASM1815R-10 1.2-5.5 2.88 T2 - - - X - - - X 3L-SOT23 ASM1815R-20 1.2-5.5 2.55 T2 - - - X - - - X 3L-SOT23 ASM1815R-5 1.2-5.5 3.06 T2 - - - X - - - X 3L-SOT23 ASM1816R-10 1.2-5.5 2.88 T2 - - - X - - X - 3L-SOT23 ASM1816R-20 1.2-5.5 2.55 T2 - - - X - - X - 3L-SOT23 ASM1816R-5 1.2-5.5 3.06 T2 - - - X - - X - 3L-SOT23 ASM1817R-10 1.2-5.5 2.88 T2 - - - - X - - X 3L-SOT23 ASM1817R-20 1.2-5.5 2.55 T2 - - - - X - - X 3L-SOT23 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. 16 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM1817R-5 1.2-5.5 3.06 T2 - - - - X - - X 3L-SOT23 ASM8500-27 1.0-5.5 2.7 T2 - - - X - - X - 3L-SOT89 ASM8500-29 1.0-5.5 2.93 T2 - - - X - - X - 3L-SOT89 ASM8500-42 1.0-5.5 4.2 T2 - - - X - - X - 3L-SOT89 CPU Supervisors with Dual Supply Monitoring, Selectable Threshold ASM1834 1.2-5.5 Vt2 T2 - - - X - L - X 8P-DIP ASM1834A 1.2-5.5 Vt2 T2 - - - X - L X X 8P-DIP ASM1834AEMA 1.2-5.5 Vt2 T2 - - - X - L X X 8-MicroSO ASM1834AS 1.2-5.5 Vt2 T2 - - - X - L X X 8-SO ASM1834D 1.2-5.5 Vt2 T2 - - - - X L X X 8P-DIP ASM1834DEMA 1.2-5.5 Vt2 T2 - - - - X L - X 8-MicroSO ASM1834DS 1.2-5.5 Vt2 T2 - - - - X L - X 8-SO ASM1834EMA 1.2-5.5 Vt2 T2 - - - X - L - X 8-MicroSO ASM1834S 1.2-5.5 Vt2 T2 - - - X - L - X 8-SO CPU Supervisors with Watchdog Timer, Battery Backup, and Power Fail Detector ASM690ACPA 1.1-5.5 4.65 T1 X X X X - - - X 8P-DIP ASM690ACSA 1.1-5.5 4.65 T1 X X X X - - - X 8-SO ASM690AEPA 1.1-5.5 4.65 T2 X X X X - - - X 8P-DIP ASM690AESA 1.1-5.5 4.65 T2 X X X X - - - X 8-SO ASM692ACPA 1.1-5.5 4.4 T1 X X X X - - - X 8P-DIP ASM692ACSA 1.1-5.5 4.4 T1 X X X X - - - X 8-SO ASM692AEPA 1.1-5.5 4.4 T2 X X X X - - - X 8P-DIP ASM692AESA 1.1-5.5 4.4 T2 X X X X - - - X 8-SO ASM802LCPA 1.1-5.5 4.65 T1 X X X X - - - X 8P-DIP ASM802LCSA 1.1-5.5 4.65 T1 X X X X - - - X 8-SO ASM802LEPA 1.1-5.5 4.65 T2 X X X X - - - X 8P-DIP ASM802LESA 1.1-5.5 4.65 T2 X X X X - - - X 8-SO ASM802MCPA 1.1-5.5 4.4 T1 X X X X - - - X 8P-DIP ASM802MCSA 1.1-5.5 4.4 T1 X X X X - - - X 8-SO ASM802MEPA 1.1-5.5 4.4 T2 X X X X - - - X 8P-DIP Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. www.alsc.com Product Guide 2004 17 Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM802MESA 1.1-5.5 4.4 T2 X X X X - - - X 8-SO ASM805LCPA 1.1-5.5 4.65 T1 X X X - X - - X 8P-DIP ASM805LCSA 1.1-5.5 4.65 T1 X X X - X - - X 8-SO ASM805LEPA 1.1-5.5 4.65 T2 X X X - X - - X 8P-DIP ASM805LESA 1.1-5.5 4.65 T2 X X X - X - - X 8-SO CPU Supervisors with Watchdog Timer and Power Fail Detector ASM705CPA 1.2-5.5 4.65 T1 X X - X - L - X 8P-DIP ASM705CSA 1.2-5.5 4.65 T1 X X - X - L - X 8-SO ASM705CUA 1.2-5.5 4.65 T1 X X - X - L - X 8-MicroSO ASM705EPA 1.2-5.5 4.65 T2 X X - X - L - X 8P-DIP ASM705ESA 1.2-5.5 4.65 T2 X X - X - L - X 8-SO ASM706CPA 1.2-5.5 4.4 T1 X X - X - L - X 8P-DIP ASM706CSA 1.2-5.5 4.4 T1 X X - X - L - X 8-SO ASM706CUA 1.2-5.5 4.4 T1 X X - X - L - X 8-MicroSO ASM706EPA 1.2-5.5 4.4 T2 X X - X - L - X 8P-DIP ASM706ESA 1.2-5.5 4.4 T2 X X - X - L - X 8-SO ASM706JCPA 1.1-5.5 4 T1 X X - X - L - X 8P-DIP ASM706JCSA 1.1-5.5 4 T1 X X - X - L - X 8-SO ASM706JCUA 1.1-5.5 4 T1 X X - X - L - X 8-MicroSO ASM706JEPA 1.2-5.5 4 T2 X X - X L - X 8P-DIP ASM706JESA 1.2-5.5 4 T2 X X - X - L - X 8-SO ASM706PCPA 1.1-5.5 2.63 T1 X X - X L - X 8P-DIP ASM706PCSA 1.1-5.5 2.63 T1 X X - X L - X 8-SO ASM706PCUA 1.1-5.5 2.63 T1 X X - X L - X 8-MicroSO ASM706PEPA 1.2-5.5 2.63 T2 X X - X L - X 8P-DIP ASM706PESA 1.2-5.5 2.63 T2 X X - X L - X 8-SO ASM706RCPA 1.1-5.5 2.63 T1 X X - X - L - X 8P-DIP ASM706RCSA 1.1-5.5 2.63 T1 X X - X - L - X 8-SO ASM706RCUA 1.1-5.5 2.63 T1 X X - X - L - X 8-MicroSO Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. 18 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM706REPA 1.2-5.5 2.63 T2 X X - X - L - X 8P-DIP ASM706RESA 1.2-5.5 2.63 T2 X X - X - L - X 8-SO ASM706SCPA 1.1-5.5 2.93 T1 X X - X - L - X 8P-DIP ASM706SCSA 1.1-5.5 2.93 T1 X X - X - L - X 8-SO ASM706SCUA 1.1-5.5 2.93 T1 X X - X - L - X 8-MicroSO ASM706SEPA 1.2-5.5 2.93 T2 X X - X - L - X 8P-DIP ASM706SESA 1.2-5.5 2.93 T2 X X - X - L - X 8-SO ASM706TCPA 1.1-5.5 3.08 T1 X X - X - L - X 8P-DIP ASM706TCSA 1.1-5.5 3.08 T1 X X - X - L - X 8-SO ASM706TCUA 1.1-5.5 3.08 T1 X X - X - L - X 8-MicroSO ASM706TEPA 1.2-5.5 3.08 T2 X X - X - L - X 8P-DIP ASM706TESA 1.2-5.5 3.08 T2 X X - X - L - X 8-SO ASM813LCPA 1.1-5.5 4.65 T1 X X - - X L - X 8P-DIP ASM813LCSA 1.1-5.5 4.65 T1 X X - - X L - X 8-SO ASM813LCUA 1.1-5.5 4.65 T1 X X - - X L - X 8-MicroSO ASM813LEPA 1.1-5.5 4.65 T2 X X - - X L - X 8P-DIP ASM813LESA 1.1-5.5 4.65 T2 X X - - X L - X 8-SO CPU Supervisors with Power Fail Detector ASM707CPA 1.2-5.5 4.65 T1 X - - X X L - X 8P-DIP ASM707CSA 1.2-5.5 4.65 T1 X - - X X L - X 8-SO ASM707CUA 1.2-5.5 4.65 T1 X - - X X L - X 8-MicroSO ASM707EPA 1.2-5.5 4.65 T2 X - - X X L - X 8P-DIP ASM707ESA 1.2-5.5 4.65 T2 X - - X X L - X 8-SO ASM708CPA 1.2-5.5 4.4 T1 X - - X X L - X 8P-DIP ASM708CSA 1.2-5.5 4.4 T1 X - - X X L - X 8-SO ASM708CUA 1.2-5.5 4.4 T1 X - - X X L - X 8-MicroSO ASM708EPA 1.2-5.5 4.4 T2 X - - X X L - X 8P-DIP ASM708ESA 1.2-5.5 4.4 T2 X - - X X L - X 8-SO ASM708JCPA 1.1-5.5 4 T1 X - - X X L - X 8P-DIP ASM708JCSA 1.1-5.5 4 T1 X - - X X L - X 8-SO ASM708JCUA 1.1-5.5 4 T1 X - - X X L - X 8-MicroSO ASM708JEPA 1.2-5.5 4 T2 X - - X X L - X 8P-DIP ASM708JESA 1.2-5.5 4 T2 X - - X X L - X 8-SO Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. www.alsc.com Product Guide 2004 19 Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM708RCPA 1.1-5.5 2.63 T1 X - - X X L - X 8P-DIP ASM708RCSA 1.1-5.5 2.63 T1 X - - X X L - X 8-SO ASM708RCUA 1.1-5.5 2.63 T1 X - - X X L - X 8-MicroSO ASM708REPA 1.2-5.5 2.63 T2 X - - X X L - X 8P-DIP ASM708RESA 1.2-5.5 2.63 T2 X - - X X L - X 8-SO ASM708SCPA 1.1-5.5 2.93 T1 X - - X X L - X 8P-DIP ASM708SCSA 1.1-5.5 2.93 T1 X - - X X L - X 8-SO ASM708SCUA 1.1-5.5 2.93 T1 X - - X X L - X 8-MicroSO ASM708SEPA 1.2-5.5 2.93 T2 X - - X X L - X 8P-DIP ASM708SESA 1.2-5.5 2.93 T2 X - - X X L - X 8-SO ASM708TCPA 1.1-5.5 3.08 T1 X - - X X L - X 8P-DIP ASM708TCSA 1.1-5.5 3.08 T1 X - - X X L - X 8-SO ASM708TCUA 1.1-5.5 3.08 T1 X - - X X L - X 8-MicroSO ASM708TEPA 1.2-5.5 3.08 T2 X - - X X L - X 8P-DIP ASM708TESA 1.2-5.5 3.08 T2 X - - X X L - X 8-SO Low Power CPU Supervisors ASM809JEUR 1.2-5.5 4 T3 - - - X - - - X 3L-SOT23 ASM809LEUR 1.2-5.5 4.63 T3 - - - X - - - X 3L-SOT23 ASM809MEUR 1.2-5.5 4.38 T3 - - - X - - - X 3L-SOT23 ASM809REUR 1.2-5.5 2.63 T3 - - - X - - - X 3L-SOT23 ASM809SEUR 1.2-5.5 2.93 T3 - - - X - - - X 3L-SOT23 ASM809TEUR 1.2-5.5 3.08 T3 - - - X - - - X 3L-SOT23 ASM810JEUR 1.2-5.5 4 T3 - - - - X - - X 3L-SOT23 ASM810LEUR 1.2-5.5 4.63 T3 - - - - X - - X 3L-SOT23 ASM810MEUR 1.2-5.5 4.38 T3 - - - - X - - X 3L-SOT23 ASM810REUR 1.2-5.5 2.63 T3 - - - - X - - X 3L-SOT23 ASM810SEUR 1.2-5.5 2.93 T3 - - - - X - - X 3L-SOT23 ASM810TEUR 1.2-5.5 3.08 T3 - - - - X - - X 3L-SOT23 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. 20 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
CPU Supervisor Product Selector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM811JEUS 1.2-5.5 4 T3 - - - X - L - X 4L-SOT143 ASM811LEUS 1.2-5.5 4.63 T3 - - - X - L - X 4L-SOT143 ASM811MEUS 1.2-5.5 4.38 T3 - - - X - L - X 4L-SOT143 ASM811REUS 1.2-5.5 2.63 T3 - - - X - L - X 4L-SOT143 ASM811SEUS 1.2-5.5 2.93 T3 - - - X - L - X 4L-SOT143 ASM811TEUS 1.2-5.5 3.08 T3 - - - X - L - X 4L-SOT143 ASM812JEUS 1.2-5.5 4 T3 - - - - X L - X 4L-SOT143 ASM812LEUS 1.2-5.5 4.63 T3 - - - - X L - X 4L-SOT143 ASM812MEUS 1.2-5.5 4.38 T3 - - - - X L - X 4L-SOT143 ASM812REUS 1.2-5.5 2.63 T3 - - - - X L - X 4L-SOT143 ASM812SEUS 1.2-5.5 2.93 T3 - - - - X L - X 4L-SOT143 ASM812TEUS 1.2-5.5 3.08 T3 - - - - X L - X 4L-SOT143 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. All products in SOT-23 and SOT-143 package are only offered in Tape and Reel.To order parts in Tape and Reel,add “-T” to part number. www.alsc.com Product Guide 2004 21 Notice: The information in this document is subject to change without notice.
CPU Supervisor Cross Reference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM1232LP DS1232LPS-2 IMP1232LP MIC1232N TC1232CPA ASM1232LPCMA DS1232LPµ IMP1232LPCMA - - - ASM1232LPEMA DS1232LPµ IMP1232LPEMA - - - ASM1232LPN DS1232LP IMP1232LPN - MIC1232N TC1232EPA ASM1232LPS DS1232LPS IMP1232LPS - - TC1232COE ASM1232LPS-2 DS1232LPSN-2 IMP1232LPS-2 - MIC1232M TC1232COA ASM1232LPSN DS1232LPS IMP1232LPSN - - TC1232EOE ASM1232LPSN-2 DS1232LPSN-2 IMP1232LPSN-2 - MIC1232M TC1232EOA ASM1233AZ-15 DS1233A-15 - - - - ASM1233DZ-5 DS1233DZ-5 IMP1233DZ-5 - - - ASM1233DZ-10 DS1233DZ-10 IMP1233DZ-10 - - - ASM1233DZ-15 DS1233DZ-15 IMP1233DZ-15 - - - ASM1233MS-55 DS1233MS-55 IMP1233MS-55 - - - ASM1233MS-5 DS1233MS-5 IMP1233MS-5 - - - ASM1233MS-3 DS1233MS-3 IMP1233MS-3 - - - ASM161JEUS MAX6467US40 IMP161JEUS - - - ASM161LEUS MAX6467US46 IMP161LEUS - - - ASM161MEUS MAX6467US44 IMP161MEUS - - - ASM161REUS MAX6467US26 IMP161REUS - - - ASM161SEUS MAX6467US29 IMP161SEUS - - - ASM161TEUS MAX6467US31 IMP161TEUS - - - ASM162JEUS - IMP162JEUS - - - ASM162LEUS - IMP162LEUS - - - ASM162MEUS - IMP162MEUS - - - ASM162REUS - IMP162REUS - - - ASM162SEUS - IMP162SEUS - - - ASM162TEUS - IMP162TEUS - - - ASM1810R-5 DS1810R-5 IMP1810R-5 - MIC1810-5U TC1272-5 ASM1810R-10 DS1810R-10 IMP1810R-10 - MIC1810-10U TC1272-10 ASM1810R-15 DS1810R-15 IMP1810R-15 - MIC1810-15U TC1272-15 ASM1811R-5 DS1811R-5 IMP1811R-5 - - - ASM1811R-10 DS1811R-10 IMP1811R-10 - - - ASM1811R-15 DS1811R-15 IMP1811R-15 - - - ASM1812R-5 DS1812R-5 IMP1812R-5 - - TC1274-5 ASM1812R-10 DS1812R-10 IMP1812R-10 - - TC1274-10 ASM1812R-15 DS1812R-15 IMP1812R-15 - - TC1274-15 ASM1815R-5 DS1815R-5 IMP1815R-5 - MIC1815-5U TC1275-5 ASM1815R-10 DS1815R-10 IMP1815R-10 - MIC1815-10U TC1275-10 ASM1815R-20 DS1815R-20 IMP1815R-20 - MIC1815-20U TC1275-20 ASM1816R-5 DS1816R-5 IMP1816R-5 - - TC1276-5 ASM1816R-10 DS1816R-10 IMP1816R-10 - - TC1276-10 ASM1816R-20 DS1816R-20 IMP1816R-20 - - TC1276-20 22 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
CPU Supervisor Cross Reference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM1817R-5 DS1817R-5 IMP1817R-5 - - TC1277-5 ASM1817R-10 DS1817R-10 IMP1817R-10 - - TC1277-10 ASM1817R-20 DS1817R-20 IMP1817R-20 - - TC1277-20 ASM1832 DS1832 IMP1832 - MIC1832N - ASM1832EMA DS1832UN IMP1832EMA - - - ASM1832S DS1832S IMP1832S - MIC1832M - ASM1834 DS1834 IMP1834 - - - ASM1834A DS1834CMA IMP1834A - - - ASM1834AEMA DS1834AU IMP1834AEMA - - - ASM1834AS DS1834ASM IMP1834AS - - - ASM1834D DS1834D IMP1834D - - - ASM1834DEMA DS1834DU IMP1834DEMA - - - ASM1834DS DS1834DS IMP1834DS - - - ASM1834EMA DS1834U IMP1834EMA - - - ASM1834S DS1834S IMP1834S - - - ASM690ACPA MAX690ACPA IMP690ACPA ADM690AAN - - ASM690ACSA MAX690ACSA IMP690ACSA ADM690AARN - - ASM690AEPA MAX690AEPA IMP690AEPA ADM690AAN - - ASM690AESA MAX690AESA IMP690AESA ADM690AARN - - ASM692ACPA MAX692ACPA IMP692ACPA ADM692AAN - - ASM692ACSA MAX692ACSA IMP692ACSA ADM692AARN - - ASM692AEPA MAX692AEPA IMP692AEPA ADM692AAN - - ASM692AESA MAX692AESA IMP692AESA ADM692AARN - - ASM705CPA MAX705CPA IMP705CPA ADM705AN MIC705N - ASM705CSA MAX705CSA IMP705CSA ADM705AR MIC705M - ASM705CUA MAX705CUA IMP705CUA - - - ASM705EPA MAX705EPA IMP705EPA ADM705AN MIC705N - ASM705ESA MAX705ESA IMP705ESA ADM705AR MIC705M - ASM706CPA MAX706CPA IMP706CPA ADM706AN MIC706N - ASM706CSA MAX706CSA IMP706CSA ADM706AR MIC706M - ASM706CUA MAX706CUA IMP706CUA - - - ASM706EPA MAX706EPA IMP706EPA ADM706AN MIC706N - ASM706ESA MAX706ESA IMP706ESA ADM706AR MIC706M - ASM706JCPA MAX706JCPA IMP706JCPA - - - ASM706JCSA MAX706JCSA IMP706JCSA - - - ASM706JCUA MAX706JCUA IMP706JCUA - - - ASM706JEPA MAX706JEPA IMP706JEPA - - - ASM706JESA MAX706JESA IMP706JESA - - - ASM706PCPA MAX706PCPA IMP706PCPA ADM706PAN MIC706PN - ASM706PCSA MAX706PCSA IMP706PCSA ADM706PAR MIC706PM - ASM706PCUA MAX706PCUA IMP706PCUA - - - ASM706PEPA MAX706PEPA IMP706PEPA ADM706PAN MIC706PN - ASM706PESA MAX706PESA IMP706PESA ADM706PAR MIC706PM - www.alsc.com Product Guide 2004 23 Notice: The information in this document is subject to change without notice.
CPU Supervisor Cross Reference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM706RCPA MAX706RCPA IMP706RCPA ADM706RAN MIC706RN - ASM706RCSA MAX706RCSA IMP706RCSA ADM706RAR MIC706RM - ASM706RCUA MAX706RCUA IMP706RCUA - - - ASM706REPA MAX706REPA IMP706REPA ADM706RAN MIC706RN - ASM706RESA MAX706RESA IMP706RESA ADM706RAR MIC706RM - ASM706SCPA MAX706SCPA IMP706SCPA ADM706SAN MIC706SN - ASM706SCSA MAX706SCSA IMP706SCSA ADM706SAR MIC706SM - ASM706SCUA MAX706SCUA IMP706SCUA - - - ASM706SEPA MAX706SEPA IMP706SEPA ADM706SAN MIC706SN - ASM706SESA MAX706SESA IMP706SESA ADM706SAR MIC706SM - ASM706TCPA MAX706TCPA IMP706TCPA ADM706TAN MIC706TN - ASM706TCSA MAX706TCSA IMP706TCSA ADM706TAR MIC706TM - ASM706TCUA MAX706TCUA IMP706TCUA - - - ASM706TEPA MAX706TEPA IMP706TEPA ADM706TAN MIC706TN - ASM706TESA MAX706TESA IMP706TESA ADM706TAR MIC706TM - ASM707CPA MAX707CPA IMP707CPA ADM707AN MIC707N - ASM707CSA MAX707CSA IMP707CSA ADM707AR MIC707M - ASM707CUA MAX707CUA IMP707CUA ADM707ARM - - ASM707EPA MAX707EPA IMP707EPA ADM707AN MIC707N - ASM707ESA MAX707ESA IMP707ESA ADM707AR MIC707M - ASM708CPA MAX708CPA IMP708CPA ADM708AN MIC708N - ASM708CSA MAX708CSA IMP708CSA ADM708AR MIC708M - ASM708CUA MAX708CUA IMP708CUA ADM708ARM - - ASM708EPA MAX708EPA IMP708EPA ADM708AN MIC708N - ASM708ESA MAX708ESA IMP708ESA ADM708AR MIC708M - ASM708JCPA - IMP708JCPA - - - ASM708JCSA - IMP708JCSA - - - ASM708JCUA - IMP708JCUA - - - ASM708JEPA - IMP708JEPA - - - ASM708JESA - IMP708JESA - - - ASM708RCPA MAX708RCPA IMP708RCPA ADM708RAN MIC708RN - ASM708RCSA MAX708RCSA IMP708RCSA ADM708RAR MIC708RM - ASM708RCUA MAX708RCUA IMP708RCUA - - - ASM708REPA MAX708REPA IMP708REPA ADM708RAN MIC708RN - ASM708RESA MAX708RESA IMP708RESA ADM708RAR MIC708RM - ASM708SCPA MAX708SCPA IMP708SCPA ADM708SAN MIC708SN - ASM708SCSA MAX708SCSA IMP708SCSA ADM708SAR MIC708SM - ASM708SCUA MAX708SCUA IMP708SCUA - - - ASM708SEPA MAX708SEPA IMP708SEPA ADM708SAN MIC708SN - ASM708SESA MAX708SESA IMP708SESA ADM708SAR MIC708SM - ASM708TCPA MAX708TCPA IMP708TCPA ADM708TAN MIC708TN - ASM708TCSA MAX708TCSA IMP708TCSA ADM708TAR MIC708TM - ASM708TCUA MAX708TCUA IMP708TCUA - - - 24 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
CPU Supervisor Cross Reference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM708TEPA MAX708TEPA IMP708TEPA ADM708TAN MIC708TN - ASM708TESA MAX708TESA IMP708TESA ADM708TAR MIC708TM - ASM802LCPA MAX802LCPA IMP802LCPA ADM802LAN - - ASM802LCSA MAX802LCSA IMP802LCSA ADM802LARN - - ASM802LEPA MAX802LEPA IMP802LEPA ADM802LAN - - ASM802LESA MAX802LESA IMP802LESA ADM802LARN - - ASM802MCPA MAX802MCPA IMP802MCPA ADM802MAN - - ASM802MCSA MAX802MCSA IMP802MCSA ADM802MARN - - ASM802MEPA MAX802MEPA IMP802MEPA ADM802MAN - - ASM802MESA MAX802MESA IMP802MESA ADM802MARN - - ASM805LCPA MAX805LCPA IMP805LCPA ADM805LAN - - ASM805LCSA MAX805LCSA IMP805LCSA ADM805LARN - - ASM805LEPA MAX805LEPA IMP805LEPA ADM805LAN - - ASM805LESA MAX805LESA IMP805LESA ADM805LARN - - ASM809JEUR MAX809JEUR IMP809JEUR ADM809JAR MIC809JU TCM809J ASM809LEUR MAX809LEUR IMP809LEUR ADM809LAR MIC809LU TCM809L ASM809MEUR MAX809MEUR IMP809MEUR ADM809MAR MIC809MU TCM809M ASM809REUR MAX809REUR IMP809REUR ADM809RAR MIC809RU TCM809R ASM809SEUR MAX809SEUR IMP809SEUR ADM809SAR MIC809SU TCM809S ASM809TEUR MAX809TEUR IMP809TEUR ADM809TAR MIC809TU TCM809T ASM810JEUR MAX810JEUR IMP810JEUR ADM810JAR MIC810JU TCM810J ASM810LEUR MAX810LEUR IMP810LEUR ADM810LAR MIC810LU TCM810L ASM810MEUR MAX810MEUR IMP810MEUR ADM810MAR MIC810MU TCM810M ASM810REUR MAX810REUR IMP810REUR ADM810RAR MIC810RU TCM810R ASM810SEUR MAX810SEUR IMP810SEUR ADM810SAR MIC810SU TCM810S ASM810TEUR MAX810TEUR IMP810TEUR ADM810TAR MIC810TU TCM810T ASM811JEUS MAX811JEUS IMP811JEUS ADM811JAR MIC811JU TCM81LJ ASM811LEUS MAX811LEUS IMP811LEUS ADM811LAR MIC811 TCM811L ASM811MEUS MAX811MEUS IMP811MEUS ADM811MAR MIC811 TCM811M ASM811REUS MAX811REUS IMP811REUS ADM811RAR MIC811 TCM811R ASM811SEUS MAX811SEUS IMP811SEUS ADM811SAR MIC811 TCM811S ASM811TEUS MAX811TEUS IMP811TEUS ADM811TAR MIC811 TCM811T ASM812JEUS MAX812JEUS IMP812JEUS ADM812JAR MIC812 TCM812J ASM812LEUS MAX812LEUS IMP812LEUS ADM812LAR MIC812 TCM812L ASM812MEUS MAX812MEUS IMP812MEUS ADM812MAR MIC812 TCM812M ASM812REUS MAX812REUS IMP812REUS ADM812RAR MIC812 TCM812R ASM812SEUS MAX812SEUS IMP812SEUS ADM812SAR MIC812 TCM812S ASM812TEUS MAX812TEUS IMP812TEUS ADM812TAR MIC812 TCM812T ASM813LCPA MAX813LCPA IMP813LCPA - - - ASM813LCSA MAX813LCSA IMP813LCSA - - - ASM813LCUA MAX813LCUA IMP813LCUA - - - ASM813LEPA MAX813LEPA IMP813LEPA - - - ASM813LESA MAX813LESA IMP813LESA - - - www.alsc.com Product Guide 2004 25 Notice: The information in this document is subject to change without notice.
CPU Supervisor Cross Reference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM8500-27 - - - - - ASM8500-29 - - - - - ASM8500-42 - - - - - 26 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
SYSTEM SOLUTIONS PRODUCTS www.alsc.com Product Guide 2004 27 Notice: The information in this document is subject to change without notice.
System Solutions Products Alliance develops Connectivity and Networking ASSPs that address critical bandwidth and performance bottlenecks in legacy and emerging embedded, networking, computing and storage systems. • The Connectivity Product Portfolio includes the most comprehensive product selection of high-speed bridges based on HyperTransport™ technology (HT) including HT-to-PCI/PCI-X bridges. These bridges work together with the HyperTransport interface on the new generation of leading embedded and discreet microprocessors from AMD, Broadcom, PMC-Sierra and Transmeta. They allow system architects to leverage the performance of these leading microprocessors while still maintaining compatibility with legacy PCI/PCI-X based systems. The Connectivity Product Portfolio also includes a series of industry standard IEEE1149.1 JTAG gateways and controllers that partition a JTAG scan chain into multiple smaller chains for easier fault diagnostics and faster Flash programming. • The Networking Product Portfolio includes a family of networking media access controllers to address the needs of established and emerging protocols and standards including 10 Gbps Ethernet, Resilient Packet Ring (RPR) (IEEE802.17), Generic Framing Procedure (GFP) and others. These networking controllers serve a variety of applications and vertical markets including networking, cable infrastructure, storage, compute and others. 28 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Connectivity HyperTransport™ Bridges Product Selector Guide SP1011 AS90L10204 AS90L10208 HT Link Specifications HT 1.01 HT 1.05 HT 1.05 200, 300, 400, 500, 600 & 800 HT Link Speed 200 & 400 MHz 200, 400, 600 & 800 MHz MHz 8-bit for sides A and B 8-bit for sides A and B HT Link Width 8-bit for sides A and B (Supports 2 & 4-bit) (Supports 2 & 4-bit) PCI Bus Type PCI rev 2.2 PCI rev 2.2 PCI rev 2.2 PCI Bus Max Frequency 66 MHz 66 MHz 66 MHz PCI-X Bus Type - PCI-X 1.0b PCI-X 1.0b PCI-X Bus Max Frequency - 133 MHz 133 MHz PCI/PCI-X Bus Width 64-bit 64-bit 64-bit YES Configurable PCI/PCI-X bus - - 1 x 64-bit bus or 2 x 32-bit independent busses YES SP1011 Register Compatible - - Configurable as a single or dual SP1011 Core Voltage 2.5V 1.8V 1.8V PCI/PCI-X Bus Voltage 3.3V 3.3V 3.3V 5V Tolerant PCI IO YES YES YES GPIO - 7 per PCI/PCI-X bus 7 per PCI/PCI-X bus 5 external slots per PCI/PCI-X PCI/PCI-X Bus Arbiter 5 external slots 5 external slots bus Package 352 BGA 388 PBGA 388 PBGA Package Size 31mm x 31mm 27mm x 27mm 27mm x 27mm Lead Free or - YES (Green) YES (Green) Green Package* * Green package means lead free compound and substrate www.alsc.com Product Guide 2004 29 Notice: The information in this document is subject to change without notice.
AS90L10204 HyperTransport™-to-PCI/PCI-X Bridge Overview The AS90L10204 is a high performance bandwidth up to 25.6 Gbps. Each AS90L10204 HT port HyperTransport™-to-PCI/PCI-X bridge capable of can be 2, 4, or 8 bits wide in both transmit and receive tunneling the data between the two HT ports or directions. transferring the data between the HT ports and the AS90L10204 supports one 64-bit, PCI/PCI- PCI/PCI-X port. It is designed for bandwidth-hungry X1.0b port to connect to a variety of PCI/PCI-X based and performance-intensive applications in computer peripherals and add-on cards such as NICs, storage servers, workstations, desktop PCs and embedded HBA and others. Up to 31 devices can be daisy- systems. chained to build higher capacity systems with multiple Each 8-bit HT port operates at frequencies of PCI/PCI-X buses and HT-based peripherals. 200, 400, 600 and 800 MHz DDR for both transmit and receive directions, and sustains a total aggregate Key Features • Two bidirectional 8-bit HyperTransport interfaces: • Built-in two-level PCI arbiter with support for up to five • Supports 200, 400, 600 and 800 MHz DDR (double external devices data rate) for peak bandwidth of 3.2 GB/s per 8-bit • Can also be configured to support an external bidirectional HT port arbiter • Supports dynamic frequency reprogramming • 3.3V PCI IO with 5V tolerant IOs • Complies with HyperTransport 1.05 Link Interface • Transaction forwarding for the following commands: Specification • All IO and memory commands • Tunnels between the two HyperTransport interfaces • Type 1 to Type 1 configuration commands • The HT interfaces support dual-hosted chain (host (downstream only) CPU on each port) with the capability to transfer data • Type 1 to Type 0 configuration commands from the PCI/PCI-X bus to either host CPU (downstream only) • 1 x 64 bit, up to 133 MHz PCI-X 1.0b with support for • 1.8V core, 1.2V HT IO, 3.3V PCI/PCI-X IO up to 66 MHz PCI 2.2 • JTAG port • Supports with parity and error checking features • Available in a 388-pin PBGA green package AS90L10204 Device Block Diagram H T 1 .0 5 Inte rfa ce H T 1 .0 5 Inte rfa ce Lin k Interface L ink In te rfa ce Tx Tx Tx Tx PHY F IF O F IF O PHY 8-bit H T P acket G en era to r P acke t G e ne rator 8 -b it H T @ 800 M H z Lin k Interface L ink In te rfa ce @ 80 0 M H z Rx Rx Rx Rx PHY F IF O F IF O PHY R x B uffer R x B uffer P C I/P C I-X Interface 64 -b it P C I/P C I-X P o rt 1x6 4-bit, 6 6 M H z P C I o r 133 M H z P C I-X 1 .0b 30 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
AS90L10208 HyperTransport™-to-PCI/PCI-X Bridge Overview The AS90L10208 is a high performance per 8-bit bidirectional HT port. Each AS90L10208 HT HyperTransport™-to-PCI/PCI-X bridge capable of port can be 2, 4, or 8-bits wide in both transmit and transferring data between the HT host port and the receive directions. AS90L10208 supports one 64-bit, other HT port or the PCI/PCI-X port. It is designed for PCI/PCI-X1.0b port that can be configured as a single bandwidth-hungry and performance-intensive 64-bit port or a dual 32-bit ports. Up to 31 devices can applications in communications, networking, servers, be daisy-chained to build higher capacity systems with and storage systems. multiple PCI/PCI-X buses and HT-based peripherals. A Each HT port operates at frequencies up to 800 fairness algorithm allocates bandwidth among devices, MHz DDR for both transmit and receive directions and thereby eliminating starvation of bridges at the end of sustains a total aggregate bandwidth up to 25.6 Gbps the chain. Key Features • Two bidirectional 8-bit HyperTransport interfaces: • Built-in two-level PCI arbiter with support for up to five • Supports 200, 300, 400, 500, 600 and 800 MHz DDR external devices (double data rate) for peak bandwidth of 3.2 GB/s per • Can be configured to support an external arbiter 8-bit bidirectional HT port • 3.3V PCI IO with 5V tolerant IOs • Supports dynamic frequency reprogramming • Supports with parity and error checking features • Complies with HyperTransport 1.05 Link Interface • Superset register compatible with the SP1011 to Specifications leverage the same software driver • No protocol-induced maximum HyperTransport link • Can be configured to fully emulate a single or a dual length, which allows system designers to optimize speed SP1011 devices vs. distance • Transaction forwarding for the following commands: • The HT interfaces support dual-hosted chain • All IO and memory commands • One 64-bit configurable PCI/PCI-X 1.0b port: • Type 1 to Type 1 configuration commands • 1 x 64-bit, up to 66 MHz PCI 2.2 or up to 133 MHz (downstream only) PCI-X 1.0b • Type 1 to Type 0 configuration commands • 2 x 32-bit, up to 66 MHz PCI 2.2 or up to 133 MHz (downstream only) PCI-X 1.0b • 1.8V core, 1.2V HT IO, 3.3V PCI/PCI-X IO • Supports daisy-chaining up to 31 devices. The • JTAG port bandwidth is shared among the devices using a fairness • Available in a 388-pin PBGA green package algorithm AS90L10208 Device Block Diagram H T 1 .0 5 Inte rfa ce H T 1 .0 5 Inte rfa ce Lin k Interface L ink In te rfa ce Tx Tx Tx Tx PHY F IF O F IF O PHY 8-bit H T P acket G en era to r P acke t G e ne rator 8-b it H T @ 800 M H z Lin k Interface L ink In te rfa ce @ 800 M H z Rx Rx Rx Rx PHY F IF O F IF O PHY R x B uffer R x B uffer P C I/P C I-X Interface 1x6 4-bit, 6 6 M H z P C I o r 133 M H z P C I-X 1 .0b 2x3 2-bit, 6 6 M H z P C I o r 133 M H z P C I-X 1 .0b www.alsc.com Product Guide 2004 31 Notice: The information in this document is subject to change without notice.
JTAG Controllers Product Selector Guide AS91L1001 AS91L1002 AS91L1003U AS91L1006BU Description JTAG Test Controller JTAG Test Sequencer 3-Port JTAG Gateway 6-Port JTAG Gateway IEEE1149.1 JTAG 1 1 1 1 Primary Port IEEE1149.1 JTAG 1 - 3 6 Secondary Port YES Flash Interface - (Used to execute tests - - stored in Flash) YES CPU Interface (Used to allow CPU to - - - drive the tests) Core and IO Voltage 3.3V 3.3V 3.3V 3.3V 5V Tolerant IO YES YES YES YES 100-pin LQFP 100-pin LQFP 100-pin LQFP 100-pin LQFP Package 100-pin FPBGA 100-pin FPBGA 100-pin FPBGA 100-pin FPBGA 18mm x 18mm (LQFP) 18mm x 18mm (LQFP) 18mm x 18mm (LQFP) 18mm x 18mm (LQFP) Package Size 11mm x 11mm (FPBGA) 11mm x 11mm (FPBGA) 11mm x 11mm (FPBGA) 11mm x 11mm (FPBGA) Lead-Free or YES YES YES YES (Lead-free for LQFP, (Lead-free for LQFP, (Lead-free for LQFP, (Lead-free for LQFP, Green Package* Green for FPBGA) Green for FPBGA) Green for FPBGA) Green for FPBGA) * Green package means lead free compound and substrate 32 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
AS91L1001 JTAG Test Controller Overview The AS91L1001 device provides an Master mode: In this mode the primary interface between the 60x bus on the Motorola and secondary ports are now both totally MPC8260 processor and two totally independent independent IEEE1149.1 JTAG bus masters, IEEE1149.1 ports. It handles all the protocol for the 60x which enable concurrent operation on both of the bus to write and read directly to registers within the IEEE1149.1 JTAG chains. The Master mode device with no additional glue logic. enables the primary IEEE1149.1 JTAG port to be The AS91L1001 has three distinct modes of used to access other PCBs through the 5-wire operation, namely Slave mode, Master mode, and 3rd- IEEE1149.1 interface on the back plane. The Party Support mode. These different modes control secondary IEEE1149.1 JTAG port is used to test how data will be generated on the IEEE1149.1 buses. the card that is hosting the AS91L1001. Slave mode: In this mode, a transparent 3rd Party Support mode: In this mode, connection between the primary and the secondary bit bang operation (serial shifting of data) can be ports is established. This mode is usually used to test a enabled on any of the two ports. This is used to board from a system back plane. programs legacy FPGA/CPLD devices. Key Features • Interprets between the Motorola MPC8260 • Available in a 100-pin lead-free LQFP package or processor and two IEEE1149.1 JTAG ports a 100-pin FPBGA green package • Three distinct modes of operation: Slave mode, • 3.3V Core and IO Master mode, and 3rd Party Support mode • 5V Tolerant IOs • Supports a wide range of 3rd party tools • Pinout and feature set compatible (complete second source) with the Firecron JTS01 device AS91L1001 System Block Diagram Microprocessor AS91L1001 JTAG Test Controller Flash/Memory CPU Interface Port AS91L1003 3-Port JTAG DSP Gateway Secondary Primary JTAG JTAG Port Port ASIC/CPLD/FPGA www.alsc.com Product Guide 2004 33 Notice: The information in this document is subject to change without notice.
AS91L1002 JTAG Test Sequencer Overview The AS91L1002 provides a solution to perform The AS91L1002 can be controlled using one boundary scan tests and IEEE1149.1 JTAG tests on a of two different sources: a power-on reset circuit, or a PCB board at reset time without any third party test front panel switch. Any one of these can cause the hardware or a microprocessor. AS91L1002 to execute tests that have been loaded Once enabled, the AS91L1002 executes JTAG into the Flash memory. and boundary scan tests stored in a Flash memory. The When the tests have completed, the status of results of the tests are compared with the expected the execution is presented off chip through a status results also stored in Flash memory. Upon completion line to indicate the PASS/FAIL condition. The test of the tests, a PASS/FAIL result is presented. The results can also be written back into the Flash to AS91L1002 enables very rapid testing of the complete enable the diagnosis of failures when a PCB is PCB at reset time to provide a quick indication and a returned to the factory for debug. high degree of confidence in the operation of the PCB. Key Features • Performs IEEE1149.1 JTAG and boundary scan • Pinout and feature set compatible (complete tests in standalone mode without any 3rd party test second source) with the Firecron JTS02 device hardware • Available in a 100-pin LQFP lead-free package or • Eliminates the need for firmware development, a 100-pin FPBGA green package thereby speeding up time to market • 3.3V Core and IO • Performs self tests in parallel on multiple PCBs in a • 5V Tolerant IOs system • Stores tests results back into Flash memory AS91L1002 System Block Diagram Flash (Used to store test program and expected test results) Flash/Memory Test Result Indicators AS91L1002 AS91L1003U JTAG Test 3-Port JTAG DSP Sequencer Gateway ASIC/CPLD/ FPGA 34 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
AS91L1003U 3-Port JTAG Gateway Overview The AS91L1003U is a one to three-port JTAG multi-drop environment without any additional signals. gateway. It partitions a simple JTAG chain into three This multi-drop capability enables the standard separate chains. These separate chains can be IEEE1149.1 interface to be used not just for stand optionally configured to operate as a single chain. alone PCB testing, but complete system testing The AS91L1003U provides the capability of including all PCBs within a system back plane partitioning the PCB into multiple smaller IEEE1149.1 environment. scan chains totally under software control. Partitioning All of the protocols required for addressing the the IEEE1149.1 chains on the PCB has several AS91L1003U device via the multi-drop capability and benefits, which include easier fault diagnostics the protocols for configuring which of the three capabilities as a fault on one of the IEEE1149.1 Local IEEE1149.1 LSPs of the AS91L1003U are to be used, Scan Ports (LSPs) does not render the PCB un- is handled via the 3rd party ATPG tools from vendors testable, faster Flash programming on the PCBs and like Asset-Intertech and JTAG Technologies. In a removal of IEEE1149.1 signal loading issues. multi-drop environment it is also possible to perform The AS91L1003U device is used to provide interconnect tests between multiple PCBs within the enhanced capabilities to the standard IEEE1149.1. It system, thus extending the interconnect tests to the enables the IEEE1149.1 interface to be used in a true back plane itself. Key Features • Device multi-drop addressable via the IEEE1149.1 • Provides the ability to initiate self test on a remote protocol PCB via a standard IEEE1149.1 command • Support for 3 local scan chains addressable via the • Support for JTAG Technologies AutoWR feature IEEE1149.1 interface • Pinout and feature set compatible (complete • Support for Pass-through mode second source) with the Firecron JTS03U device • Support for the IEEE1149.1 USERCODE instruction • Available in a 100-pin LQFP lead-free package or • Support for Status instruction enabling non-intrusive a 100-pin FPBGA green package monitoring of the system card • 3.3V Core and IO • Local Scan Port (LSP) enable signal provides the • 5V Tolerant IOs ability to use non IEEE1149.1 compliant devices that require JTAG enable signal AS91L1003U System Block Diagram Standard ASIC Product JTAG Connector AS91L1003U Flash Memory Standard FPGA Product www.alsc.com Product Guide 2004 35 Notice: The information in this document is subject to change without notice.
AS91L1006BU 6-Port JTAG Gateway Overview The AS91L1006BU is a one to six-port JTAG. It enables the IEEE1149.1 JTAG interface to be IEEE1149.1 JTAG gateway. It partitions a simple used in a true multi-drop environment without any IEEE1149.1 JTAG chain into six separate chains. additional signals. This multi-drop capability enables These separate chains can be optionally configured to the standard IEEE1149.1 JTAG interface to be used operate as a single chain. not just for stand-alone PCB testing, but also for The AS91L1006BU provides the capability of complete system testing including all PCBs within a partitioning the PCB into multiple smaller IEEE1149.1 system back plane environment. JTAG scan chains that are totally under software All of the protocols required for addressing the control. Partitioning the IEEE1149.1 JTAG chains on AS91L1006BU device via the multi-drop capability and the PCB has several benefits, including easier fault the protocols for configuring which of the six diagnostics capabilities as a fault on one of the IEEE1149.1 LSPs on the AS91L1006BU is to be used, IEEE1149.1 JTAG Local Scan Ports (LSPs) does not are handled via 3rd party ATPG tools from vendors like render the PCB untestable, faster Flash programming Asset-Intertech and JTAG Technologies. In a multi- on the PCBs, and removal of IEEE1149.1 JTAG signal drop environment it is also possible to perform loading issues. interconnect tests between multiple PCBs within a The AS91L1006BU is also used to provide system, thus extending the interconnect tests to the enhanced capabilities to the standard IEEE1149.1 back plane itself. Key Features • Device multi-drop addressable via the IEEE1149.1 • Provides the ability to initiate self test on a remote JTAG protocol PCB via a standard IEEE1149.1 JTAG command • Support for 6 local scan chains addressable via the • Support for JTAG Technologies AutoWR feature, IEEE1149.1 JTAG interface which enables faster Flash programming • Support for Pass-through mode • Pinout and feature set compatible (complete • Support for status instruction enabling non-intrusive second source) with the Firecron JTS06BU device monitoring of the system card • Available in a 100-pin LQFP lead-free package or • Local Scan Port (LSP) enable signal provides the a 100-pin FPBGA green package ability to use non IEEE1149.1 JTAG compliant • 3.3V Core and IO devices that require JTAG enable signal • 5V Tolerant IOs AS91L1006BU System Block Diagram Standard Standard Microprocessor Product Product Standard ASIC ASIC JTAG Connector Product AS91L1006BU Flash Memory Flash Memory CPLD FPGA ASIC 36 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Networking RPR Controllers Product Selector Guide AS95L2101 AS95L2102 AS95L2100 Forwarding and Processing 5 Gbps 10 Gbps 20 Gbps Bandwidth Client-Side Interface 1 SPI4.2 port 1 SPI4.2 Port 2 SPI4.2 Ports Line-Side Interface 2 SFI-4 Ports (A and B) 2 SFI-4 Ports (A and B) 2 SFI-4 Ports (A and B) 32-bit PCI bus or 16-bit generic 32-bit PCI bus or 16-bit generic 32-bit PCI bus or 16-bit generic Control Plane Interface CPU bus CPU bus CPU bus Ethernet MAC 2 x 2.5G - 2 x 10G SONET (STS) / SDH (STM) OC-12 and OC-48 OC-12 and OC-48 OC-48 and OC-192 Protocol per Line-Side Port POS/HDLC, GFP and Ethernet / POS/HDLC, GFP and Frame Delineation POS/HDLC and GFP PacketPHY Ethernet / PacketPHY IEEE 802.17 draft 3.x IEEE 802.17 draft 3.x IEEE 802.17 draft 3.x Ring Protocols Cisco SRP v2 Cisco SRP v2 Cisco SRP v2 Others Others Others On-chip Transit Buffer Single or dual Single or dual Single or dual Single or Dual Card Mode YES YES YES Packet Priority Classification High, medium and low High, medium and low High, medium and low Package 928 HSBGA 928 HSBGA 928 HSBGA Package Size 40mm x 40mm 40mm x 40mm 40mm x 40mm www.alsc.com Product Guide 2004 37 Notice: The information in this document is subject to change without notice.
AS95L210x Family of Resilient Packet Ring Controllers Overview The AS95L210x family of Resilient Packet Ring standards. The AS95L210x family incorporates the (RPR) Controllers is especially designed to support the resilient ring Media Access Control (MAC) along with emerging IEEE802.17 Resilient Packet Ring (RPR) layer 1 and layer 2 functions that include: SONET standard at various line interface speeds including OC- framers, Ethernet MACs, POS/HDLC, GFP and WIS 12, OC-48 and OC-192 for SONET, and 2.5G and 10G frame delineators. The family also integrates on-chip for Ethernet and PacketPHY. address matching Content Addressable Memory The AS95L210x family is based on a unique (CAMs), and large buffer memory for insert and high patented Adaptive Compute Architecture that combines priority transit queues. wire-speed processing power with adaptive logic. This The AS95L210x family includes on-chip technology provides unparalleled control over hardware configuration, performance and fault-management and software that enable the same device to be features that support RPR requirements for Operation, adapted – without performance penalty – to various Administration, Maintenance and Provisioning ring protocols such as the emerging IEEE802.17 draft (OAM&P). The AS95L210x family is ideally suited for a 3.x, Cisco’s SRP™ and other proprietary protocols. variety of vertical markets including networking, The RPR Controller family uniquely supports communications, computing, cable infrastructure, multiple physical interfaces, modes, protocols and servers and storage cluster systems. AS95L210x Device Block Diagram DDR SRAM Interface RPR MAC Line-Side Port A Adaptive Header Receive Queue Engine SFI-4 OC-192 Framers Quad OC-48 Framers Quad OC-12 Framers Transit Transmit Queues 2.5G & 10G Ethernet MAC SPI4.2 HDLC/GFP Single or Scheduler Adaptive Compute Dual Engine SPI4.2 Line-Side Port B Interface SFI-4 OC-192 Framers Transit Transmit Queues Quad OC-48 Framers Quad OC-12 Framers 2.5G & 10G Ethernet MAC Adaptive Header Receive Queue HDLC/GFP Engine DDR SRAM Interface PCI / CPU Management Bus 38 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Functional Description The AS95L210x family includes three devices ring processing, bandwidth management and protection based on the same architecture that incorporate the switching. same set of features. They are software compatible Each packet received on the line-side ports is and differ in the bandwidth and line rate they support. delineated, processed and reassembled in accordance The AS95L2100 has a 20 Gbps maximum bandwidth with the appropriate protocol and framing convention and supports OC-192, OC-48 and 10 GE line (Ethernet, SONET, GFP, or HDLC) and passed to the interfaces. The AS95L2102 has 10 Gbps maximum AHE. The AHE performs CRC checks and discards or bandwidth and supports OC-48 and OC-12 line marks corrupt packets. In ring mode it matches the interfaces. The AS95L2101 has 5 Gbps max bandwidth packet’s destination address with CAM entries to and supports OC-48, OC-12 and 2.5 GE line interfaces. determine packet routing. Local traffic is stripped from Each device is comprised of two major subsystems: the the ring and the packet type is classified as data or line-side ports and the RPR MAC. control. Local data packets are transferred to the client- The two line-side ports (A and B) are side SPI4.2 port for delivery to the application symmetrical and each incorporates a PHY interface, processor. Control packets, consisting of provisioning frame delineation logic, SONET framers, Ethernet information, fairness messages, ring status, topology MACs and multiplexing logic. They are used to connect and others are passed to the control plane CPU or to the AS95L210x family to the rings through an external the client-side port for processing. PHY device (Serdes). The AS95L210x family supports multiple The RPR MAC performs the MAC functions queuing options including single or dual transit buffers and incorporates two Adaptive Header Engines (AHE), with up to three priority classifications (high, medium each with an address-matching CAM. It also includes and low). protection switching logic and an Adaptive Control The AHE can extract information from Engine (ACE) for executing fairness algorithms and encapsulated headers for various frame delineation controlling dispatching regimes. protocols enabling it to adapt to a wide spectrum of One or two client-side ports (depending on the industry and proprietary standards as well as to custom device) are used to connect to a client FPGA or to a header processing requirements. Network Processor (NPU). A control plane interface is The AS95L210x family of RPR Controllers used to configure and manage the operation of the operates in either single-line card or dual-line card AS95L210x RPR Controllers. modes. In single line-card mode, a single device The AS95L210x family operates in two modes. terminates the rings for cost efficiency. In dual-line card In standard topology mode (framer mode) it operates mode, two AS95L210x (one on each line card) as a dual full-duplex Ethernet MAC or as multiple terminate the rings (one for each ringlet) for SONET Framers; and in ring mode the AS95L210x redundancy. family additionally has all the logic required for packet Single-Line Card System Block Diagram Ring 0 Fabric Traffic Manager NPU/FPGA Ring 1 RPR PHY Controller AS95L210x Switch Ring 2 Control Ring 3 Plane CPU www.alsc.com Product Guide 2004 39 Notice: The information in this document is subject to change without notice.
Software A complete Linux-based software kernel driver (running the fairness algorithm). Binary file generation and user-space API that allows for configuration and tools and Assembler tools are included as part of the management of all line and client–side interfaces for software module. the AS95L210x RPR Controller family is available. The Host kernel snap-in executable contains The driver consists of two logical portions: the the software to manage the fairness algorithm (running main kernel driver that manages the hardware, and the in the Adaptive Control Engine), the topology discovery kernel “Snap-in” – referred to as Profile – that manages protocol, the intelligent protection switching and the ring protocol specific features. A different Profile is steering control as well as other ring control protocols needed for each of the ring protocols such as such as LRTT (Loop Round Trip Time) and FDD IEEE802.17 Draft 3.x, Cisco’s SRP and others. The (Fairness Differential Delay) calculations. following figure illustrates the software modules. The The AS95L210x family provides a number of driver also supports the two modes of operation: framer on-chip configurations and fault management features mode and ring mode. that support RPR requirements for OAM&P. Equipment Each Profile consists of two portions: a binary manufacturers use these adaptive features to provide executable file that is directly downloaded to the more robust and flexible multi-service solutions. AS95L210x family during system initialization; and a A user-level API tester is provided to allow host executable that interacts with the Profile and with each driver and ring-level API to be tested. The API the main kernel driver. tester also provides an easy mechanism to bring up the The binary file portion of the Profile contains AS95L210x family in ring mode or framer mode. execution code for the Adaptive Control Engine Software Modules User Space Kernel Space Physical Hardware Kernel Space AS95L210x Driver Customer Provided Threaded User Space Application Et PI PCI/CPU Bus tA he rn Controller RPR g m et open (..) open (..) M M gm Controller LC tA HD Configuration PI AS95L210x Statistics OS Kernel Multiplexer API GFP close (..) close (..) Error Handling t Mgm Mgm Handler Internet / Recovery RPR ET APIt Controller SON read (..) read (..) SPI4.2 Mgmt API AS95L210x Kernel Space Snap-in Profile IEEE 802.17 / SRP v2 / Others write (..) write (..) Profile Management API Instance Manager Topology Discovery ioctl (..) ioctl (..) Packet DMA Handler Intelligent Protection Diagnostics / Self Test Switching or Steering Control Ring Control API Fairness Algorithm 40 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
AS95L210x Key Features • Highly integrated device with on-chip SONET • Full duplex 2.5G and 10G Ethernet MAC processing Framers (OC-12/OC-48/OC-192), Ethernet MACs compliant with IEEEP802.3ae/D5.0 (2.5G and 10G) and RPR MAC • WIS (WAN Interface Sub-layer) support for 10 Gbps Ethernet Serial WAN applications • Supports IEEE802.17 draft 3.x, Cisco SRP v2 and others • Compliant with POS/HDLC IETF RFC 1662 and IETF RFC 2615 • Adaptive compute architecture accommodates modifications and proprietary protocols without • SONET/SDH framers defined by IETF RFCs 2615 / performance loss 1662 and GFP framers defined by ANSI T1X1.5 • Supports packet ring header processing, bandwidth • RMON counters comply with IETF RFC 2863 (802.3 management and protection switching MIBs) • Provides steered and wrapped protection switching (within 50 ms) per IEEE802.17 • Supports the Generic Framing Procedure (GFP) encapsulation per ANSI T1.105.02 (SONET) and • Supports up to 255 nodes per ring ITU-T G.709 (OTN) • Up to 20 Gbps bandwidth • On-chip memory for high-priority transit traffic buffer and staging buffer for insert traffic • Single-line card and dual-line card modes • On-chip CAM for address matching • Terminates up to 4 rings (8 ringlets) • Interface for external SRAM for medium and low • SONET/SDH section/line/path processing compliant priority transit traffic with Telcordia GR-253, ANSI T1.105, T1.416 and ITU G.751, G.783 and G.804 • The control plane interface can be configured either as a 32-bit PCI bus or as a generic 16-bit CPU bus • 928-pin HSBGA package www.alsc.com Product Guide 2004 41 Notice: The information in this document is subject to change without notice.
42 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
MEMORY PRODUCTS www.alsc.com Product Guide 2004 43 Notice: The information in this document is subject to change without notice.
SRAM Products Alliance offers a broad range of SRAM products, including synchronous and fast asynchronous SRAM. Synchronous SRAMs address the need for high-bandwidth data path buffers for primarily high-speed communications. Alliance offers a complete family of synchronous SRAMs, including No Turnaround Delay (NTD) and synchronous burst devices for these applications. In addition, Alliance supports the full range of 3.3V and 5V asynchronous SRAMs used with mainstream digital signal processors (DSPs) and microcontrollers. SRAM 64K 256K 512K 1M 2M 4M 9M 18M 36M 128K x 18 256K x 18 512K x 18 1M x 18 1M x 32/36 Synchronous - - - - 64K x 32/36 128K x 32/36 256K x 32/36 512K x 32/36 2M x 18 5V Fast 128K x 8 512K x 8 8K x 8 32K x 8 32K x 16 - - - - Asynchronous 64K x 16 256K x 16 3.3V Fast 128K x 8 512K x 8 - 32K x 8 32K x 16 - - - - Asynchronous 64K x 16 256K x 16 All SRAMs are available in industrial temperature range 44 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Synchronous SRAM Alliance Semicnductor 7C = CMOS SRAM Core Voltage: 33 = 33V, and 25 = 2.5V Device depth denoted in K bits or M bits NTDTM = No turn-around delay, PFS = pipelined single-cycle deselect, PFD = Pipelined dual-cycle deselect, FT = flow through Device density width: x18-bits, x32-bits, x36-bits Suffix letter denotes die revision Clock cycle time in MHz Packages: TQ = TQFP-thin quad flat pack (100 pin), B = ball gid array Temperature Ranges C = Commercial (0 C to 70 C) I = Industrial (-40 C to 85 C) AS 7 C 2 5 256 NTD 36A -166 TQ C 3.3V Synchronous SRAM Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 2M 64K x 36 AS7C3364FT36B 7.5 ns TQFP (100) Production 3.3V IO 64K x 32 AS7C3364FT32B 7.5 ns TQFP (100) Production 3.3V IO 128 x 18 AS7C33128FT18B 7.5 ns TQFP (100) Production 3.3V IO 64K x 36 AS7C3364PFS36B 166 TQFP (100) Production 3.3V IO 64K x 32 AS7C3364PFS32B 166 TQFP (100) Production 3.3V IO 128K x 18 AS7C33128PFS18B 166 TQFP (100) Production 3.3V IO 64K x 36 AS7C3364PFD36B 166 TQFP (100) Production 3.3V IO 64K x 32 AS7C3364PFD32B 166 TQFP (100) Production 3.3V IO 128K x 18 AS7C33128PFD18B 166 TQFP (100) Production 3.3V IO 4M 128K x 36 AS7C33128FT36B 7.5 ns TQFP (100) Production 3.3V IO 128K x 32 AS7C33128FT32B 7.5 ns TQFP (100) Production 3.3V IO 256K x 18 AS7C33256FT18B 7.5 ns TQFP (100) Production 3.3V IO 128K x 36 AS7C33128PFS36B 166 TQFP (100) Production 3.3V IO 128K x 32 AS7C33128PFS32B 166 TQFP (100) Production 3.3V IO 256K x 18 AS7C33256PFS18B 166 TQFP (100) Production 3.3V IO 128K x 36 AS7C33128PFD36B 166 TQFP (100) Production 3.3V IO 128K x 32 AS7C33128PFD32B 166 TQFP (100) Production 3.3V IO 256K x 18 AS7C33256PFD18B 166 TQFP (100) Production 3.3V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. www.alsc.com Product Guide 2004 45 Notice: The information in this document is subject to change without notice.
Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 9M 256K x 32 AS7C33256PFS32A 166 TQFP (100) Production 3.3V/2.5V IO 512K x 18 AS7C33512PFS18A 166 TQFP (100) Production 3.3V/2.5V IO 256K x 36 AS7C33256PFD36A 166 TQFP (100) Production 3.3V/2.5V IO 256K x 32 AS7C33256PFD32A 166 TQFP (100) Production 3.3V/2.5V IO 512K x 18 AS7C33512PFD18A 166 TQFP (100) Production 3.3V/2.5V IO 18M 512K x 36 AS7C33512FT36A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512FT32A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C331MFT18A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C331MPFS18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C33512PFS36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512PFS32A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C331MPFD18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K X 36 AS7C33512PFD36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512PFD32A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 36M 1M x 36 AS7C331MFT36A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 32 AS7C331MFT32A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 2M X 18 AS7C332MFT18A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 36 AS7C331MPFS36A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 32 AS7C331MPFS32A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 2M x 18 AS7C332MPFS18A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. 46 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
2.5V Synchronous SRAM Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 18M 512K x 36 AS7C25512FT36A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C25512FT32A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C251MFT18A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C251MPFD18A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C251MPFS18A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C25512PFS36A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C25512PFS32A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C25512PFD36A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C25512PFD32A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 3.3V NTD™ Synchronous SRAM (NTD is industry compatible with other ZBT™ and NT cycle products.) Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 2M 64K x 36 AS7C3364NTD36B 166 TQFP (100) Production 3.3V IO 64K x 32 AS7C3364NTD32B 166 TQFP (100) Production 3.3V IO 4M 128K x 36 AS7C33128NTD36B 166 TQFP (100) Production 3.3V IO 128K x 32 AS7C33128NTD32B 166 TQFP (100) Production 3.3V IO 256K x 18 AS7C33256NTD18B 166 TQFP (100) Production 3.3V IO 9M 256K x 36 AS7C33256NTD36A 166 TQFP (100) Production 3.3V/2.5V IO 256K x 32 AS7C33256NTD32A 166 TQFP (100) Production 3.3V/2.5V IO 512K x 18 AS7C33512NTD18A 166 TQFP (100) Production 3.3V/2.5V IO 18M 512K x 36 AS7C33512NTD36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512NTD32A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1 M x 18 AS7C331MNTD18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 36M 1M x 36 AS7C331MNTD36A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 32 AS7C331MNTD32A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 2M x 18 AS7C332MNTD18A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. www.alsc.com Product Guide 2004 47 Notice: The information in this document is subject to change without notice.
2.5V NTD™ Synchronous SRAM (NTD is industry compatible with other ZBT™ and NT cycle products.) Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 18M 1M x 18 AS7C251MNTD18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C25512NTD36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO Synchronous Dual Port SRAM Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 9M 256K x 36 AS9C25256M2036L 166 PQFP (208) Samples 3.3V/2.5V IO 512K x 18 AS9C25512M2018L 166 TQFP (144) Samples 3.3V/2.5V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. 48 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
Asynchronous SRAM Alliance Semicnductor 7C = CMOS SRAM Voltage: Blank = 5V CMOS, 3 = 3.3V CMOS Device number assigned by Alliance Semiconductor. Suffix letter denotes die revision. Access time in nanoseconds Packages: J = SOJ 300 or 400 mil, TJ = SOJ 300 mil (applies only when J is 400 mil), T = TSOP 1 or 2, ST = sTSOP Temperature Ranges C = Commercial (0 C to 70 C) I = Industrial (-40 C to 85 C) AS 7 C 3 4098A -12 J C 5V Fast Asynchronous SRAM Product Selector Guide Alliance Part Density Org Speed (ns) Packages Status** Comments Number 64K 8K x 8 AS7C164 10/12/15/20 SOJ (28) Production - 256K 32K x 8 AS7C256A 10/12/15/20 SOJ (28), TSOP1 (28) Production - 512K 32K x 16 AS7C513B 10/12/15/20 SOJ (44), TSOP2 (44) Production - SOJ (32.3 & 32.4), 32.3 = 300 mil, 1M 128K x 8 AS7C1024B 10/12/15/20 Production TSOP1(32) 32.4 = 400 mil CPG (Center Power & 128K x 8 AS7C1025B 10/12/15/20 SOJ (32.3 & 32.4) Production Ground) 64K x 16 AS7C1026B 10/12/15/20 SOJ (44), TSOP2 (44) Production - 4M AS7C4096 12/15/20 SOJ (36), TSOP2 (44) Production - 512K x 8 S=2Q ’04, AS7C4096A 12/15/20 SOJ (36), TSOP2 (44) - P= 3Q ‘04 AS7C4098 12/15/20 SOJ (44), TSOP2 (44) Production - 256K x 16 S=2Q ’04, AS7C4098A 12/15/20 SOJ (44), TSOP2 (44) - P= 3Q ‘04 ** S = sample date, P = estimated production date. www.alsc.com Product Guide 2004 49 Notice: The information in this document is subject to change without notice.
3.3V Fast Asynchronous SRAM Product Selector Guide Alliance Part Density Org Speed (ns) Packages Status** Comments Number 256K 32K x 8 AS7C3256A 10/12/15/20 SOJ (28), TSOP1 (28) Production - 512K 32K x 16 AS7C3513B 10/12/15/20 SOJ (44), TSOP2 (44) Production - SOJ (32.3 & 32.4), 32.3 = 300 mil, 1M 128K x 8 AS7C31024B 12/15/20 Production TSOP1(32) 32.4 = 400 mil CPG (Center Power 128K x 8 AS7C31025B 10/12/15/20 SOJ (32.3 & 32.4) Production & Ground) 64K x 16 AS7C31026B 10/12/15/20 SOJ (44), TSOP2 (44) Production - 4M 512K x 8 AS7C34096A 10/12/15/20 SOJ (36), TSOP2 (44) Production - 256K x 16 AS7C34098A 10/12/15/20 SOJ (44), TSOP2 (44) Production - ** S = sample date, P = estimated production date. 50 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
www.alsc.com Synchronous SRAM Cross Reference Guide CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33128FT18B 2M 128Kx18 3.3 133-166 CY7C1324F - - MT58L128L18FT K7B201825B - AS7C3364FT32B 2M 64Kx32 3.3 133-166 CY7C1336F IDT71V633S IS61LF6432A MT58L64L32FT K7B203225B GS82032AT AS7C3364FT36B 2M 64Kx36 3.3 133-166 CY7C1344F - IS61LF6436A MT58L64L36FT K7B203625B - AS7C33128PFS18B 2M 128Kx18 3.3 133-166 CY7C1326F - - MT58L128L18PT - - AS7C3364PFS32B 2M 64Kx32 3.3 133-166 CY7C1329G IDT71V632S IS61LP6432A MT58L64L32PT K7A203200B GS82032AT AS7C3364PFS36B 2M 64Kx36 3.3 133-166 CY7C1346G - IS61LP6436A MT58L64L36PT K7A203600B - AS7C33128PFD18B 2M 128Kx18 3.3 133-166 CY7C1223F - - MT58L128L18DT - - AS7C3364PFD32B 2M 64Kx32 3.3 133-166 - - - MT58L64L32DT - GS820E32AT AS7C3364PFD36B 2M 64Kx36 3.3 133-166 - - - MT58L64L36DT - - Product Guide 2004 AS7C3364NTD32B 2M 64Kx32 3.3 133-166 - - - MT55L64L32P1T - - AS7C3364NTD36B 2M 64Kx36 3.3 133-166 - - - MT55L64L36P1T - - AS7C33128FT32B 4M 128Kx32 3.3 133-166 CY7C1338F - IS61SF12832 MT58L128L32F1T K7B403225B GS840F36AT Notice: The information in this document is subject to change without notice. AS7C33128FT36B 4M 128Kx36 3.3 133-166 CY7C1345F IDT71V3577S IS61SF12836 MT58L128L36F1T K7B403625B GS840F36AT Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP 51
52 Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33256FT18B 4M 256Kx18 3.3 133-166 CY7C1325F IDT71V3579S IS61SF25618 MT58L256L18F1T K7B401825B GS840F36AT AS7C33128PFS32B 4M 128Kx32 3.3 133-166 CY7C1339F - IS61SP12832 MT58L128L32P1T K7A403200B - AS7C33128PFS36B 4M 128Kx36 3.3 133-166 CY7C1347F IDT71V3576S 1S61SP12836 MT58L128L36P1T K7A403600B GS84032AT AS7C33256PFS18B 4M 256Kx18 3.3 133-166 CY7C1327F IDT71V3578S IS61SP25618 MT58L256L18P1T K7A401800B GS84018AT AS7C33128PFD32B 4M 128Kx32 3.3 133-166 CY7C1340F - - MT58L128L32D1T K7A403201B GS840E32AT AS7C33128PFD36B 4M 128Kx36 3.3 133-166 - - - MT58L128L36D1T K7A403601B GS840E18AT AS7C33256PFD18B 4M 256Kx18 3.3 133-166 CY7C1328F - - MT58L256L18D1T - GS840E18AT AS7C33128NTD32B 4M 128Kx32 3.3 133-166 - - IS61NP12832 MT55L128L32P1T K7N403201B - AS7C33128NTD36B 4M 128Kx36 3.3 133-166 CY7C1350F IDT71V3556S IS61NP12836 MT55L128L36P1T K7N403601B GS840Z36AT Product Guide 2004 AS7C33256NTD18B 4M 256Kx18 3.3 133-166 CY7C1352F IDT71V3558S IS61NP25618 MT55L256L18P1T K7N401801B GS840Z18AT AS7C33256PFS32A 9M 256Kx32 3.3 133-166 CY7C1364B - IS61SPS25632 MT58L256L32PT - GS88032BT AS7C33512PFS18A 9M 512Kx18 3.3 133-166 CY7C1362B IDT71B67803S IS61SPS51218 MT58L512L18PT K7A801800B GS88018BT Notice: The information in this document is subject to change without notice. AS7C33512PFD18A 9M 512Kx18 3.3 133-166 CY7C1367B - IS61SPD51218T MT58L512L18DT K7A801801B GS880E18BT Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP www.alsc.com
www.alsc.com Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33256PFD32A 9M 256Kx32 3.3 133-166 CY7C1368B - IS61SPD25632T MT58L256L32DT - GS880E32BT AS7C33256PFD36A 9M 256Kx36 3.3 133-166 CY7C1366B - IS61SPD25636T MT58L256L36DT K7A803601B GS880E18BT AS7C33256NTD32A 9M 256Kx32 3.3 133-166 - - IS61NP25632 MT55L256L32PT - - AS7C33256NTD36A 9M 256Kx36 3.3 133-166 CY7C1354B IDT71V65603S IS61NP25636 MT55L256L36PT K7N803601B GS880Z36BT AS7C33512NTD18A 9M 512Kx18 3.3 133-166 CY7C1356B IDT71V65803S IS61NP51218 MT55L512L18PT K7N801801B GS880Z18BT AS7C33512FT32A 18M 512Kx32 3.3 133-166 - - - - - GS8160F32T AS7C33512FT36A 18M 512Kx36 3.3 133-166 CY7C1381C - IS61LF51236A - K7B163625B GS8160F36T AS7C251MFT18A 18M 1Mx18 2.5 166-250 - IDT71T75902S IS61VF102418A - - - AS7C25512FT32A 18M 512Kx32 2.5 166-250 - - - - - - Product Guide 2004 AS7C25512FT36A 18M 512Kx36 2.5 166-250 CY7C1381CV25 - IS61VF51236A - - - AS7C331MFT18A 18M 1Mx18 3.3 166-250 CY7C1383C - IS61LF102418A - K7B161825B GS8160F18T AS7C251MPFS18A 18M 1Mx18 2.5 166-250 CY7C1382CV25 - IS61VPS102418A - - - Notice: The information in this document is subject to change without notice. AS7C25512PFS32A 18M 512K x 32 2.5 166-250 - - - - - - Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP 53
54 Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C25512PFS36A 18M 512Kx36 2.5 166-250 CY7C1380CV25 - IS61VPS51236A - - - AS7C331MPFS18A 18M 1Mx18 3.3 166-250 CY7C1382C - IS61LPS102418A - K7A161800B GS816018T AS7C33512PFS32A 18M 512Kx32 3.3 133-166 - - - - - GS816032T AS7C33512PFS36A 18M 512Kx36 3.3 133-166 CY7C1380C - IS61LPS51236A - K7A163600B GS816036T AS7C251MPFD18A 18M 1Mx18 2.5 166-250 CY7C1387CV25 - IS61VPD102418A - - - AS7C25512PFD32A 18M 512Kx32 2.5 166-250 - - - - - GS8160E32T AS7C25512PFD36A 18M 512Kx36 2.5 166-250 CY7C1386CV25 - IS61VPD51236A - - - AS7C331MPFD18A 18M 1Mx18 3.3 166-250 CY7C1387C - IS61LPD102418A - K7A161801B GS8160E18T AS7C33512PFD32A 18M 512Kx32 3.3 133-166 - - - - - GS8160E32T Product Guide 2004 AS7C33512PFD36A 18M 512Kx36 3.3 133-166 CY7C1386C - IS61LPD51236A - K7A163601B GS8160E36T AS7C251MNTD18A 18M 1Mx8 2.5 166-250 CY7C1372CV25 IDT71T75802S IS61NVP102418 - K7N161845B - AS7C25512NTD36A 18M 512Kx36 2.5 166-250 CY7C1370CV25 IDT71T75062S IS61NVP51236 - K7N163645B - Notice: The information in this document is subject to change without notice. AS7C331MNTD18A 18M 1Mx18 3.3 166-250 CY7C1372C - IS61NLP102418 - K7N161801B GS8160Z36T Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP www.alsc.com
www.alsc.com Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33512NTD32A 18M 512Kx32 3.3 166-250 - - - - - - AS7C33512NTD36A 18M 512Kx36 3.3 133-166 CY7C1370C IS61NLP51236 - K7N163601B GS8160Z36T AS7C331MPFS32A 36M 1Mx32 3.3 166-250 - - - - - GS832032T AS7C331MPFS36A 36M 1Mx36 3.3 166-250 CY7C1440V33 - - - K7A323600M GS832036T AS7C332MPFS18A 36M 2Mx18 3.3 166-250 - - - - K7A321800M GS832018T AS7C331MFT32A 36M 1Mx32 3.3 166-250 - - - - - - AS7C331MFT36A 36M 1Mx36 3.3 166-250 CY7C1441V33 - - - K7B323625M - AS7C332MFT18A 36M 2Mx18 3.3 166-250 - - - - K7B321825M - Product Guide 2004 AS7C331MNTD32A 36M 1Mx32 3.3 166-250 - - - - - - AS7C331MNTD36A 36M 1Mx36 3.3 166-250 CY7C1460V33 - IS61NLP102436 - K7N323601M GS8320Z36T AS7C332MNTD18A 36M 2Mx18 3.3 166-250 CY7C1462V33 - - - K7N321801M GS8320Z18T Notice: The information in this document is subject to change without notice. Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP 55
56 Fast Asynchronous SRAM Cross Reference Guide Alliance Den Org Volt Speed (ns) Cypress GSI IDT ISSI Samsung AS7C164 64K 8Kx8 5V 10-20 CY7C185 - IDT7164L IS1C64B - AS7C256A 256K 32Kx8 5V 10-20 CY7C199 - IDT71256SA IS61C256AH - AS7C3256A 256K 32Kx8 3.3V 10-20 CY7C1399B GS70328 IDT71V256SA IS61LV256 - AS7C513B 512K 32x16 5V 10-20 CY7C1020B - - IS61C3216 - AS7C3513B 512K 32x16 3.3V 10-20 CY7C1020CV33 - - IS1LV3216L - CY7C109B AS7C1024B 1M 128Kx8 5V 10-20 - IDT1024S IS61C1024 - CY7C1009B Product Guide 2004 AS7C31024B 1M 128Kx8 3.3V 12-20 - - - - - 128Kx8 AS7C1025B 1M 5V 10-20 CY7C1019B - IDT71124S - K6R1008C1D CPG T=TSOP I/II Z=TSOP I/II PZ=TSOP I TS=TSOP I H=sTSOP I T=TSOP I/II V=300/400 mil SOJ PH=TSOP II Alliance Semiconductor package abbreviations and their equivalents. TP=TSOP II B=48-pin BGA E=48-pin BGA P=PDIP Y=400 mil SOJ T=TSOP I/II, TJ=300 mil SOJ, J=400 mil SOJ, ST=sTSOP I, CPG=Center power and ground SJ=300 mil SOJ M=48-pin mBGA J=300/400 mil SOJ B=48-pin BGA TY=300 mil SOJ C=Commercial, I=Industrial J=400 mil SOJ J=300 SOJ H=119 BGA Notice: The information in this document is subject to change without notice. BA=48-pin mBGA P=PDIP B=119 BGA K=400 SOJ D=PDIP BG=119 PBGA B=48-pin BGA N,P or W=PDIP www.alsc.com
www.alsc.com Fast Asynchronous SRAM Cross Reference Guide (Continued) Alliance Den Org Volt Speed (ns) Cypress GSI IDT ISSI Samsung 128Kx8 AS7C31025B 1M 3.3V 10-20 CY7C1018CV33 GS71108A IDT71V124SA IS61LV1024 K6R1008V1D CPG AS7C1026B 1M 64Kx16 5V 10-20 CY7C1021B - IDT71016S IS61C6416 K6R1016C1D AS7C31026B 1M 64Kx16 3.3V 10-20 CY7C1021CV33 GS71116A IDT71V016SA IS61LV6416 K6R1016V1D AS7C4096A 4M 512Kx8 5V 12-20 CY7C1049B - - - K6R4008C1D AS7C34096A 4M 512Kx8 3.3V 10-20 CY7C1049CV33 GS74108A IDT71V424S IS61LV5128AL K6R4008V1D AS7C4098A 4M 256Kx16 5V 12-20 CY7C1041B - - - K6R4016C1D Product Guide 2004 AS7C34098A 4M 256Kx16 3.3V 10-20 CY7C1041CV33 GS74116A IDT71V416S IS61LV25616AL K6R4016V1D T=TSOP I/II Z=TSOP I/II PZ=TSOP I TS=TSOP I H=sTSOP I T=TSOP I/II V=300/400 mil SOJ PH=TSOP II Alliance Semiconductor package abbreviations and their equivalents. TP=TSOP II B=48-pin BGA E=48-pin BGA P=PDIP Y=400 mil SOJ T=TSOP I/II, TJ=300 mil SOJ, J=400 mil SOJ, ST=sTSOP I, CPG=Center power and ground SJ=300 mil SOJ M=48-pin mBGA J=300/400 mil SOJ B=48-pin BGA TY=300 mil SOJ C=Commercial, I=Industrial J=400 mil SOJ J=300 SOJ H=119 BGA BA=48-pin mBGA P=PDIP Notice: The information in this document is subject to change without notice. B=119 BGA K=400 SOJ D=PDIP BG=119 PBGA B=48-pin BGA N P or W=PDIP 57
58 Synchronous Dual Port SRAM Cross Reference Guide Alliance Den Org Volt (V) CLK (MHz) IDT AS9C25256M2036L 9M 256Kx36 3.3 133-166 IDT70T3519S AS9C25512M2018L 9M 512Kx18 3.3 133-166 IDT70T3339S Alliance Semiconductor package abbreviations and their equivalents. TQ=TQFP, B=BGA Product Guide 2004 Notice: The information in this document is subject to change without notice. www.alsc.com
2004 Product Guide

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2004 Product Guide

  • 2.
    DISCLAIMER Alliance Semiconductor Corporationreserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an Alliance Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Alliance Semiconductor Corporation. LIFE SUPPORT POLICY Alliance Semiconductor Corporation products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of Alliance Semiconductor. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Copyright 2004. All rights reserved NTD™ is a trademark of Alliance Semiconductor Corporation. HyperTransport™ is a trademark of the HyperTransport Technology Consortium.
  • 3.
    Table of Contents ANALOG AND MIXED SIGNAL PRODUCTS ................................................................................ 3 ANALOG AND MIXED SIGNAL PRODUCTS ......................................................................................... 4 CLOCK AND TIMING PRODUCTS ...................................................................................................... 5 Clock and Timing Product Selector Guide Alpha-Numeric Listing.......................................... 6 Clock and Timing Product Selector Guide Function and Configuration Listing ...................... 9 Zero Delay Buffers (ZDB) and Specialty Clock Management Cross Reference Guide........ 12 EMI Reduction Products Cross Reference Guide................................................................. 13 POWER AND SYSTEMS MANAGEMENT PRODUCTS .......................................................................... 14 CPU Supervisor Product Selector Guide .............................................................................. 15 CPU Supervisor Cross Reference Guide.............................................................................. 22 SYSTEM SOLUTIONS PRODUCTS............................................................................................. 27 CONNECTIVITY ............................................................................................................................. 29 HyperTransport™ Bridges Product Selector Guide .............................................................. 29 AS90L10204 HyperTransport™-to-PCI/PCI-X Bridge .......................................................... 30 AS90L10208 HyperTransport™-to-PCI/PCI-X Bridge .......................................................... 31 JTAG Controllers Product Selector Guide ............................................................................ 32 AS91L1001 JTAG Test Controller......................................................................................... 33 AS91L1002 JTAG Test Sequencer....................................................................................... 34 AS91L1003U 3-Port JTAG Gateway..................................................................................... 35 AS91L1006BU 6-Port JTAG Gateway .................................................................................. 36 NETWORKING .............................................................................................................................. 37 RPR Controllers Product Selector Guide.............................................................................. 37 AS95L210x Family of Resilient Packet Ring Controllers ...................................................... 38 MEMORY PRODUCTS.................................................................................................................. 43 SRAM PRODUCTS ....................................................................................................................... 44 Synchronous SRAM .............................................................................................................. 45 Asynchronous SRAM ............................................................................................................ 49 Synchronous SRAM Cross Reference Guide ....................................................................... 51 Fast Asynchronous SRAM Cross Reference Guide ............................................................. 56 Synchronous Dual Port SRAM Cross Reference Guide ....................................................... 58 www.alsc.com Product Guide 2004 1 Notice: The information in this document is subject to change without notice.
  • 4.
    2 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 5.
    ANALOG AND MIXEDSIGNAL PRODUCTS www.alsc.com Product Guide 2004 3 Notice: The information in this document is subject to change without notice.
  • 6.
    Analog and MixedSignal Products Alliance Semiconductor is a worldwide supplier of Analog and Mixed Signal Products in two main categories: Power and Systems Management, and Clock and Timing. • The Power and Systems Management Portfolio includes CPU Supervisor Products. These include products that feature POR (Power On Reset), WDT (Watch Dog Timers), LVS (Low Voltage Sense), BB (Battery Backup), brownout detect and control, and many more system and device level key functions. • The Clock and Timing Portfolio includes Frequency Synthesizers and Generators, Multipliers, Zero Delay Buffers, Distribution and Fan-out buffers. The EMI Reduction family of devices, a sub-segment of Clock and Timing, are made up of Frequency Synthesizer and Generators which are widely used in many designs today to reduce radiated emissions towards regulatory compliance. The EMI reduction family is noted for low cost, very low power consumption, very small package size options, and overall timing accuracy and performance. Fabricated in Low Voltage CMOS technologies, the Analog and Mixed Signal Product portfolio offers a full range of coverage, functions, options, and configurations, that provide flexibility in design and low cost. Power-On Reset PD MOD LF (ext loop filter) Application XIN/CLKIN Xtal Freq VDD OSC Divide XOUT PD Filter VCO DIV FBK uP Divider MOD_OUT ASM 809 RESET EMI Clock Synthesizer REF_OUT GND GND 4 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 7.
    Clock and TimingProducts Alliance Semiconductor provides in-depth coverage and support in Clock Management with cost effective, low power, Clock and Timing solutions that cater to the requirements for PC/Data processing applications and handhelds, high resolution LCD displays, DDR memory modules, consumer applications (MP3 players/recorders, games, etc.), networking, wireless, mobile applications and others. The Clock Management Solution family encompasses Clock and Frequency Generators, Frequency Multipliers, Zero Delay Buffers, and specific specialty solutions. High precision frequency multipliers provide 2x or 4x outputs of the input frequency up to 312 MHz, with higher frequencies to be offered in the near future. The depth of modulation, the profile (sinusoidal, triangular, non-linear), type of modulation and direction (center or down) are selectable from these Clock and Timing products. In addition, both modulated and unmodulated outputs are available. Many of the devices (single, dual and triple PLL based designs) feature a selection of output frequency derived from the input reference, along with the depth of modulation, type of modulation profile, and frequency of modulation through programming via I2C. A broad family of Zero Delay Buffers (ZDB) provide multiple low skew outputs of an input clock suitable for clock distribution applications, such as clocks to multiple PCI slots in a PC motherboard or SDRAM bank clocks. Available in 1:5 and 1:9 configurations with internal feedback or 1:4 and 1:8 configurations with external feedback, these Zero Delay Buffers provide relative skew among various outputs under controlled load conditions. Various drive options are also available to support one or two 50-ohm transmission lines. Clock and Timing products are designed to work with 2.5V, 3.3V, and 5V applications. Clock and Timing devices are found in applications such as workstations, servers, RAID arrays, notebook PCs, LCD high-resolution displays, PDA and hand held devices, automotive electronics, battery-driven entertainment systems, and others. www.alsc.com Product Guide 2004 5 Notice: The information in this document is subject to change without notice.
  • 8.
    Clock and TimingProduct Selector Guide Alpha-Numeric Listing Industrial Automotive Other PKG Part Number SOIC TSSOP Product Description (-40°C to +85°C) (-40°C to +125°C) options AS80M2180 YES - YES YES - EMI REDUCTION ASM3P1819N YES - YES YES - EMI REDUCTION ASM3P2180A-D YES - YES YES - EMI REDUCTION ASM3P2182A-D YES - YES YES - EMI REDUCTION ASM3P2183A-D YES - YES YES - EMI REDUCTION ASM3P2184A-D YES - YES YES - EMI REDUCTION ASM3P2185A-D YES - YES YES - EMI REDUCTION Very Low Power EMI ASM3P2779A YES - YES YES 6 TSOT23 REDUCTION ASM3P2811A YES - YES YES - EMI REDUCTION ASM3P2812A YES - YES YES - EMI REDUCTION ASM3P2814A YES - YES YES - EMI REDUCTION ASM3P2821B YES - YES YES - EMI REDUCTION ASM3P5821A YES - YES YES - EMI REDUCTION ASM3X2105A YES YES YES YES - EMI REDUCTION DDR I REGISTER - ASM4SSTVF16857 Extended Commercial* - - YES TVSOP PLANAR DDR I REGISTER - ASM4SSTVF16859 Extended Commercial* - - YES MLF TVSOP STACKED DDR I REGISTER - ASM4SSTVF32852 Extended Commercial* - - - LFBGA STACKED ASM5CVF857 Extended Commercial* - - YES MLF/BGA DDR I (to DDR 400) ZDB ASM5P2304A-1 YES - YES YES - ZDB 15-133 MHz ASM5P2304A-1H YES - YES YES - ZDB 15-133 MHz ASM5P2304A-2 YES - YES YES - ZDB 15-133 MHz ASM5P2304A-2H YES - YES YES - ZDB 15-133 MHz ASM5P2304A-5H YES - YES YES - ZDB 15-133 MHz ASM5P2304B-1 YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2304B-1H YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2304B-2 YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2304B-2H YES - YES YES - Low Freq ZDB (4-25 MHz) ASM5P2305A-1 YES - YES YES - ZDB 15-133 MHz All products are available in Commercial (0°C to +70°C). * Extended Commercial = 0°C to +85°C 6 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 9.
    Clock and TimingProduct Selector Guide Alpha-Numeric Listing Industrial Automotive Other PKG Part Number SOIC TSSOP Product Description (-40°C to +85°C) (-40°C to +125°C) options ASM5P2305A-1H YES - YES YES - ZDB 15-133 MHz ASM5P2308A-1 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-1H YES - YES YES - ZDB 15-133 MHz ASM5P2308A-2 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-3 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-4 YES - YES YES - ZDB 15-133 MHz ASM5P2308A-5H YES - YES YES - ZDB 15-133 MHz ASM5P2309A-1 YES - YES YES - ZDB 15-133 MHz ASM5P2309A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-2 YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-2H YES - YES YES - ZDB 15-133 MHz ASM5P23S04A-5H YES - YES YES - ZDB 15-133 MHz ASM5P23S05A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S05A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-1H YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-2 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-3 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-4 YES - YES YES - ZDB 15-133 MHz ASM5P23S08A-5H YES - YES YES - ZDB 15-133 MHz ASM5P23S09A-1 YES - YES YES - ZDB 15-133 MHz ASM5P23S09A-1H YES - YES YES - ZDB 15-133 MHz L2042A YES - YES YES - EMI REDUCTION (Low Voltage) P1707A YES - YES YES - EMI REDUCTION P1708C YES - YES YES - EMI REDUCTION P1817A-B YES - YES YES - EMI REDUCTION P1819A-B YES - YES YES - EMI REDUCTION All products are available in Commercial (0°C to +70°C). www.alsc.com Product Guide 2004 7 Notice: The information in this document is subject to change without notice.
  • 10.
    Clock and TimingProduct Selector Guide Alpha-Numeric Listing Industrial Automotive Other PKG Part Number SOIC TSSOP Product Description (-40°C to +85°C) (-40°C to +125°C) options P2005A YES YES YES YES - EMI REDUCTION P2005S YES YES YES YES - EMI REDUCTION P2008A YES - YES YES - EMI REDUCTION P2010A YES YES YES YES - EMI REDUCTION P2027A YES - YES YES - EMI REDUCTION P2040A YES - YES YES - EMI REDUCTION P2040C YES - YES YES - EMI REDUCTION P2041A YES - YES YES - EMI REDUCTION P2042A YES - YES YES - EMI REDUCTION P2082A YES - YES YES - FREQUENCY MULTIPLIER P2084A YES - YES YES - FREQUENCY MULTIPLIER P2160A YES - YES YES - EMI REDUCTION P2681A YES - YES YES - EMI REDUCTION P2779A YES - YES YES - EMI REDUCTION P2781A YES - YES YES - EMI REDUCTION P2782A YES - YES YES - EMI REDUCTION P2784A YES - YES YES - EMI REDUCTION P2811A YES - YES YES - EMI REDUCTION P2812A YES - YES YES - EMI REDUCTION P2814A YES - YES YES - EMI REDUCTION All products are available in Commercial (0°C to +70°C). 8 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 11.
    Clock and TimingProduct Selector Guide Function and Configuration Listing Frequency Output Fout_MAX Reference ModOut Xtal Supply Part Number Range (Fin) in Frequency Package in MHz Output Scaling Osc Voltage MHz Deviation (%) Input Frequency Range 6 MHz to 210 MHz 8 SOIC AS80M2180 6-30 30 -1.25% or 4.0% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P1819N 20-40 40 -1.25% YES 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2180A-D 6-36 36 +/-0.625 to -3.5% - 1X - 3.0 to 3.6 8 TSSOP +/-0.13 to 8 SOIC ASM3P2182A-D 25-210 210 - 1X - 3.0 to 3.6 +/-1.24% 8 TSSOP 8 SOIC ASM3P2183A-D 6-103 103 +/-0.625 to -3.6% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2184A-D 10-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP +/-0.625 to 8 SOIC ASM3P2185A-D 25-50 50 - 1X - 3.0 to 3.6 -1.25% 8 TSSOP 8 SOIC ASM3P2779A 15-30 38 +/-1% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2811A 10-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2812A 10-40 80 +/-0.625 to -3.5% - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2814A 10-40 160 +/-0.625 to -3.5% - 4X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P2821B 15-27 27 -2.5% YES 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM3P5821A 20-40 34 -1.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC ASM3X2105A 6-10 10 +/-1% - 1X, ½X YES 3.0 to 3.6 8 TSSOP +/-1.25 to 8 SOIC P1817A-B 10-32 32 YES 1X YES 3.0 to 3.6 +/-1.50% 8 TSSOP 8 SOIC P1819A-B 20-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2005A 8-32 32 +/-1.0 to +/-3.0% - 1X, ½X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2005S 8-32 32 +/-0.6 to +/-1.8% - 1X, ½X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2008A 4-32 32 +/-0.8 to +/-3.2% YES 1X, ½X YES 2.9 to 5.5 8 TSSOP +/-1.25 to 8 SOIC P2010A 10-35 35 - 1X YES 3.0 to 3.6 +/-2.5% 8 TSSOP 8 SOIC P2027A 10-30 30 +/-0.2 to +/-0.6% - 1X YES 3.0 to 3.8 8 TSSOP +/-0.50 to 8 SOIC P2041A 25-60 60 - 1X - 2.7 to 5.5 +/-2.50% 8 TSSOP 8 SOIC P2681A 6-20 20 +/-0.4 to +/-5% - 1X, ½X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2811A-B 10-40 40 +/-0.625 to -3.5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2812A-B 10-40 80 +/-0.625 to -3.5% - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2814A-B 10-40 160 +/-0.625 to -3.5% - 4X YES 3.0 to 3.6 8 TSSOP Input Frequency Range 30 MHz to 175 MHz +/-0.50 to 2.25 to 8 SOIC L2042A 30-75 75 - 1X - +/-2.00% 3.7 8 TSSOP +/-0.25 to 8 SOIC P1708C 60-175 175 - 1X - 3.0 to 3.6 +/-2.00% 8 TSSOP www.alsc.com Product Guide 2004 9 Notice: The information in this document is subject to change without notice.
  • 12.
    Clock and TimingProduct Selector Guide Function and Configuration Listing Frequency Output Fout_MAX Reference ModOut Xtal Supply Part Number Range (Fin) in Frequency Package in MHz Output Scaling Osc Voltage MHz Deviation (%) Input Frequency Range 30 MHz to 175 MHz (Continued) 8 SOIC P2040A 30-110 110 +/-0.7 to +/-2.0% - 1X - 3.0 to 3.6 8 TSSOP +/-0.20 to 8 SOIC P2042A 30-110 110 - 1X - 3.0 to 3.6 +/-2.00% 8 TSSOP Wide Input Frequency Range Devices +/-0.5 to 8 SOIC P1707A 60-175 175 - 1X - 3.0 to 3.6 +/-2.50% 8 TSSOP 8 SOIC P2040C 50-175 175 +/-0.4 to +/-2.2% - 1X - 3.0 to 3.6 8 TSSOP +/-0.50 to 8 SOIC P2160A 40-166 166 - 1X - 3.0 to 3.6 +/-1.00% 8 TSSOP 8 SOIC P2781A-B 3-78 78 +/-0.25 to +/-5% - 1X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2782A-B 3-78 156 +/-0.25 to +/-5% - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2784A-B 3-78 312 +/-0.25 to +/-5% - 4X YES 3.0 to 3.6 8 TSSOP High Precision Frequency Multipliers 8 SOIC P2082A 3-78 156 - - 2X YES 3.0 to 3.6 8 TSSOP 8 SOIC P2084A 3-78 312 - - 4X YES 3.0 to 3.6 8 TSSOP Specialty Clock Management DDR 1 JEDEC 48 TSSOP ASM4SSTVF16857 Compliant 14-bit 250 - - - - 2.3 to 2.7 TVSOP Register - Planar DDR 1 JEDEC 64 TSSOP ASM4SSTVF16859 Compliant 13/26-bit 250 - - - - 2.3 to 2.7 56 MLF Register - Stacked DDR 1 JEDEC 114 ASM4SSTVF32852 Compliant 14/28-bit 250 - - - - 2.3 to 2.7 LFBGA Register - Stacked DDR 1 – DDR 333 48 TSSOP – DDR 400 ASM5CVF857 250 -0.5% YES 1X - 2.3 to 2.7 40 MLF JEDEC Compliant 56 BGA ZDB Zero Delay Buffers 8 SOIC ASM5P2304A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P2304A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304A-2 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304A-2H 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 8 SOIC ASM5P2304B-1 4-25 25 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P2304B-1H 4-25 25 - - 1X - 3.0 to 3.6 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304B-2 4-25 50 - - - 3.0 to 3.6 ½X 8 TSSOP 1X, 2X, 8 SOIC ASM5P2304B-2H 4-25 50 - - - 3.0 to 3.6 ½X 8 TSSOP 10 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 13.
    Clock and TimingProduct Selector Guide Function and Configuration Listing Frequency Output Fout_MAX Reference ModOut Xtal Supply Part Number Range (Fin) in Frequency Package in MHz Output Scaling Osc Voltage MHz Deviation (%) 8 SOIC ASM5P2305A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P2305A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 16 SOIC ASM5P2308A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2308A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 1X, 2X, 16 SOIC ASM5P2308A-2 15-133 133 - - - 3.0 to 3.6 ½X 16 TSSOP 16 SOIC ASM5P2308A-3** 15-133 133 - - 2X, 4X - 3.0 to 3.6 TSSOP 16 SOIC ASM5P2308A-4 15-133 133 - - 2X, 2X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2308A-5H 15-133 133 - - ½X, ½X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2309A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P2309A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 8 SOIC ASM5P23S04A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P23S04A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 1X, 2X, 8 SOIC ASM5P23S04A-2 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 1X, 2X, 8 SOIC ASM5P23S04A-2H 15-133 133 - - - 3.0 to 3.6 ½X 8 TSSOP 8 SOIC ASM5P23S04A-5H 15-133 133 - - ½X, ½X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P23S05A-1 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 8 SOIC ASM5P23S05A-1H 15-133 133 - - 1X - 3.0 to 3.6 8 TSSOP 16 SOIC ASM5P23S08A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S08A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 1X, 2X, 16 SOIC ASM5P23S08A-2 15-133 133 - - - 3.0 to 3.6 ½X 16 TSSOP 16 SOIC ASM5P23S08A-3** 15-133 133 - - 2X, 4X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S08A-4 15-133 133 - - 2X, 2X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S08A-5H 15-133 133 - - ½X, ½X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S09A-1 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP 16 SOIC ASM5P23S09A-1H 15-133 133 - - 1X - 3.0 to 3.6 16 TSSOP ** Output phase is indeterminant from INPUT REF. If needed in phase, use the –2 version. www.alsc.com Product Guide 2004 11 Notice: The information in this document is subject to change without notice.
  • 14.
    Zero Delay Buffers(ZDB) and Specialty Clock Management Cross Reference Guide Alliance TI Cypress ICS IDT Pericom ASM4SSTVF16857 SN74SSTVF16857 CY2SSTV16857 ICSSSTVF16857 IDT74SSTV16857 PI74SSTVF16857 ASM4SSTVF16859 SN74SSTVF16859 CY2SSTV16859 ICSSSTVF16859 IDT74SSTV16859 PI74SSTVF16859 ASM4SSTVF32582 SN74SSTVF32852 CY2SSTV32852 ICSSSTVF32852 IDT74SSTV32852 PI74SSTVF32852 ASM5PCVF857 CDCVF857 CY2SSTV857-32 ICS95V857 IDTCSPT857C PI6CVF857 ASM5P2304A-1 - CY2304-1 - - - ASM5P2304A-2 - CY2304-2 - - - ASM5P2304B-1 - CY2304-1 - - - ASM5P2304B-2 - CY2304-2 - - - ASM5P2305A-1 - CY2305-1 - IDT2305-1 PI6C2408-1 ASM5P2305A-1H - CY2305-H1 - IDT2305-1H PI6C2408-1H ASM5P2308A-1 - CY2308-1 MK2308S-1 IDT2308-1 PI6C2408-1 ASM5P2308A-1H - CY2308-1H MK2308S-1H IDT2308-1H PI6C2408-1H ASM5P2308A-2 - CY2308-2 - IDT2308-2 PI6C2408-2 ASM5P2308A-3 - CY2308-3 - IDT2308-3 PI6C2408-3 ASM5P2308A-4 - CY2308-4 - IDT2308-4 PI6C2408-4 ASM5P2308A-5H - CY2308-5H - IDT2308-5H - ASM5P2309A-1 - CY2309 - IDT2309 - ASM5P2309A-1H - CY2309-1H - IDT2309-1H - ASM5P23S05A-1 - CY23S05 - IDT23S05 PI6C2405A-1 ASM5P23S05A-1H - CY23S05-1H - IDT23S05-1H PI6C2405A-1H ASM5P23S08A-1 - CY23S08-1 - IDT23S08-1 PI6C2408-1 ASM5P23S08A-1H - CY230S8-1H - IDT23S08-1H PI6C2408-1H ASM5P23S08A-2 - CY23S08-2 - IDT23S08-2 PI6C2408-2 ASM5P23S08A-3 - CY23S08-3 - IDT23S08-3 PI6C2408-3 ASM5P23S08A-4 - CY23S08-4 - IDT23S08-4 PI6C2408-4 ASM5P23S08A-5H - CY23S08-5H - IDT23S08-5H - ASM5P23S09A-1H - CY23S09-1H - IDT23S09-1H PI62409-1H ASM5P23S09A-1 - CY23S09-1 - IDT23S09 PI62409-1 Note: Alliance offers both SOIC & TSSOP, industrial or commercial temperature grades, and STD or lead-free package options for all devices listed. 12 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 15.
    EMI Reduction ProductsCross Reference Guide Alliance Input Frequency Cypress Output Frequency Mobile Modulation Frequency Selection Part Frequency Selection Graphic Part Number Type (in MHz) Needed Number (in MHz) Needed Frequency AS80M2180 6-30 NO Down, Center W180/180i 8-28 4 ranges 27 MHz Source ASM3P1819N 20-40 NO Down, Center CY25819 20-40 - 27 MHz Source ASM3P2779A 20-38 NO Center - - - 27 MHz Source ASM3P2811A 10-40 2 ranges Down, Center CY25811 10-40 3 ranges - ASM3P2812A 10-40 2 ranges Down, Center CY25812 20-80 3 ranges - ASM3P2814A 10-40 2 ranges Down, Center CY25814 40-160 3 ranges - ASM3P2821B 15-27 NO Down CY25811 4-32 3 ranges - ASM3P5821A 20-40 NO Down CY25811 4-32 3 ranges - LVDS Frequencies 65 MHz (XGA), P1707A 60-175 NO Center SM561 54-166 10 ranges 108 MHz (SXGA), and 162 MHz (UXGA) LVDS Frequencies P1708C 50-110 NO Center SM560 25-108 10 ranges 65 MHz (XGA), 108 MHz (SXGA) P1819A-H 20-40 NO Down, Center CY25819 16-32 4 ranges 27 MHz Source LVDS Frequencies 65 MHz (XGA), P2040C 60-175 NO Center - - - 108 MHz (SXGA), and 162 MHz (UXGA) P2781A 3-78 4 ranges Center FS781 SOIC 6-82 4 ranges 25 MHz Source FS781 P2781B 3-78 4 ranges Center TSSOP 6-82 4 ranges 27 MHz Source P2782A 3-78 4 ranges Center FS782 SOIC 6-66 4 ranges - FS782 P2782B 3-78 4 ranges Center TSSOP 6-66 4 ranges - P2784A 3-78 4 ranges Center FS784 SOIC 6-32 4 ranges - FS784 P2784B 3-78 4 ranges Center TSSOP 6-32 4 ranges - www.alsc.com Product Guide 2004 13 Notice: The information in this document is subject to change without notice.
  • 16.
    Power and SystemsManagement Products CPU Supervisor Products Alliance Semiconductor provides cost effective, low power, Supervisor products that are an essential part of the 5V/3.3V/3V system providing active low and active high reset inputs to microprocessors, microcontrollers, ASICs, ASSPs, and digital systems. These Supervisor products initialize the systems into a known state and avoid malfunctioning of systems during power-up, power-down, power control, and brownout conditions, thus eliminating the possibility of code corruption. The CPU Supervisor Products also feature edge triggered and level triggered manual reset inputs. These enable the users to connect an external contact switch to generate a reset. This typically would be used as an alternative to operator intervention in systems that require reset. An early warning to the system controller about the impending system power failure, provided through the power fail input, enables the saving of essential system parameters. A Watch Dog Timer (WDT) is another useful feature that monitors and restarts a system processor. These are typically used as time out devices to force a system out of software “endless loop”. The reset outputs on the CPU Supervisor Products are available in Open Drain (OD) or Push Pull (PP) configurations to suit the user requirements. Various threshold voltage options are available on the supervisor devices, 4.63V, 4.38V, 4.00V, 3.08V, 2.93V, and 2.63V, which support 5%, 10%, and 20% system voltage tolerances. Reset timeout period options such as 140ms, 300 ms, and 800 ms cater to different system requirements. Dual power supply monitoring is a highly useful feature that is essential in the design of one core supply and IO supply systems. This system architecture is gaining wide acceptance. The CPU and System Supervisor Products are available in industry standard, space saving packages such as SOT-23, SOT-143, SO-8, and Micro SO in commercial and industrial temperature range. Supervisor devices are found in computers, embedded systems, portable and battery operated systems, notebook PCs, cellular phones, safety systems, automotive systems, wireless communication systems, PDAs, printers, set top boxes, intelligent systems and others. 14 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 17.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP CPU Supervisors with Selectable Trip-point Tolerance, Watchdog timer with POR ASM1232LP 4.5-5.5 Vt1 T1 - X - X X L X X 8P-DIP ASM1232LPCMA 4.5-5.5 Vt1 T1 - X - X X L X X 8-MicroSO ASM1232LPEMA 4.5-5.5 Vt1 T2 - X - X X L X X 8-MicroSO ASM1232LPN 4.5-5.5 Vt1 T2 - X - X X L X X 8P-DIP ASM1232LPS 4.5-5.5 Vt1 T1 - X - X X L X X 16-SO ASM1232LPS-2 4.5-5.5 Vt1 T1 - X - X X L X X 8-SO ASM1232LPSN 4.5-5.5 Vt1 T2 - X - X X L X X 16-SO ASM1232LPSN-2 4.5-5.5 Vt1 T2 - X - X X L X X 8-SO ASM1832 1.0-5.5 Vt1 T2 - X - X X L - X 8P-DIP ASM1832EMA 1.0-5.5 Vt1 T2 - X - X X L - X 8-MicroSO ASM1832S 1.0-5.5 Vt1 T2 - X - X X L - X 8-SO CPU Supervisors with POR, Edge Triggered MR ASM161JEUS 1.1-5.5 4 T2 - - - X - ↓ X - 4L-SOT143 ASM161LEUS 1.1-5.5 4.63 T2 - - - X - ↓ X - 4L-SOT143 ASM161MEUS 1.1-5.5 4.38 T2 - - - X - ↓ X - 4L-SOT143 ASM161REUS 1.1-5.5 2.63 T2 - - - X - ↓ X - 4L-SOT143 ASM161SEUS 1.1-5.5 2.93 T2 - - - X - ↓ X - 4L-SOT143 ASM161TEUS 1.1-5.5 3.08 T2 - - - X - ↓ X - 4L-SOT143 ASM162JEUS 1.1-5.5 4 T2 - - - - - ↓ - X 4L-SOT143 ASM162LEUS 1.1-5.5 4.63 T2 - - - - - ↓ - X 4L-SOT143 ASM162MEUS 1.1-5.5 4.38 T2 - - - - - ↓ - X 4L-SOT143 ASM162REUS 1.1-5.5 2.63 T2 - - - - - ↓ - X 4L-SOT143 ASM162SEUS 1.1-5.5 2.93 T2 - - - - - ↓ - X 4L-SOT143 ASM162TEUS 1.1-5.5 3.08 T2 - - - - - ↓ - X 4L-SOT143 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. www.alsc.com Product Guide 2004 15 Notice: The information in this document is subject to change without notice.
  • 18.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP Low Power CPU Supervisors ASM1233DZ-10 1.2-5.5 4.375 T2 - - - X - - X - 4L-SOT223 ASM1233AZ-15 1.2-5.5 2.72 T2 - - - X - - X - 4L-SOT223 ASM1233DZ-15 1.2-5.5 4.125 T2 - - - X - - X - 4L-SOT223 ASM1233DZ-5 1.2-5.5 4.625 T2 - - - X - - X - 4L-SOT223 ASM1233MS-3 1.2-5.5 2.72 T2 - - - X - - X - 8-SO ASM1233MS-5 1.2-5.5 4.375 T2 - - - X - - X - 8-SO ASM1233MS-55 1.2-5.5 4.625 T2 - - - X - - X - 8-SO ASM1810R-10 1.2-5.5 4.37 T2 - - - X - - - X 3L-SOT23 ASM1810R-15 1.2-5.5 4.12 T2 - - - X - - - X 3L-SOT23 ASM1810R-5 1.2-5.5 4.62 T2 - - - X - - - X 3L-SOT23 ASM1811R-10 1.2-5.5 4.35 T2 - - - X - - X - 3L-SOT23 ASM1811R-15 1.2-5.5 4.13 T2 - - - X - - X - 3L-SOT23 ASM1811R-5 1.2-5.5 4.62 T2 - - - X - - X - 3L-SOT23 ASM1812R-10 1.2-5.5 4.35 T2 - - - - X - - X 3L-SOT23 ASM1812R-15 1.2-5.5 4.13 T2 - - - - X - - X 3L-SOT23 ASM1812R-5 1.2-5.5 4.62 T2 - - - - X - - X 3L-SOT23 ASM1815R-10 1.2-5.5 2.88 T2 - - - X - - - X 3L-SOT23 ASM1815R-20 1.2-5.5 2.55 T2 - - - X - - - X 3L-SOT23 ASM1815R-5 1.2-5.5 3.06 T2 - - - X - - - X 3L-SOT23 ASM1816R-10 1.2-5.5 2.88 T2 - - - X - - X - 3L-SOT23 ASM1816R-20 1.2-5.5 2.55 T2 - - - X - - X - 3L-SOT23 ASM1816R-5 1.2-5.5 3.06 T2 - - - X - - X - 3L-SOT23 ASM1817R-10 1.2-5.5 2.88 T2 - - - - X - - X 3L-SOT23 ASM1817R-20 1.2-5.5 2.55 T2 - - - - X - - X 3L-SOT23 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. 16 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 19.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM1817R-5 1.2-5.5 3.06 T2 - - - - X - - X 3L-SOT23 ASM8500-27 1.0-5.5 2.7 T2 - - - X - - X - 3L-SOT89 ASM8500-29 1.0-5.5 2.93 T2 - - - X - - X - 3L-SOT89 ASM8500-42 1.0-5.5 4.2 T2 - - - X - - X - 3L-SOT89 CPU Supervisors with Dual Supply Monitoring, Selectable Threshold ASM1834 1.2-5.5 Vt2 T2 - - - X - L - X 8P-DIP ASM1834A 1.2-5.5 Vt2 T2 - - - X - L X X 8P-DIP ASM1834AEMA 1.2-5.5 Vt2 T2 - - - X - L X X 8-MicroSO ASM1834AS 1.2-5.5 Vt2 T2 - - - X - L X X 8-SO ASM1834D 1.2-5.5 Vt2 T2 - - - - X L X X 8P-DIP ASM1834DEMA 1.2-5.5 Vt2 T2 - - - - X L - X 8-MicroSO ASM1834DS 1.2-5.5 Vt2 T2 - - - - X L - X 8-SO ASM1834EMA 1.2-5.5 Vt2 T2 - - - X - L - X 8-MicroSO ASM1834S 1.2-5.5 Vt2 T2 - - - X - L - X 8-SO CPU Supervisors with Watchdog Timer, Battery Backup, and Power Fail Detector ASM690ACPA 1.1-5.5 4.65 T1 X X X X - - - X 8P-DIP ASM690ACSA 1.1-5.5 4.65 T1 X X X X - - - X 8-SO ASM690AEPA 1.1-5.5 4.65 T2 X X X X - - - X 8P-DIP ASM690AESA 1.1-5.5 4.65 T2 X X X X - - - X 8-SO ASM692ACPA 1.1-5.5 4.4 T1 X X X X - - - X 8P-DIP ASM692ACSA 1.1-5.5 4.4 T1 X X X X - - - X 8-SO ASM692AEPA 1.1-5.5 4.4 T2 X X X X - - - X 8P-DIP ASM692AESA 1.1-5.5 4.4 T2 X X X X - - - X 8-SO ASM802LCPA 1.1-5.5 4.65 T1 X X X X - - - X 8P-DIP ASM802LCSA 1.1-5.5 4.65 T1 X X X X - - - X 8-SO ASM802LEPA 1.1-5.5 4.65 T2 X X X X - - - X 8P-DIP ASM802LESA 1.1-5.5 4.65 T2 X X X X - - - X 8-SO ASM802MCPA 1.1-5.5 4.4 T1 X X X X - - - X 8P-DIP ASM802MCSA 1.1-5.5 4.4 T1 X X X X - - - X 8-SO ASM802MEPA 1.1-5.5 4.4 T2 X X X X - - - X 8P-DIP Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. www.alsc.com Product Guide 2004 17 Notice: The information in this document is subject to change without notice.
  • 20.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM802MESA 1.1-5.5 4.4 T2 X X X X - - - X 8-SO ASM805LCPA 1.1-5.5 4.65 T1 X X X - X - - X 8P-DIP ASM805LCSA 1.1-5.5 4.65 T1 X X X - X - - X 8-SO ASM805LEPA 1.1-5.5 4.65 T2 X X X - X - - X 8P-DIP ASM805LESA 1.1-5.5 4.65 T2 X X X - X - - X 8-SO CPU Supervisors with Watchdog Timer and Power Fail Detector ASM705CPA 1.2-5.5 4.65 T1 X X - X - L - X 8P-DIP ASM705CSA 1.2-5.5 4.65 T1 X X - X - L - X 8-SO ASM705CUA 1.2-5.5 4.65 T1 X X - X - L - X 8-MicroSO ASM705EPA 1.2-5.5 4.65 T2 X X - X - L - X 8P-DIP ASM705ESA 1.2-5.5 4.65 T2 X X - X - L - X 8-SO ASM706CPA 1.2-5.5 4.4 T1 X X - X - L - X 8P-DIP ASM706CSA 1.2-5.5 4.4 T1 X X - X - L - X 8-SO ASM706CUA 1.2-5.5 4.4 T1 X X - X - L - X 8-MicroSO ASM706EPA 1.2-5.5 4.4 T2 X X - X - L - X 8P-DIP ASM706ESA 1.2-5.5 4.4 T2 X X - X - L - X 8-SO ASM706JCPA 1.1-5.5 4 T1 X X - X - L - X 8P-DIP ASM706JCSA 1.1-5.5 4 T1 X X - X - L - X 8-SO ASM706JCUA 1.1-5.5 4 T1 X X - X - L - X 8-MicroSO ASM706JEPA 1.2-5.5 4 T2 X X - X L - X 8P-DIP ASM706JESA 1.2-5.5 4 T2 X X - X - L - X 8-SO ASM706PCPA 1.1-5.5 2.63 T1 X X - X L - X 8P-DIP ASM706PCSA 1.1-5.5 2.63 T1 X X - X L - X 8-SO ASM706PCUA 1.1-5.5 2.63 T1 X X - X L - X 8-MicroSO ASM706PEPA 1.2-5.5 2.63 T2 X X - X L - X 8P-DIP ASM706PESA 1.2-5.5 2.63 T2 X X - X L - X 8-SO ASM706RCPA 1.1-5.5 2.63 T1 X X - X - L - X 8P-DIP ASM706RCSA 1.1-5.5 2.63 T1 X X - X - L - X 8-SO ASM706RCUA 1.1-5.5 2.63 T1 X X - X - L - X 8-MicroSO Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. 18 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 21.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM706REPA 1.2-5.5 2.63 T2 X X - X - L - X 8P-DIP ASM706RESA 1.2-5.5 2.63 T2 X X - X - L - X 8-SO ASM706SCPA 1.1-5.5 2.93 T1 X X - X - L - X 8P-DIP ASM706SCSA 1.1-5.5 2.93 T1 X X - X - L - X 8-SO ASM706SCUA 1.1-5.5 2.93 T1 X X - X - L - X 8-MicroSO ASM706SEPA 1.2-5.5 2.93 T2 X X - X - L - X 8P-DIP ASM706SESA 1.2-5.5 2.93 T2 X X - X - L - X 8-SO ASM706TCPA 1.1-5.5 3.08 T1 X X - X - L - X 8P-DIP ASM706TCSA 1.1-5.5 3.08 T1 X X - X - L - X 8-SO ASM706TCUA 1.1-5.5 3.08 T1 X X - X - L - X 8-MicroSO ASM706TEPA 1.2-5.5 3.08 T2 X X - X - L - X 8P-DIP ASM706TESA 1.2-5.5 3.08 T2 X X - X - L - X 8-SO ASM813LCPA 1.1-5.5 4.65 T1 X X - - X L - X 8P-DIP ASM813LCSA 1.1-5.5 4.65 T1 X X - - X L - X 8-SO ASM813LCUA 1.1-5.5 4.65 T1 X X - - X L - X 8-MicroSO ASM813LEPA 1.1-5.5 4.65 T2 X X - - X L - X 8P-DIP ASM813LESA 1.1-5.5 4.65 T2 X X - - X L - X 8-SO CPU Supervisors with Power Fail Detector ASM707CPA 1.2-5.5 4.65 T1 X - - X X L - X 8P-DIP ASM707CSA 1.2-5.5 4.65 T1 X - - X X L - X 8-SO ASM707CUA 1.2-5.5 4.65 T1 X - - X X L - X 8-MicroSO ASM707EPA 1.2-5.5 4.65 T2 X - - X X L - X 8P-DIP ASM707ESA 1.2-5.5 4.65 T2 X - - X X L - X 8-SO ASM708CPA 1.2-5.5 4.4 T1 X - - X X L - X 8P-DIP ASM708CSA 1.2-5.5 4.4 T1 X - - X X L - X 8-SO ASM708CUA 1.2-5.5 4.4 T1 X - - X X L - X 8-MicroSO ASM708EPA 1.2-5.5 4.4 T2 X - - X X L - X 8P-DIP ASM708ESA 1.2-5.5 4.4 T2 X - - X X L - X 8-SO ASM708JCPA 1.1-5.5 4 T1 X - - X X L - X 8P-DIP ASM708JCSA 1.1-5.5 4 T1 X - - X X L - X 8-SO ASM708JCUA 1.1-5.5 4 T1 X - - X X L - X 8-MicroSO ASM708JEPA 1.2-5.5 4 T2 X - - X X L - X 8P-DIP ASM708JESA 1.2-5.5 4 T2 X - - X X L - X 8-SO Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. www.alsc.com Product Guide 2004 19 Notice: The information in this document is subject to change without notice.
  • 22.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM708RCPA 1.1-5.5 2.63 T1 X - - X X L - X 8P-DIP ASM708RCSA 1.1-5.5 2.63 T1 X - - X X L - X 8-SO ASM708RCUA 1.1-5.5 2.63 T1 X - - X X L - X 8-MicroSO ASM708REPA 1.2-5.5 2.63 T2 X - - X X L - X 8P-DIP ASM708RESA 1.2-5.5 2.63 T2 X - - X X L - X 8-SO ASM708SCPA 1.1-5.5 2.93 T1 X - - X X L - X 8P-DIP ASM708SCSA 1.1-5.5 2.93 T1 X - - X X L - X 8-SO ASM708SCUA 1.1-5.5 2.93 T1 X - - X X L - X 8-MicroSO ASM708SEPA 1.2-5.5 2.93 T2 X - - X X L - X 8P-DIP ASM708SESA 1.2-5.5 2.93 T2 X - - X X L - X 8-SO ASM708TCPA 1.1-5.5 3.08 T1 X - - X X L - X 8P-DIP ASM708TCSA 1.1-5.5 3.08 T1 X - - X X L - X 8-SO ASM708TCUA 1.1-5.5 3.08 T1 X - - X X L - X 8-MicroSO ASM708TEPA 1.2-5.5 3.08 T2 X - - X X L - X 8P-DIP ASM708TESA 1.2-5.5 3.08 T2 X - - X X L - X 8-SO Low Power CPU Supervisors ASM809JEUR 1.2-5.5 4 T3 - - - X - - - X 3L-SOT23 ASM809LEUR 1.2-5.5 4.63 T3 - - - X - - - X 3L-SOT23 ASM809MEUR 1.2-5.5 4.38 T3 - - - X - - - X 3L-SOT23 ASM809REUR 1.2-5.5 2.63 T3 - - - X - - - X 3L-SOT23 ASM809SEUR 1.2-5.5 2.93 T3 - - - X - - - X 3L-SOT23 ASM809TEUR 1.2-5.5 3.08 T3 - - - X - - - X 3L-SOT23 ASM810JEUR 1.2-5.5 4 T3 - - - - X - - X 3L-SOT23 ASM810LEUR 1.2-5.5 4.63 T3 - - - - X - - X 3L-SOT23 ASM810MEUR 1.2-5.5 4.38 T3 - - - - X - - X 3L-SOT23 ASM810REUR 1.2-5.5 2.63 T3 - - - - X - - X 3L-SOT23 ASM810SEUR 1.2-5.5 2.93 T3 - - - - X - - X 3L-SOT23 ASM810TEUR 1.2-5.5 3.08 T3 - - - - X - - X 3L-SOT23 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. 20 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 23.
    CPU Supervisor ProductSelector Guide Specifications Features Alliance Part Number Batt Output Package Input Voltage (V) RST Vth (V) Temp PFD WDT Back MR Stage Min to Max up L H OD PP ASM811JEUS 1.2-5.5 4 T3 - - - X - L - X 4L-SOT143 ASM811LEUS 1.2-5.5 4.63 T3 - - - X - L - X 4L-SOT143 ASM811MEUS 1.2-5.5 4.38 T3 - - - X - L - X 4L-SOT143 ASM811REUS 1.2-5.5 2.63 T3 - - - X - L - X 4L-SOT143 ASM811SEUS 1.2-5.5 2.93 T3 - - - X - L - X 4L-SOT143 ASM811TEUS 1.2-5.5 3.08 T3 - - - X - L - X 4L-SOT143 ASM812JEUS 1.2-5.5 4 T3 - - - - X L - X 4L-SOT143 ASM812LEUS 1.2-5.5 4.63 T3 - - - - X L - X 4L-SOT143 ASM812MEUS 1.2-5.5 4.38 T3 - - - - X L - X 4L-SOT143 ASM812REUS 1.2-5.5 2.63 T3 - - - - X L - X 4L-SOT143 ASM812SEUS 1.2-5.5 2.93 T3 - - - - X L - X 4L-SOT143 ASM812TEUS 1.2-5.5 3.08 T3 - - - - X L - X 4L-SOT143 Legend: Vth = Threshold, PFD = Power Fail Detect, WDT = Watch Dog Timer, RST = Reset, MR = Manual Reset, OD = Open Drain, PP = Push Pull, T1 = 0°C to +70°C, T2 = -40°C to + 85°C, T3 = -40°C to +105°C, H = High, L = Low, ↓ = Edge Triggered, Vt1 = Selectable between 4.62V or 4.37V, Vt2 = Selectable between 4.63V or 4.38V, and 2.88V or 2.55V. All products in SOT-23 and SOT-143 package are only offered in Tape and Reel.To order parts in Tape and Reel,add “-T” to part number. www.alsc.com Product Guide 2004 21 Notice: The information in this document is subject to change without notice.
  • 24.
    CPU Supervisor CrossReference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM1232LP DS1232LPS-2 IMP1232LP MIC1232N TC1232CPA ASM1232LPCMA DS1232LPµ IMP1232LPCMA - - - ASM1232LPEMA DS1232LPµ IMP1232LPEMA - - - ASM1232LPN DS1232LP IMP1232LPN - MIC1232N TC1232EPA ASM1232LPS DS1232LPS IMP1232LPS - - TC1232COE ASM1232LPS-2 DS1232LPSN-2 IMP1232LPS-2 - MIC1232M TC1232COA ASM1232LPSN DS1232LPS IMP1232LPSN - - TC1232EOE ASM1232LPSN-2 DS1232LPSN-2 IMP1232LPSN-2 - MIC1232M TC1232EOA ASM1233AZ-15 DS1233A-15 - - - - ASM1233DZ-5 DS1233DZ-5 IMP1233DZ-5 - - - ASM1233DZ-10 DS1233DZ-10 IMP1233DZ-10 - - - ASM1233DZ-15 DS1233DZ-15 IMP1233DZ-15 - - - ASM1233MS-55 DS1233MS-55 IMP1233MS-55 - - - ASM1233MS-5 DS1233MS-5 IMP1233MS-5 - - - ASM1233MS-3 DS1233MS-3 IMP1233MS-3 - - - ASM161JEUS MAX6467US40 IMP161JEUS - - - ASM161LEUS MAX6467US46 IMP161LEUS - - - ASM161MEUS MAX6467US44 IMP161MEUS - - - ASM161REUS MAX6467US26 IMP161REUS - - - ASM161SEUS MAX6467US29 IMP161SEUS - - - ASM161TEUS MAX6467US31 IMP161TEUS - - - ASM162JEUS - IMP162JEUS - - - ASM162LEUS - IMP162LEUS - - - ASM162MEUS - IMP162MEUS - - - ASM162REUS - IMP162REUS - - - ASM162SEUS - IMP162SEUS - - - ASM162TEUS - IMP162TEUS - - - ASM1810R-5 DS1810R-5 IMP1810R-5 - MIC1810-5U TC1272-5 ASM1810R-10 DS1810R-10 IMP1810R-10 - MIC1810-10U TC1272-10 ASM1810R-15 DS1810R-15 IMP1810R-15 - MIC1810-15U TC1272-15 ASM1811R-5 DS1811R-5 IMP1811R-5 - - - ASM1811R-10 DS1811R-10 IMP1811R-10 - - - ASM1811R-15 DS1811R-15 IMP1811R-15 - - - ASM1812R-5 DS1812R-5 IMP1812R-5 - - TC1274-5 ASM1812R-10 DS1812R-10 IMP1812R-10 - - TC1274-10 ASM1812R-15 DS1812R-15 IMP1812R-15 - - TC1274-15 ASM1815R-5 DS1815R-5 IMP1815R-5 - MIC1815-5U TC1275-5 ASM1815R-10 DS1815R-10 IMP1815R-10 - MIC1815-10U TC1275-10 ASM1815R-20 DS1815R-20 IMP1815R-20 - MIC1815-20U TC1275-20 ASM1816R-5 DS1816R-5 IMP1816R-5 - - TC1276-5 ASM1816R-10 DS1816R-10 IMP1816R-10 - - TC1276-10 ASM1816R-20 DS1816R-20 IMP1816R-20 - - TC1276-20 22 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 25.
    CPU Supervisor CrossReference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM1817R-5 DS1817R-5 IMP1817R-5 - - TC1277-5 ASM1817R-10 DS1817R-10 IMP1817R-10 - - TC1277-10 ASM1817R-20 DS1817R-20 IMP1817R-20 - - TC1277-20 ASM1832 DS1832 IMP1832 - MIC1832N - ASM1832EMA DS1832UN IMP1832EMA - - - ASM1832S DS1832S IMP1832S - MIC1832M - ASM1834 DS1834 IMP1834 - - - ASM1834A DS1834CMA IMP1834A - - - ASM1834AEMA DS1834AU IMP1834AEMA - - - ASM1834AS DS1834ASM IMP1834AS - - - ASM1834D DS1834D IMP1834D - - - ASM1834DEMA DS1834DU IMP1834DEMA - - - ASM1834DS DS1834DS IMP1834DS - - - ASM1834EMA DS1834U IMP1834EMA - - - ASM1834S DS1834S IMP1834S - - - ASM690ACPA MAX690ACPA IMP690ACPA ADM690AAN - - ASM690ACSA MAX690ACSA IMP690ACSA ADM690AARN - - ASM690AEPA MAX690AEPA IMP690AEPA ADM690AAN - - ASM690AESA MAX690AESA IMP690AESA ADM690AARN - - ASM692ACPA MAX692ACPA IMP692ACPA ADM692AAN - - ASM692ACSA MAX692ACSA IMP692ACSA ADM692AARN - - ASM692AEPA MAX692AEPA IMP692AEPA ADM692AAN - - ASM692AESA MAX692AESA IMP692AESA ADM692AARN - - ASM705CPA MAX705CPA IMP705CPA ADM705AN MIC705N - ASM705CSA MAX705CSA IMP705CSA ADM705AR MIC705M - ASM705CUA MAX705CUA IMP705CUA - - - ASM705EPA MAX705EPA IMP705EPA ADM705AN MIC705N - ASM705ESA MAX705ESA IMP705ESA ADM705AR MIC705M - ASM706CPA MAX706CPA IMP706CPA ADM706AN MIC706N - ASM706CSA MAX706CSA IMP706CSA ADM706AR MIC706M - ASM706CUA MAX706CUA IMP706CUA - - - ASM706EPA MAX706EPA IMP706EPA ADM706AN MIC706N - ASM706ESA MAX706ESA IMP706ESA ADM706AR MIC706M - ASM706JCPA MAX706JCPA IMP706JCPA - - - ASM706JCSA MAX706JCSA IMP706JCSA - - - ASM706JCUA MAX706JCUA IMP706JCUA - - - ASM706JEPA MAX706JEPA IMP706JEPA - - - ASM706JESA MAX706JESA IMP706JESA - - - ASM706PCPA MAX706PCPA IMP706PCPA ADM706PAN MIC706PN - ASM706PCSA MAX706PCSA IMP706PCSA ADM706PAR MIC706PM - ASM706PCUA MAX706PCUA IMP706PCUA - - - ASM706PEPA MAX706PEPA IMP706PEPA ADM706PAN MIC706PN - ASM706PESA MAX706PESA IMP706PESA ADM706PAR MIC706PM - www.alsc.com Product Guide 2004 23 Notice: The information in this document is subject to change without notice.
  • 26.
    CPU Supervisor CrossReference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM706RCPA MAX706RCPA IMP706RCPA ADM706RAN MIC706RN - ASM706RCSA MAX706RCSA IMP706RCSA ADM706RAR MIC706RM - ASM706RCUA MAX706RCUA IMP706RCUA - - - ASM706REPA MAX706REPA IMP706REPA ADM706RAN MIC706RN - ASM706RESA MAX706RESA IMP706RESA ADM706RAR MIC706RM - ASM706SCPA MAX706SCPA IMP706SCPA ADM706SAN MIC706SN - ASM706SCSA MAX706SCSA IMP706SCSA ADM706SAR MIC706SM - ASM706SCUA MAX706SCUA IMP706SCUA - - - ASM706SEPA MAX706SEPA IMP706SEPA ADM706SAN MIC706SN - ASM706SESA MAX706SESA IMP706SESA ADM706SAR MIC706SM - ASM706TCPA MAX706TCPA IMP706TCPA ADM706TAN MIC706TN - ASM706TCSA MAX706TCSA IMP706TCSA ADM706TAR MIC706TM - ASM706TCUA MAX706TCUA IMP706TCUA - - - ASM706TEPA MAX706TEPA IMP706TEPA ADM706TAN MIC706TN - ASM706TESA MAX706TESA IMP706TESA ADM706TAR MIC706TM - ASM707CPA MAX707CPA IMP707CPA ADM707AN MIC707N - ASM707CSA MAX707CSA IMP707CSA ADM707AR MIC707M - ASM707CUA MAX707CUA IMP707CUA ADM707ARM - - ASM707EPA MAX707EPA IMP707EPA ADM707AN MIC707N - ASM707ESA MAX707ESA IMP707ESA ADM707AR MIC707M - ASM708CPA MAX708CPA IMP708CPA ADM708AN MIC708N - ASM708CSA MAX708CSA IMP708CSA ADM708AR MIC708M - ASM708CUA MAX708CUA IMP708CUA ADM708ARM - - ASM708EPA MAX708EPA IMP708EPA ADM708AN MIC708N - ASM708ESA MAX708ESA IMP708ESA ADM708AR MIC708M - ASM708JCPA - IMP708JCPA - - - ASM708JCSA - IMP708JCSA - - - ASM708JCUA - IMP708JCUA - - - ASM708JEPA - IMP708JEPA - - - ASM708JESA - IMP708JESA - - - ASM708RCPA MAX708RCPA IMP708RCPA ADM708RAN MIC708RN - ASM708RCSA MAX708RCSA IMP708RCSA ADM708RAR MIC708RM - ASM708RCUA MAX708RCUA IMP708RCUA - - - ASM708REPA MAX708REPA IMP708REPA ADM708RAN MIC708RN - ASM708RESA MAX708RESA IMP708RESA ADM708RAR MIC708RM - ASM708SCPA MAX708SCPA IMP708SCPA ADM708SAN MIC708SN - ASM708SCSA MAX708SCSA IMP708SCSA ADM708SAR MIC708SM - ASM708SCUA MAX708SCUA IMP708SCUA - - - ASM708SEPA MAX708SEPA IMP708SEPA ADM708SAN MIC708SN - ASM708SESA MAX708SESA IMP708SESA ADM708SAR MIC708SM - ASM708TCPA MAX708TCPA IMP708TCPA ADM708TAN MIC708TN - ASM708TCSA MAX708TCSA IMP708TCSA ADM708TAR MIC708TM - ASM708TCUA MAX708TCUA IMP708TCUA - - - 24 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 27.
    CPU Supervisor CrossReference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM708TEPA MAX708TEPA IMP708TEPA ADM708TAN MIC708TN - ASM708TESA MAX708TESA IMP708TESA ADM708TAR MIC708TM - ASM802LCPA MAX802LCPA IMP802LCPA ADM802LAN - - ASM802LCSA MAX802LCSA IMP802LCSA ADM802LARN - - ASM802LEPA MAX802LEPA IMP802LEPA ADM802LAN - - ASM802LESA MAX802LESA IMP802LESA ADM802LARN - - ASM802MCPA MAX802MCPA IMP802MCPA ADM802MAN - - ASM802MCSA MAX802MCSA IMP802MCSA ADM802MARN - - ASM802MEPA MAX802MEPA IMP802MEPA ADM802MAN - - ASM802MESA MAX802MESA IMP802MESA ADM802MARN - - ASM805LCPA MAX805LCPA IMP805LCPA ADM805LAN - - ASM805LCSA MAX805LCSA IMP805LCSA ADM805LARN - - ASM805LEPA MAX805LEPA IMP805LEPA ADM805LAN - - ASM805LESA MAX805LESA IMP805LESA ADM805LARN - - ASM809JEUR MAX809JEUR IMP809JEUR ADM809JAR MIC809JU TCM809J ASM809LEUR MAX809LEUR IMP809LEUR ADM809LAR MIC809LU TCM809L ASM809MEUR MAX809MEUR IMP809MEUR ADM809MAR MIC809MU TCM809M ASM809REUR MAX809REUR IMP809REUR ADM809RAR MIC809RU TCM809R ASM809SEUR MAX809SEUR IMP809SEUR ADM809SAR MIC809SU TCM809S ASM809TEUR MAX809TEUR IMP809TEUR ADM809TAR MIC809TU TCM809T ASM810JEUR MAX810JEUR IMP810JEUR ADM810JAR MIC810JU TCM810J ASM810LEUR MAX810LEUR IMP810LEUR ADM810LAR MIC810LU TCM810L ASM810MEUR MAX810MEUR IMP810MEUR ADM810MAR MIC810MU TCM810M ASM810REUR MAX810REUR IMP810REUR ADM810RAR MIC810RU TCM810R ASM810SEUR MAX810SEUR IMP810SEUR ADM810SAR MIC810SU TCM810S ASM810TEUR MAX810TEUR IMP810TEUR ADM810TAR MIC810TU TCM810T ASM811JEUS MAX811JEUS IMP811JEUS ADM811JAR MIC811JU TCM81LJ ASM811LEUS MAX811LEUS IMP811LEUS ADM811LAR MIC811 TCM811L ASM811MEUS MAX811MEUS IMP811MEUS ADM811MAR MIC811 TCM811M ASM811REUS MAX811REUS IMP811REUS ADM811RAR MIC811 TCM811R ASM811SEUS MAX811SEUS IMP811SEUS ADM811SAR MIC811 TCM811S ASM811TEUS MAX811TEUS IMP811TEUS ADM811TAR MIC811 TCM811T ASM812JEUS MAX812JEUS IMP812JEUS ADM812JAR MIC812 TCM812J ASM812LEUS MAX812LEUS IMP812LEUS ADM812LAR MIC812 TCM812L ASM812MEUS MAX812MEUS IMP812MEUS ADM812MAR MIC812 TCM812M ASM812REUS MAX812REUS IMP812REUS ADM812RAR MIC812 TCM812R ASM812SEUS MAX812SEUS IMP812SEUS ADM812SAR MIC812 TCM812S ASM812TEUS MAX812TEUS IMP812TEUS ADM812TAR MIC812 TCM812T ASM813LCPA MAX813LCPA IMP813LCPA - - - ASM813LCSA MAX813LCSA IMP813LCSA - - - ASM813LCUA MAX813LCUA IMP813LCUA - - - ASM813LEPA MAX813LEPA IMP813LEPA - - - ASM813LESA MAX813LESA IMP813LESA - - - www.alsc.com Product Guide 2004 25 Notice: The information in this document is subject to change without notice.
  • 28.
    CPU Supervisor CrossReference Guide Alliance Maxim/Dallas IMP Analog Devices Micrel Microchip ASM8500-27 - - - - - ASM8500-29 - - - - - ASM8500-42 - - - - - 26 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 29.
    SYSTEM SOLUTIONS PRODUCTS www.alsc.com Product Guide 2004 27 Notice: The information in this document is subject to change without notice.
  • 30.
    System Solutions Products Alliance develops Connectivity and Networking ASSPs that address critical bandwidth and performance bottlenecks in legacy and emerging embedded, networking, computing and storage systems. • The Connectivity Product Portfolio includes the most comprehensive product selection of high-speed bridges based on HyperTransport™ technology (HT) including HT-to-PCI/PCI-X bridges. These bridges work together with the HyperTransport interface on the new generation of leading embedded and discreet microprocessors from AMD, Broadcom, PMC-Sierra and Transmeta. They allow system architects to leverage the performance of these leading microprocessors while still maintaining compatibility with legacy PCI/PCI-X based systems. The Connectivity Product Portfolio also includes a series of industry standard IEEE1149.1 JTAG gateways and controllers that partition a JTAG scan chain into multiple smaller chains for easier fault diagnostics and faster Flash programming. • The Networking Product Portfolio includes a family of networking media access controllers to address the needs of established and emerging protocols and standards including 10 Gbps Ethernet, Resilient Packet Ring (RPR) (IEEE802.17), Generic Framing Procedure (GFP) and others. These networking controllers serve a variety of applications and vertical markets including networking, cable infrastructure, storage, compute and others. 28 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 31.
    Connectivity HyperTransport™ Bridges Product Selector Guide SP1011 AS90L10204 AS90L10208 HT Link Specifications HT 1.01 HT 1.05 HT 1.05 200, 300, 400, 500, 600 & 800 HT Link Speed 200 & 400 MHz 200, 400, 600 & 800 MHz MHz 8-bit for sides A and B 8-bit for sides A and B HT Link Width 8-bit for sides A and B (Supports 2 & 4-bit) (Supports 2 & 4-bit) PCI Bus Type PCI rev 2.2 PCI rev 2.2 PCI rev 2.2 PCI Bus Max Frequency 66 MHz 66 MHz 66 MHz PCI-X Bus Type - PCI-X 1.0b PCI-X 1.0b PCI-X Bus Max Frequency - 133 MHz 133 MHz PCI/PCI-X Bus Width 64-bit 64-bit 64-bit YES Configurable PCI/PCI-X bus - - 1 x 64-bit bus or 2 x 32-bit independent busses YES SP1011 Register Compatible - - Configurable as a single or dual SP1011 Core Voltage 2.5V 1.8V 1.8V PCI/PCI-X Bus Voltage 3.3V 3.3V 3.3V 5V Tolerant PCI IO YES YES YES GPIO - 7 per PCI/PCI-X bus 7 per PCI/PCI-X bus 5 external slots per PCI/PCI-X PCI/PCI-X Bus Arbiter 5 external slots 5 external slots bus Package 352 BGA 388 PBGA 388 PBGA Package Size 31mm x 31mm 27mm x 27mm 27mm x 27mm Lead Free or - YES (Green) YES (Green) Green Package* * Green package means lead free compound and substrate www.alsc.com Product Guide 2004 29 Notice: The information in this document is subject to change without notice.
  • 32.
    AS90L10204 HyperTransport™-to-PCI/PCI-X Bridge Overview The AS90L10204 is a high performance bandwidth up to 25.6 Gbps. Each AS90L10204 HT port HyperTransport™-to-PCI/PCI-X bridge capable of can be 2, 4, or 8 bits wide in both transmit and receive tunneling the data between the two HT ports or directions. transferring the data between the HT ports and the AS90L10204 supports one 64-bit, PCI/PCI- PCI/PCI-X port. It is designed for bandwidth-hungry X1.0b port to connect to a variety of PCI/PCI-X based and performance-intensive applications in computer peripherals and add-on cards such as NICs, storage servers, workstations, desktop PCs and embedded HBA and others. Up to 31 devices can be daisy- systems. chained to build higher capacity systems with multiple Each 8-bit HT port operates at frequencies of PCI/PCI-X buses and HT-based peripherals. 200, 400, 600 and 800 MHz DDR for both transmit and receive directions, and sustains a total aggregate Key Features • Two bidirectional 8-bit HyperTransport interfaces: • Built-in two-level PCI arbiter with support for up to five • Supports 200, 400, 600 and 800 MHz DDR (double external devices data rate) for peak bandwidth of 3.2 GB/s per 8-bit • Can also be configured to support an external bidirectional HT port arbiter • Supports dynamic frequency reprogramming • 3.3V PCI IO with 5V tolerant IOs • Complies with HyperTransport 1.05 Link Interface • Transaction forwarding for the following commands: Specification • All IO and memory commands • Tunnels between the two HyperTransport interfaces • Type 1 to Type 1 configuration commands • The HT interfaces support dual-hosted chain (host (downstream only) CPU on each port) with the capability to transfer data • Type 1 to Type 0 configuration commands from the PCI/PCI-X bus to either host CPU (downstream only) • 1 x 64 bit, up to 133 MHz PCI-X 1.0b with support for • 1.8V core, 1.2V HT IO, 3.3V PCI/PCI-X IO up to 66 MHz PCI 2.2 • JTAG port • Supports with parity and error checking features • Available in a 388-pin PBGA green package AS90L10204 Device Block Diagram H T 1 .0 5 Inte rfa ce H T 1 .0 5 Inte rfa ce Lin k Interface L ink In te rfa ce Tx Tx Tx Tx PHY F IF O F IF O PHY 8-bit H T P acket G en era to r P acke t G e ne rator 8 -b it H T @ 800 M H z Lin k Interface L ink In te rfa ce @ 80 0 M H z Rx Rx Rx Rx PHY F IF O F IF O PHY R x B uffer R x B uffer P C I/P C I-X Interface 64 -b it P C I/P C I-X P o rt 1x6 4-bit, 6 6 M H z P C I o r 133 M H z P C I-X 1 .0b 30 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 33.
    AS90L10208 HyperTransport™-to-PCI/PCI-X Bridge Overview The AS90L10208 is a high performance per 8-bit bidirectional HT port. Each AS90L10208 HT HyperTransport™-to-PCI/PCI-X bridge capable of port can be 2, 4, or 8-bits wide in both transmit and transferring data between the HT host port and the receive directions. AS90L10208 supports one 64-bit, other HT port or the PCI/PCI-X port. It is designed for PCI/PCI-X1.0b port that can be configured as a single bandwidth-hungry and performance-intensive 64-bit port or a dual 32-bit ports. Up to 31 devices can applications in communications, networking, servers, be daisy-chained to build higher capacity systems with and storage systems. multiple PCI/PCI-X buses and HT-based peripherals. A Each HT port operates at frequencies up to 800 fairness algorithm allocates bandwidth among devices, MHz DDR for both transmit and receive directions and thereby eliminating starvation of bridges at the end of sustains a total aggregate bandwidth up to 25.6 Gbps the chain. Key Features • Two bidirectional 8-bit HyperTransport interfaces: • Built-in two-level PCI arbiter with support for up to five • Supports 200, 300, 400, 500, 600 and 800 MHz DDR external devices (double data rate) for peak bandwidth of 3.2 GB/s per • Can be configured to support an external arbiter 8-bit bidirectional HT port • 3.3V PCI IO with 5V tolerant IOs • Supports dynamic frequency reprogramming • Supports with parity and error checking features • Complies with HyperTransport 1.05 Link Interface • Superset register compatible with the SP1011 to Specifications leverage the same software driver • No protocol-induced maximum HyperTransport link • Can be configured to fully emulate a single or a dual length, which allows system designers to optimize speed SP1011 devices vs. distance • Transaction forwarding for the following commands: • The HT interfaces support dual-hosted chain • All IO and memory commands • One 64-bit configurable PCI/PCI-X 1.0b port: • Type 1 to Type 1 configuration commands • 1 x 64-bit, up to 66 MHz PCI 2.2 or up to 133 MHz (downstream only) PCI-X 1.0b • Type 1 to Type 0 configuration commands • 2 x 32-bit, up to 66 MHz PCI 2.2 or up to 133 MHz (downstream only) PCI-X 1.0b • 1.8V core, 1.2V HT IO, 3.3V PCI/PCI-X IO • Supports daisy-chaining up to 31 devices. The • JTAG port bandwidth is shared among the devices using a fairness • Available in a 388-pin PBGA green package algorithm AS90L10208 Device Block Diagram H T 1 .0 5 Inte rfa ce H T 1 .0 5 Inte rfa ce Lin k Interface L ink In te rfa ce Tx Tx Tx Tx PHY F IF O F IF O PHY 8-bit H T P acket G en era to r P acke t G e ne rator 8-b it H T @ 800 M H z Lin k Interface L ink In te rfa ce @ 800 M H z Rx Rx Rx Rx PHY F IF O F IF O PHY R x B uffer R x B uffer P C I/P C I-X Interface 1x6 4-bit, 6 6 M H z P C I o r 133 M H z P C I-X 1 .0b 2x3 2-bit, 6 6 M H z P C I o r 133 M H z P C I-X 1 .0b www.alsc.com Product Guide 2004 31 Notice: The information in this document is subject to change without notice.
  • 34.
    JTAG Controllers ProductSelector Guide AS91L1001 AS91L1002 AS91L1003U AS91L1006BU Description JTAG Test Controller JTAG Test Sequencer 3-Port JTAG Gateway 6-Port JTAG Gateway IEEE1149.1 JTAG 1 1 1 1 Primary Port IEEE1149.1 JTAG 1 - 3 6 Secondary Port YES Flash Interface - (Used to execute tests - - stored in Flash) YES CPU Interface (Used to allow CPU to - - - drive the tests) Core and IO Voltage 3.3V 3.3V 3.3V 3.3V 5V Tolerant IO YES YES YES YES 100-pin LQFP 100-pin LQFP 100-pin LQFP 100-pin LQFP Package 100-pin FPBGA 100-pin FPBGA 100-pin FPBGA 100-pin FPBGA 18mm x 18mm (LQFP) 18mm x 18mm (LQFP) 18mm x 18mm (LQFP) 18mm x 18mm (LQFP) Package Size 11mm x 11mm (FPBGA) 11mm x 11mm (FPBGA) 11mm x 11mm (FPBGA) 11mm x 11mm (FPBGA) Lead-Free or YES YES YES YES (Lead-free for LQFP, (Lead-free for LQFP, (Lead-free for LQFP, (Lead-free for LQFP, Green Package* Green for FPBGA) Green for FPBGA) Green for FPBGA) Green for FPBGA) * Green package means lead free compound and substrate 32 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 35.
    AS91L1001 JTAG TestController Overview The AS91L1001 device provides an Master mode: In this mode the primary interface between the 60x bus on the Motorola and secondary ports are now both totally MPC8260 processor and two totally independent independent IEEE1149.1 JTAG bus masters, IEEE1149.1 ports. It handles all the protocol for the 60x which enable concurrent operation on both of the bus to write and read directly to registers within the IEEE1149.1 JTAG chains. The Master mode device with no additional glue logic. enables the primary IEEE1149.1 JTAG port to be The AS91L1001 has three distinct modes of used to access other PCBs through the 5-wire operation, namely Slave mode, Master mode, and 3rd- IEEE1149.1 interface on the back plane. The Party Support mode. These different modes control secondary IEEE1149.1 JTAG port is used to test how data will be generated on the IEEE1149.1 buses. the card that is hosting the AS91L1001. Slave mode: In this mode, a transparent 3rd Party Support mode: In this mode, connection between the primary and the secondary bit bang operation (serial shifting of data) can be ports is established. This mode is usually used to test a enabled on any of the two ports. This is used to board from a system back plane. programs legacy FPGA/CPLD devices. Key Features • Interprets between the Motorola MPC8260 • Available in a 100-pin lead-free LQFP package or processor and two IEEE1149.1 JTAG ports a 100-pin FPBGA green package • Three distinct modes of operation: Slave mode, • 3.3V Core and IO Master mode, and 3rd Party Support mode • 5V Tolerant IOs • Supports a wide range of 3rd party tools • Pinout and feature set compatible (complete second source) with the Firecron JTS01 device AS91L1001 System Block Diagram Microprocessor AS91L1001 JTAG Test Controller Flash/Memory CPU Interface Port AS91L1003 3-Port JTAG DSP Gateway Secondary Primary JTAG JTAG Port Port ASIC/CPLD/FPGA www.alsc.com Product Guide 2004 33 Notice: The information in this document is subject to change without notice.
  • 36.
    AS91L1002 JTAG TestSequencer Overview The AS91L1002 provides a solution to perform The AS91L1002 can be controlled using one boundary scan tests and IEEE1149.1 JTAG tests on a of two different sources: a power-on reset circuit, or a PCB board at reset time without any third party test front panel switch. Any one of these can cause the hardware or a microprocessor. AS91L1002 to execute tests that have been loaded Once enabled, the AS91L1002 executes JTAG into the Flash memory. and boundary scan tests stored in a Flash memory. The When the tests have completed, the status of results of the tests are compared with the expected the execution is presented off chip through a status results also stored in Flash memory. Upon completion line to indicate the PASS/FAIL condition. The test of the tests, a PASS/FAIL result is presented. The results can also be written back into the Flash to AS91L1002 enables very rapid testing of the complete enable the diagnosis of failures when a PCB is PCB at reset time to provide a quick indication and a returned to the factory for debug. high degree of confidence in the operation of the PCB. Key Features • Performs IEEE1149.1 JTAG and boundary scan • Pinout and feature set compatible (complete tests in standalone mode without any 3rd party test second source) with the Firecron JTS02 device hardware • Available in a 100-pin LQFP lead-free package or • Eliminates the need for firmware development, a 100-pin FPBGA green package thereby speeding up time to market • 3.3V Core and IO • Performs self tests in parallel on multiple PCBs in a • 5V Tolerant IOs system • Stores tests results back into Flash memory AS91L1002 System Block Diagram Flash (Used to store test program and expected test results) Flash/Memory Test Result Indicators AS91L1002 AS91L1003U JTAG Test 3-Port JTAG DSP Sequencer Gateway ASIC/CPLD/ FPGA 34 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 37.
    AS91L1003U 3-Port JTAGGateway Overview The AS91L1003U is a one to three-port JTAG multi-drop environment without any additional signals. gateway. It partitions a simple JTAG chain into three This multi-drop capability enables the standard separate chains. These separate chains can be IEEE1149.1 interface to be used not just for stand optionally configured to operate as a single chain. alone PCB testing, but complete system testing The AS91L1003U provides the capability of including all PCBs within a system back plane partitioning the PCB into multiple smaller IEEE1149.1 environment. scan chains totally under software control. Partitioning All of the protocols required for addressing the the IEEE1149.1 chains on the PCB has several AS91L1003U device via the multi-drop capability and benefits, which include easier fault diagnostics the protocols for configuring which of the three capabilities as a fault on one of the IEEE1149.1 Local IEEE1149.1 LSPs of the AS91L1003U are to be used, Scan Ports (LSPs) does not render the PCB un- is handled via the 3rd party ATPG tools from vendors testable, faster Flash programming on the PCBs and like Asset-Intertech and JTAG Technologies. In a removal of IEEE1149.1 signal loading issues. multi-drop environment it is also possible to perform The AS91L1003U device is used to provide interconnect tests between multiple PCBs within the enhanced capabilities to the standard IEEE1149.1. It system, thus extending the interconnect tests to the enables the IEEE1149.1 interface to be used in a true back plane itself. Key Features • Device multi-drop addressable via the IEEE1149.1 • Provides the ability to initiate self test on a remote protocol PCB via a standard IEEE1149.1 command • Support for 3 local scan chains addressable via the • Support for JTAG Technologies AutoWR feature IEEE1149.1 interface • Pinout and feature set compatible (complete • Support for Pass-through mode second source) with the Firecron JTS03U device • Support for the IEEE1149.1 USERCODE instruction • Available in a 100-pin LQFP lead-free package or • Support for Status instruction enabling non-intrusive a 100-pin FPBGA green package monitoring of the system card • 3.3V Core and IO • Local Scan Port (LSP) enable signal provides the • 5V Tolerant IOs ability to use non IEEE1149.1 compliant devices that require JTAG enable signal AS91L1003U System Block Diagram Standard ASIC Product JTAG Connector AS91L1003U Flash Memory Standard FPGA Product www.alsc.com Product Guide 2004 35 Notice: The information in this document is subject to change without notice.
  • 38.
    AS91L1006BU 6-Port JTAGGateway Overview The AS91L1006BU is a one to six-port JTAG. It enables the IEEE1149.1 JTAG interface to be IEEE1149.1 JTAG gateway. It partitions a simple used in a true multi-drop environment without any IEEE1149.1 JTAG chain into six separate chains. additional signals. This multi-drop capability enables These separate chains can be optionally configured to the standard IEEE1149.1 JTAG interface to be used operate as a single chain. not just for stand-alone PCB testing, but also for The AS91L1006BU provides the capability of complete system testing including all PCBs within a partitioning the PCB into multiple smaller IEEE1149.1 system back plane environment. JTAG scan chains that are totally under software All of the protocols required for addressing the control. Partitioning the IEEE1149.1 JTAG chains on AS91L1006BU device via the multi-drop capability and the PCB has several benefits, including easier fault the protocols for configuring which of the six diagnostics capabilities as a fault on one of the IEEE1149.1 LSPs on the AS91L1006BU is to be used, IEEE1149.1 JTAG Local Scan Ports (LSPs) does not are handled via 3rd party ATPG tools from vendors like render the PCB untestable, faster Flash programming Asset-Intertech and JTAG Technologies. In a multi- on the PCBs, and removal of IEEE1149.1 JTAG signal drop environment it is also possible to perform loading issues. interconnect tests between multiple PCBs within a The AS91L1006BU is also used to provide system, thus extending the interconnect tests to the enhanced capabilities to the standard IEEE1149.1 back plane itself. Key Features • Device multi-drop addressable via the IEEE1149.1 • Provides the ability to initiate self test on a remote JTAG protocol PCB via a standard IEEE1149.1 JTAG command • Support for 6 local scan chains addressable via the • Support for JTAG Technologies AutoWR feature, IEEE1149.1 JTAG interface which enables faster Flash programming • Support for Pass-through mode • Pinout and feature set compatible (complete • Support for status instruction enabling non-intrusive second source) with the Firecron JTS06BU device monitoring of the system card • Available in a 100-pin LQFP lead-free package or • Local Scan Port (LSP) enable signal provides the a 100-pin FPBGA green package ability to use non IEEE1149.1 JTAG compliant • 3.3V Core and IO devices that require JTAG enable signal • 5V Tolerant IOs AS91L1006BU System Block Diagram Standard Standard Microprocessor Product Product Standard ASIC ASIC JTAG Connector Product AS91L1006BU Flash Memory Flash Memory CPLD FPGA ASIC 36 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 39.
    Networking RPR Controllers Product Selector Guide AS95L2101 AS95L2102 AS95L2100 Forwarding and Processing 5 Gbps 10 Gbps 20 Gbps Bandwidth Client-Side Interface 1 SPI4.2 port 1 SPI4.2 Port 2 SPI4.2 Ports Line-Side Interface 2 SFI-4 Ports (A and B) 2 SFI-4 Ports (A and B) 2 SFI-4 Ports (A and B) 32-bit PCI bus or 16-bit generic 32-bit PCI bus or 16-bit generic 32-bit PCI bus or 16-bit generic Control Plane Interface CPU bus CPU bus CPU bus Ethernet MAC 2 x 2.5G - 2 x 10G SONET (STS) / SDH (STM) OC-12 and OC-48 OC-12 and OC-48 OC-48 and OC-192 Protocol per Line-Side Port POS/HDLC, GFP and Ethernet / POS/HDLC, GFP and Frame Delineation POS/HDLC and GFP PacketPHY Ethernet / PacketPHY IEEE 802.17 draft 3.x IEEE 802.17 draft 3.x IEEE 802.17 draft 3.x Ring Protocols Cisco SRP v2 Cisco SRP v2 Cisco SRP v2 Others Others Others On-chip Transit Buffer Single or dual Single or dual Single or dual Single or Dual Card Mode YES YES YES Packet Priority Classification High, medium and low High, medium and low High, medium and low Package 928 HSBGA 928 HSBGA 928 HSBGA Package Size 40mm x 40mm 40mm x 40mm 40mm x 40mm www.alsc.com Product Guide 2004 37 Notice: The information in this document is subject to change without notice.
  • 40.
    AS95L210x Family ofResilient Packet Ring Controllers Overview The AS95L210x family of Resilient Packet Ring standards. The AS95L210x family incorporates the (RPR) Controllers is especially designed to support the resilient ring Media Access Control (MAC) along with emerging IEEE802.17 Resilient Packet Ring (RPR) layer 1 and layer 2 functions that include: SONET standard at various line interface speeds including OC- framers, Ethernet MACs, POS/HDLC, GFP and WIS 12, OC-48 and OC-192 for SONET, and 2.5G and 10G frame delineators. The family also integrates on-chip for Ethernet and PacketPHY. address matching Content Addressable Memory The AS95L210x family is based on a unique (CAMs), and large buffer memory for insert and high patented Adaptive Compute Architecture that combines priority transit queues. wire-speed processing power with adaptive logic. This The AS95L210x family includes on-chip technology provides unparalleled control over hardware configuration, performance and fault-management and software that enable the same device to be features that support RPR requirements for Operation, adapted – without performance penalty – to various Administration, Maintenance and Provisioning ring protocols such as the emerging IEEE802.17 draft (OAM&P). The AS95L210x family is ideally suited for a 3.x, Cisco’s SRP™ and other proprietary protocols. variety of vertical markets including networking, The RPR Controller family uniquely supports communications, computing, cable infrastructure, multiple physical interfaces, modes, protocols and servers and storage cluster systems. AS95L210x Device Block Diagram DDR SRAM Interface RPR MAC Line-Side Port A Adaptive Header Receive Queue Engine SFI-4 OC-192 Framers Quad OC-48 Framers Quad OC-12 Framers Transit Transmit Queues 2.5G & 10G Ethernet MAC SPI4.2 HDLC/GFP Single or Scheduler Adaptive Compute Dual Engine SPI4.2 Line-Side Port B Interface SFI-4 OC-192 Framers Transit Transmit Queues Quad OC-48 Framers Quad OC-12 Framers 2.5G & 10G Ethernet MAC Adaptive Header Receive Queue HDLC/GFP Engine DDR SRAM Interface PCI / CPU Management Bus 38 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 41.
    Functional Description The AS95L210x family includes three devices ring processing, bandwidth management and protection based on the same architecture that incorporate the switching. same set of features. They are software compatible Each packet received on the line-side ports is and differ in the bandwidth and line rate they support. delineated, processed and reassembled in accordance The AS95L2100 has a 20 Gbps maximum bandwidth with the appropriate protocol and framing convention and supports OC-192, OC-48 and 10 GE line (Ethernet, SONET, GFP, or HDLC) and passed to the interfaces. The AS95L2102 has 10 Gbps maximum AHE. The AHE performs CRC checks and discards or bandwidth and supports OC-48 and OC-12 line marks corrupt packets. In ring mode it matches the interfaces. The AS95L2101 has 5 Gbps max bandwidth packet’s destination address with CAM entries to and supports OC-48, OC-12 and 2.5 GE line interfaces. determine packet routing. Local traffic is stripped from Each device is comprised of two major subsystems: the the ring and the packet type is classified as data or line-side ports and the RPR MAC. control. Local data packets are transferred to the client- The two line-side ports (A and B) are side SPI4.2 port for delivery to the application symmetrical and each incorporates a PHY interface, processor. Control packets, consisting of provisioning frame delineation logic, SONET framers, Ethernet information, fairness messages, ring status, topology MACs and multiplexing logic. They are used to connect and others are passed to the control plane CPU or to the AS95L210x family to the rings through an external the client-side port for processing. PHY device (Serdes). The AS95L210x family supports multiple The RPR MAC performs the MAC functions queuing options including single or dual transit buffers and incorporates two Adaptive Header Engines (AHE), with up to three priority classifications (high, medium each with an address-matching CAM. It also includes and low). protection switching logic and an Adaptive Control The AHE can extract information from Engine (ACE) for executing fairness algorithms and encapsulated headers for various frame delineation controlling dispatching regimes. protocols enabling it to adapt to a wide spectrum of One or two client-side ports (depending on the industry and proprietary standards as well as to custom device) are used to connect to a client FPGA or to a header processing requirements. Network Processor (NPU). A control plane interface is The AS95L210x family of RPR Controllers used to configure and manage the operation of the operates in either single-line card or dual-line card AS95L210x RPR Controllers. modes. In single line-card mode, a single device The AS95L210x family operates in two modes. terminates the rings for cost efficiency. In dual-line card In standard topology mode (framer mode) it operates mode, two AS95L210x (one on each line card) as a dual full-duplex Ethernet MAC or as multiple terminate the rings (one for each ringlet) for SONET Framers; and in ring mode the AS95L210x redundancy. family additionally has all the logic required for packet Single-Line Card System Block Diagram Ring 0 Fabric Traffic Manager NPU/FPGA Ring 1 RPR PHY Controller AS95L210x Switch Ring 2 Control Ring 3 Plane CPU www.alsc.com Product Guide 2004 39 Notice: The information in this document is subject to change without notice.
  • 42.
    Software A complete Linux-based software kernel driver (running the fairness algorithm). Binary file generation and user-space API that allows for configuration and tools and Assembler tools are included as part of the management of all line and client–side interfaces for software module. the AS95L210x RPR Controller family is available. The Host kernel snap-in executable contains The driver consists of two logical portions: the the software to manage the fairness algorithm (running main kernel driver that manages the hardware, and the in the Adaptive Control Engine), the topology discovery kernel “Snap-in” – referred to as Profile – that manages protocol, the intelligent protection switching and the ring protocol specific features. A different Profile is steering control as well as other ring control protocols needed for each of the ring protocols such as such as LRTT (Loop Round Trip Time) and FDD IEEE802.17 Draft 3.x, Cisco’s SRP and others. The (Fairness Differential Delay) calculations. following figure illustrates the software modules. The The AS95L210x family provides a number of driver also supports the two modes of operation: framer on-chip configurations and fault management features mode and ring mode. that support RPR requirements for OAM&P. Equipment Each Profile consists of two portions: a binary manufacturers use these adaptive features to provide executable file that is directly downloaded to the more robust and flexible multi-service solutions. AS95L210x family during system initialization; and a A user-level API tester is provided to allow host executable that interacts with the Profile and with each driver and ring-level API to be tested. The API the main kernel driver. tester also provides an easy mechanism to bring up the The binary file portion of the Profile contains AS95L210x family in ring mode or framer mode. execution code for the Adaptive Control Engine Software Modules User Space Kernel Space Physical Hardware Kernel Space AS95L210x Driver Customer Provided Threaded User Space Application Et PI PCI/CPU Bus tA he rn Controller RPR g m et open (..) open (..) M M gm Controller LC tA HD Configuration PI AS95L210x Statistics OS Kernel Multiplexer API GFP close (..) close (..) Error Handling t Mgm Mgm Handler Internet / Recovery RPR ET APIt Controller SON read (..) read (..) SPI4.2 Mgmt API AS95L210x Kernel Space Snap-in Profile IEEE 802.17 / SRP v2 / Others write (..) write (..) Profile Management API Instance Manager Topology Discovery ioctl (..) ioctl (..) Packet DMA Handler Intelligent Protection Diagnostics / Self Test Switching or Steering Control Ring Control API Fairness Algorithm 40 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 43.
    AS95L210x Key Features • Highly integrated device with on-chip SONET • Full duplex 2.5G and 10G Ethernet MAC processing Framers (OC-12/OC-48/OC-192), Ethernet MACs compliant with IEEEP802.3ae/D5.0 (2.5G and 10G) and RPR MAC • WIS (WAN Interface Sub-layer) support for 10 Gbps Ethernet Serial WAN applications • Supports IEEE802.17 draft 3.x, Cisco SRP v2 and others • Compliant with POS/HDLC IETF RFC 1662 and IETF RFC 2615 • Adaptive compute architecture accommodates modifications and proprietary protocols without • SONET/SDH framers defined by IETF RFCs 2615 / performance loss 1662 and GFP framers defined by ANSI T1X1.5 • Supports packet ring header processing, bandwidth • RMON counters comply with IETF RFC 2863 (802.3 management and protection switching MIBs) • Provides steered and wrapped protection switching (within 50 ms) per IEEE802.17 • Supports the Generic Framing Procedure (GFP) encapsulation per ANSI T1.105.02 (SONET) and • Supports up to 255 nodes per ring ITU-T G.709 (OTN) • Up to 20 Gbps bandwidth • On-chip memory for high-priority transit traffic buffer and staging buffer for insert traffic • Single-line card and dual-line card modes • On-chip CAM for address matching • Terminates up to 4 rings (8 ringlets) • Interface for external SRAM for medium and low • SONET/SDH section/line/path processing compliant priority transit traffic with Telcordia GR-253, ANSI T1.105, T1.416 and ITU G.751, G.783 and G.804 • The control plane interface can be configured either as a 32-bit PCI bus or as a generic 16-bit CPU bus • 928-pin HSBGA package www.alsc.com Product Guide 2004 41 Notice: The information in this document is subject to change without notice.
  • 44.
    42 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 45.
    MEMORY PRODUCTS www.alsc.com Product Guide 2004 43 Notice: The information in this document is subject to change without notice.
  • 46.
    SRAM Products Alliance offers a broad range of SRAM products, including synchronous and fast asynchronous SRAM. Synchronous SRAMs address the need for high-bandwidth data path buffers for primarily high-speed communications. Alliance offers a complete family of synchronous SRAMs, including No Turnaround Delay (NTD) and synchronous burst devices for these applications. In addition, Alliance supports the full range of 3.3V and 5V asynchronous SRAMs used with mainstream digital signal processors (DSPs) and microcontrollers. SRAM 64K 256K 512K 1M 2M 4M 9M 18M 36M 128K x 18 256K x 18 512K x 18 1M x 18 1M x 32/36 Synchronous - - - - 64K x 32/36 128K x 32/36 256K x 32/36 512K x 32/36 2M x 18 5V Fast 128K x 8 512K x 8 8K x 8 32K x 8 32K x 16 - - - - Asynchronous 64K x 16 256K x 16 3.3V Fast 128K x 8 512K x 8 - 32K x 8 32K x 16 - - - - Asynchronous 64K x 16 256K x 16 All SRAMs are available in industrial temperature range 44 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 47.
    Synchronous SRAM Alliance Semicnductor 7C = CMOS SRAM Core Voltage: 33 = 33V, and 25 = 2.5V Device depth denoted in K bits or M bits NTDTM = No turn-around delay, PFS = pipelined single-cycle deselect, PFD = Pipelined dual-cycle deselect, FT = flow through Device density width: x18-bits, x32-bits, x36-bits Suffix letter denotes die revision Clock cycle time in MHz Packages: TQ = TQFP-thin quad flat pack (100 pin), B = ball gid array Temperature Ranges C = Commercial (0 C to 70 C) I = Industrial (-40 C to 85 C) AS 7 C 2 5 256 NTD 36A -166 TQ C 3.3V Synchronous SRAM Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 2M 64K x 36 AS7C3364FT36B 7.5 ns TQFP (100) Production 3.3V IO 64K x 32 AS7C3364FT32B 7.5 ns TQFP (100) Production 3.3V IO 128 x 18 AS7C33128FT18B 7.5 ns TQFP (100) Production 3.3V IO 64K x 36 AS7C3364PFS36B 166 TQFP (100) Production 3.3V IO 64K x 32 AS7C3364PFS32B 166 TQFP (100) Production 3.3V IO 128K x 18 AS7C33128PFS18B 166 TQFP (100) Production 3.3V IO 64K x 36 AS7C3364PFD36B 166 TQFP (100) Production 3.3V IO 64K x 32 AS7C3364PFD32B 166 TQFP (100) Production 3.3V IO 128K x 18 AS7C33128PFD18B 166 TQFP (100) Production 3.3V IO 4M 128K x 36 AS7C33128FT36B 7.5 ns TQFP (100) Production 3.3V IO 128K x 32 AS7C33128FT32B 7.5 ns TQFP (100) Production 3.3V IO 256K x 18 AS7C33256FT18B 7.5 ns TQFP (100) Production 3.3V IO 128K x 36 AS7C33128PFS36B 166 TQFP (100) Production 3.3V IO 128K x 32 AS7C33128PFS32B 166 TQFP (100) Production 3.3V IO 256K x 18 AS7C33256PFS18B 166 TQFP (100) Production 3.3V IO 128K x 36 AS7C33128PFD36B 166 TQFP (100) Production 3.3V IO 128K x 32 AS7C33128PFD32B 166 TQFP (100) Production 3.3V IO 256K x 18 AS7C33256PFD18B 166 TQFP (100) Production 3.3V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. www.alsc.com Product Guide 2004 45 Notice: The information in this document is subject to change without notice.
  • 48.
    Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 9M 256K x 32 AS7C33256PFS32A 166 TQFP (100) Production 3.3V/2.5V IO 512K x 18 AS7C33512PFS18A 166 TQFP (100) Production 3.3V/2.5V IO 256K x 36 AS7C33256PFD36A 166 TQFP (100) Production 3.3V/2.5V IO 256K x 32 AS7C33256PFD32A 166 TQFP (100) Production 3.3V/2.5V IO 512K x 18 AS7C33512PFD18A 166 TQFP (100) Production 3.3V/2.5V IO 18M 512K x 36 AS7C33512FT36A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512FT32A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C331MFT18A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C331MPFS18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C33512PFS36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512PFS32A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C331MPFD18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K X 36 AS7C33512PFD36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512PFD32A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 36M 1M x 36 AS7C331MFT36A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 32 AS7C331MFT32A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 2M X 18 AS7C332MFT18A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 36 AS7C331MPFS36A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 32 AS7C331MPFS32A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 2M x 18 AS7C332MPFS18A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. 46 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 49.
    2.5V Synchronous SRAM Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 18M 512K x 36 AS7C25512FT36A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C25512FT32A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C251MFT18A 7.5 ns TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C251MPFD18A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 18 AS7C251MPFS18A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C25512PFS36A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C25512PFS32A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C25512PFD36A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C25512PFD32A 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 3.3V NTD™ Synchronous SRAM (NTD is industry compatible with other ZBT™ and NT cycle products.) Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 2M 64K x 36 AS7C3364NTD36B 166 TQFP (100) Production 3.3V IO 64K x 32 AS7C3364NTD32B 166 TQFP (100) Production 3.3V IO 4M 128K x 36 AS7C33128NTD36B 166 TQFP (100) Production 3.3V IO 128K x 32 AS7C33128NTD32B 166 TQFP (100) Production 3.3V IO 256K x 18 AS7C33256NTD18B 166 TQFP (100) Production 3.3V IO 9M 256K x 36 AS7C33256NTD36A 166 TQFP (100) Production 3.3V/2.5V IO 256K x 32 AS7C33256NTD32A 166 TQFP (100) Production 3.3V/2.5V IO 512K x 18 AS7C33512NTD18A 166 TQFP (100) Production 3.3V/2.5V IO 18M 512K x 36 AS7C33512NTD36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 32 AS7C33512NTD32A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1 M x 18 AS7C331MNTD18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 36M 1M x 36 AS7C331MNTD36A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 1M x 32 AS7C331MNTD32A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO 2M x 18 AS7C332MNTD18A 166, 200, 250 TQFP (100), BGA (165) Production 3.3V/2.5V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. www.alsc.com Product Guide 2004 47 Notice: The information in this document is subject to change without notice.
  • 50.
    2.5V NTD™ SynchronousSRAM (NTD is industry compatible with other ZBT™ and NT cycle products.) Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 18M 1M x 18 AS7C251MNTD18A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO 512K x 36 AS7C25512NTD36A 166 TQFP (100), BGA (165) Production 3.3V/2.5V IO Synchronous Dual Port SRAM Product Selector Guide Alliance Part Density Org Clk (MHz)* Packages Status** Comments Number 9M 256K x 36 AS9C25256M2036L 166 PQFP (208) Samples 3.3V/2.5V IO 512K x 18 AS9C25512M2018L 166 TQFP (144) Samples 3.3V/2.5V IO * Maximum speed in pipelined mode. ** S = sample date, P = estimated production date. 48 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 51.
    Asynchronous SRAM Alliance Semicnductor 7C = CMOS SRAM Voltage: Blank = 5V CMOS, 3 = 3.3V CMOS Device number assigned by Alliance Semiconductor. Suffix letter denotes die revision. Access time in nanoseconds Packages: J = SOJ 300 or 400 mil, TJ = SOJ 300 mil (applies only when J is 400 mil), T = TSOP 1 or 2, ST = sTSOP Temperature Ranges C = Commercial (0 C to 70 C) I = Industrial (-40 C to 85 C) AS 7 C 3 4098A -12 J C 5V Fast Asynchronous SRAM Product Selector Guide Alliance Part Density Org Speed (ns) Packages Status** Comments Number 64K 8K x 8 AS7C164 10/12/15/20 SOJ (28) Production - 256K 32K x 8 AS7C256A 10/12/15/20 SOJ (28), TSOP1 (28) Production - 512K 32K x 16 AS7C513B 10/12/15/20 SOJ (44), TSOP2 (44) Production - SOJ (32.3 & 32.4), 32.3 = 300 mil, 1M 128K x 8 AS7C1024B 10/12/15/20 Production TSOP1(32) 32.4 = 400 mil CPG (Center Power & 128K x 8 AS7C1025B 10/12/15/20 SOJ (32.3 & 32.4) Production Ground) 64K x 16 AS7C1026B 10/12/15/20 SOJ (44), TSOP2 (44) Production - 4M AS7C4096 12/15/20 SOJ (36), TSOP2 (44) Production - 512K x 8 S=2Q ’04, AS7C4096A 12/15/20 SOJ (36), TSOP2 (44) - P= 3Q ‘04 AS7C4098 12/15/20 SOJ (44), TSOP2 (44) Production - 256K x 16 S=2Q ’04, AS7C4098A 12/15/20 SOJ (44), TSOP2 (44) - P= 3Q ‘04 ** S = sample date, P = estimated production date. www.alsc.com Product Guide 2004 49 Notice: The information in this document is subject to change without notice.
  • 52.
    3.3V Fast AsynchronousSRAM Product Selector Guide Alliance Part Density Org Speed (ns) Packages Status** Comments Number 256K 32K x 8 AS7C3256A 10/12/15/20 SOJ (28), TSOP1 (28) Production - 512K 32K x 16 AS7C3513B 10/12/15/20 SOJ (44), TSOP2 (44) Production - SOJ (32.3 & 32.4), 32.3 = 300 mil, 1M 128K x 8 AS7C31024B 12/15/20 Production TSOP1(32) 32.4 = 400 mil CPG (Center Power 128K x 8 AS7C31025B 10/12/15/20 SOJ (32.3 & 32.4) Production & Ground) 64K x 16 AS7C31026B 10/12/15/20 SOJ (44), TSOP2 (44) Production - 4M 512K x 8 AS7C34096A 10/12/15/20 SOJ (36), TSOP2 (44) Production - 256K x 16 AS7C34098A 10/12/15/20 SOJ (44), TSOP2 (44) Production - ** S = sample date, P = estimated production date. 50 Product Guide 2004 www.alsc.com Notice: The information in this document is subject to change without notice.
  • 53.
    www.alsc.com Synchronous SRAM Cross Reference Guide CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33128FT18B 2M 128Kx18 3.3 133-166 CY7C1324F - - MT58L128L18FT K7B201825B - AS7C3364FT32B 2M 64Kx32 3.3 133-166 CY7C1336F IDT71V633S IS61LF6432A MT58L64L32FT K7B203225B GS82032AT AS7C3364FT36B 2M 64Kx36 3.3 133-166 CY7C1344F - IS61LF6436A MT58L64L36FT K7B203625B - AS7C33128PFS18B 2M 128Kx18 3.3 133-166 CY7C1326F - - MT58L128L18PT - - AS7C3364PFS32B 2M 64Kx32 3.3 133-166 CY7C1329G IDT71V632S IS61LP6432A MT58L64L32PT K7A203200B GS82032AT AS7C3364PFS36B 2M 64Kx36 3.3 133-166 CY7C1346G - IS61LP6436A MT58L64L36PT K7A203600B - AS7C33128PFD18B 2M 128Kx18 3.3 133-166 CY7C1223F - - MT58L128L18DT - - AS7C3364PFD32B 2M 64Kx32 3.3 133-166 - - - MT58L64L32DT - GS820E32AT AS7C3364PFD36B 2M 64Kx36 3.3 133-166 - - - MT58L64L36DT - - Product Guide 2004 AS7C3364NTD32B 2M 64Kx32 3.3 133-166 - - - MT55L64L32P1T - - AS7C3364NTD36B 2M 64Kx36 3.3 133-166 - - - MT55L64L36P1T - - AS7C33128FT32B 4M 128Kx32 3.3 133-166 CY7C1338F - IS61SF12832 MT58L128L32F1T K7B403225B GS840F36AT Notice: The information in this document is subject to change without notice. AS7C33128FT36B 4M 128Kx36 3.3 133-166 CY7C1345F IDT71V3577S IS61SF12836 MT58L128L36F1T K7B403625B GS840F36AT Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP 51
  • 54.
    52 Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33256FT18B 4M 256Kx18 3.3 133-166 CY7C1325F IDT71V3579S IS61SF25618 MT58L256L18F1T K7B401825B GS840F36AT AS7C33128PFS32B 4M 128Kx32 3.3 133-166 CY7C1339F - IS61SP12832 MT58L128L32P1T K7A403200B - AS7C33128PFS36B 4M 128Kx36 3.3 133-166 CY7C1347F IDT71V3576S 1S61SP12836 MT58L128L36P1T K7A403600B GS84032AT AS7C33256PFS18B 4M 256Kx18 3.3 133-166 CY7C1327F IDT71V3578S IS61SP25618 MT58L256L18P1T K7A401800B GS84018AT AS7C33128PFD32B 4M 128Kx32 3.3 133-166 CY7C1340F - - MT58L128L32D1T K7A403201B GS840E32AT AS7C33128PFD36B 4M 128Kx36 3.3 133-166 - - - MT58L128L36D1T K7A403601B GS840E18AT AS7C33256PFD18B 4M 256Kx18 3.3 133-166 CY7C1328F - - MT58L256L18D1T - GS840E18AT AS7C33128NTD32B 4M 128Kx32 3.3 133-166 - - IS61NP12832 MT55L128L32P1T K7N403201B - AS7C33128NTD36B 4M 128Kx36 3.3 133-166 CY7C1350F IDT71V3556S IS61NP12836 MT55L128L36P1T K7N403601B GS840Z36AT Product Guide 2004 AS7C33256NTD18B 4M 256Kx18 3.3 133-166 CY7C1352F IDT71V3558S IS61NP25618 MT55L256L18P1T K7N401801B GS840Z18AT AS7C33256PFS32A 9M 256Kx32 3.3 133-166 CY7C1364B - IS61SPS25632 MT58L256L32PT - GS88032BT AS7C33512PFS18A 9M 512Kx18 3.3 133-166 CY7C1362B IDT71B67803S IS61SPS51218 MT58L512L18PT K7A801800B GS88018BT Notice: The information in this document is subject to change without notice. AS7C33512PFD18A 9M 512Kx18 3.3 133-166 CY7C1367B - IS61SPD51218T MT58L512L18DT K7A801801B GS880E18BT Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP www.alsc.com
  • 55.
    www.alsc.com Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33256PFD32A 9M 256Kx32 3.3 133-166 CY7C1368B - IS61SPD25632T MT58L256L32DT - GS880E32BT AS7C33256PFD36A 9M 256Kx36 3.3 133-166 CY7C1366B - IS61SPD25636T MT58L256L36DT K7A803601B GS880E18BT AS7C33256NTD32A 9M 256Kx32 3.3 133-166 - - IS61NP25632 MT55L256L32PT - - AS7C33256NTD36A 9M 256Kx36 3.3 133-166 CY7C1354B IDT71V65603S IS61NP25636 MT55L256L36PT K7N803601B GS880Z36BT AS7C33512NTD18A 9M 512Kx18 3.3 133-166 CY7C1356B IDT71V65803S IS61NP51218 MT55L512L18PT K7N801801B GS880Z18BT AS7C33512FT32A 18M 512Kx32 3.3 133-166 - - - - - GS8160F32T AS7C33512FT36A 18M 512Kx36 3.3 133-166 CY7C1381C - IS61LF51236A - K7B163625B GS8160F36T AS7C251MFT18A 18M 1Mx18 2.5 166-250 - IDT71T75902S IS61VF102418A - - - AS7C25512FT32A 18M 512Kx32 2.5 166-250 - - - - - - Product Guide 2004 AS7C25512FT36A 18M 512Kx36 2.5 166-250 CY7C1381CV25 - IS61VF51236A - - - AS7C331MFT18A 18M 1Mx18 3.3 166-250 CY7C1383C - IS61LF102418A - K7B161825B GS8160F18T AS7C251MPFS18A 18M 1Mx18 2.5 166-250 CY7C1382CV25 - IS61VPS102418A - - - Notice: The information in this document is subject to change without notice. AS7C25512PFS32A 18M 512K x 32 2.5 166-250 - - - - - - Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP 53
  • 56.
    54 Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C25512PFS36A 18M 512Kx36 2.5 166-250 CY7C1380CV25 - IS61VPS51236A - - - AS7C331MPFS18A 18M 1Mx18 3.3 166-250 CY7C1382C - IS61LPS102418A - K7A161800B GS816018T AS7C33512PFS32A 18M 512Kx32 3.3 133-166 - - - - - GS816032T AS7C33512PFS36A 18M 512Kx36 3.3 133-166 CY7C1380C - IS61LPS51236A - K7A163600B GS816036T AS7C251MPFD18A 18M 1Mx18 2.5 166-250 CY7C1387CV25 - IS61VPD102418A - - - AS7C25512PFD32A 18M 512Kx32 2.5 166-250 - - - - - GS8160E32T AS7C25512PFD36A 18M 512Kx36 2.5 166-250 CY7C1386CV25 - IS61VPD51236A - - - AS7C331MPFD18A 18M 1Mx18 3.3 166-250 CY7C1387C - IS61LPD102418A - K7A161801B GS8160E18T AS7C33512PFD32A 18M 512Kx32 3.3 133-166 - - - - - GS8160E32T Product Guide 2004 AS7C33512PFD36A 18M 512Kx36 3.3 133-166 CY7C1386C - IS61LPD51236A - K7A163601B GS8160E36T AS7C251MNTD18A 18M 1Mx8 2.5 166-250 CY7C1372CV25 IDT71T75802S IS61NVP102418 - K7N161845B - AS7C25512NTD36A 18M 512Kx36 2.5 166-250 CY7C1370CV25 IDT71T75062S IS61NVP51236 - K7N163645B - Notice: The information in this document is subject to change without notice. AS7C331MNTD18A 18M 1Mx18 3.3 166-250 CY7C1372C - IS61NLP102418 - K7N161801B GS8160Z36T Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP www.alsc.com
  • 57.
    www.alsc.com Synchronous SRAM Cross Reference Guide (Continued) CLK Alliance Den Org Volt (V) Cypress IDT ISSI Micron Samsung GSI (MHz) AS7C33512NTD32A 18M 512Kx32 3.3 166-250 - - - - - - AS7C33512NTD36A 18M 512Kx36 3.3 133-166 CY7C1370C IS61NLP51236 - K7N163601B GS8160Z36T AS7C331MPFS32A 36M 1Mx32 3.3 166-250 - - - - - GS832032T AS7C331MPFS36A 36M 1Mx36 3.3 166-250 CY7C1440V33 - - - K7A323600M GS832036T AS7C332MPFS18A 36M 2Mx18 3.3 166-250 - - - - K7A321800M GS832018T AS7C331MFT32A 36M 1Mx32 3.3 166-250 - - - - - - AS7C331MFT36A 36M 1Mx36 3.3 166-250 CY7C1441V33 - - - K7B323625M - AS7C332MFT18A 36M 2Mx18 3.3 166-250 - - - - K7B321825M - Product Guide 2004 AS7C331MNTD32A 36M 1Mx32 3.3 166-250 - - - - - - AS7C331MNTD36A 36M 1Mx36 3.3 166-250 CY7C1460V33 - IS61NLP102436 - K7N323601M GS8320Z36T AS7C332MNTD18A 36M 2Mx18 3.3 166-250 CY7C1462V33 - - - K7N321801M GS8320Z18T Notice: The information in this document is subject to change without notice. Alliance Semiconductor package abbreviations and their equivalents. T= 2 CE TQFP Q=TQFP B=BGA A=TQFP PF=TQFP TQ=TQFP TQ=TQFP, B=BGA S= 3 CE TQFP F=BGA T=TQFP 55
  • 58.
    56 Fast Asynchronous SRAM Cross Reference Guide Alliance Den Org Volt Speed (ns) Cypress GSI IDT ISSI Samsung AS7C164 64K 8Kx8 5V 10-20 CY7C185 - IDT7164L IS1C64B - AS7C256A 256K 32Kx8 5V 10-20 CY7C199 - IDT71256SA IS61C256AH - AS7C3256A 256K 32Kx8 3.3V 10-20 CY7C1399B GS70328 IDT71V256SA IS61LV256 - AS7C513B 512K 32x16 5V 10-20 CY7C1020B - - IS61C3216 - AS7C3513B 512K 32x16 3.3V 10-20 CY7C1020CV33 - - IS1LV3216L - CY7C109B AS7C1024B 1M 128Kx8 5V 10-20 - IDT1024S IS61C1024 - CY7C1009B Product Guide 2004 AS7C31024B 1M 128Kx8 3.3V 12-20 - - - - - 128Kx8 AS7C1025B 1M 5V 10-20 CY7C1019B - IDT71124S - K6R1008C1D CPG T=TSOP I/II Z=TSOP I/II PZ=TSOP I TS=TSOP I H=sTSOP I T=TSOP I/II V=300/400 mil SOJ PH=TSOP II Alliance Semiconductor package abbreviations and their equivalents. TP=TSOP II B=48-pin BGA E=48-pin BGA P=PDIP Y=400 mil SOJ T=TSOP I/II, TJ=300 mil SOJ, J=400 mil SOJ, ST=sTSOP I, CPG=Center power and ground SJ=300 mil SOJ M=48-pin mBGA J=300/400 mil SOJ B=48-pin BGA TY=300 mil SOJ C=Commercial, I=Industrial J=400 mil SOJ J=300 SOJ H=119 BGA Notice: The information in this document is subject to change without notice. BA=48-pin mBGA P=PDIP B=119 BGA K=400 SOJ D=PDIP BG=119 PBGA B=48-pin BGA N,P or W=PDIP www.alsc.com
  • 59.
    www.alsc.com Fast Asynchronous SRAM Cross Reference Guide (Continued) Alliance Den Org Volt Speed (ns) Cypress GSI IDT ISSI Samsung 128Kx8 AS7C31025B 1M 3.3V 10-20 CY7C1018CV33 GS71108A IDT71V124SA IS61LV1024 K6R1008V1D CPG AS7C1026B 1M 64Kx16 5V 10-20 CY7C1021B - IDT71016S IS61C6416 K6R1016C1D AS7C31026B 1M 64Kx16 3.3V 10-20 CY7C1021CV33 GS71116A IDT71V016SA IS61LV6416 K6R1016V1D AS7C4096A 4M 512Kx8 5V 12-20 CY7C1049B - - - K6R4008C1D AS7C34096A 4M 512Kx8 3.3V 10-20 CY7C1049CV33 GS74108A IDT71V424S IS61LV5128AL K6R4008V1D AS7C4098A 4M 256Kx16 5V 12-20 CY7C1041B - - - K6R4016C1D Product Guide 2004 AS7C34098A 4M 256Kx16 3.3V 10-20 CY7C1041CV33 GS74116A IDT71V416S IS61LV25616AL K6R4016V1D T=TSOP I/II Z=TSOP I/II PZ=TSOP I TS=TSOP I H=sTSOP I T=TSOP I/II V=300/400 mil SOJ PH=TSOP II Alliance Semiconductor package abbreviations and their equivalents. TP=TSOP II B=48-pin BGA E=48-pin BGA P=PDIP Y=400 mil SOJ T=TSOP I/II, TJ=300 mil SOJ, J=400 mil SOJ, ST=sTSOP I, CPG=Center power and ground SJ=300 mil SOJ M=48-pin mBGA J=300/400 mil SOJ B=48-pin BGA TY=300 mil SOJ C=Commercial, I=Industrial J=400 mil SOJ J=300 SOJ H=119 BGA BA=48-pin mBGA P=PDIP Notice: The information in this document is subject to change without notice. B=119 BGA K=400 SOJ D=PDIP BG=119 PBGA B=48-pin BGA N P or W=PDIP 57
  • 60.
    58 Synchronous Dual Port SRAM Cross Reference Guide Alliance Den Org Volt (V) CLK (MHz) IDT AS9C25256M2036L 9M 256Kx36 3.3 133-166 IDT70T3519S AS9C25512M2018L 9M 512Kx18 3.3 133-166 IDT70T3339S Alliance Semiconductor package abbreviations and their equivalents. TQ=TQFP, B=BGA Product Guide 2004 Notice: The information in this document is subject to change without notice. www.alsc.com