2. Zilker Labs Overview
Mixed-signal Fabless Semiconductor Vendor
Founded in 2002
Headquartered in Austin, TX
Top-tier investors
– Sevin Rosen
– North Bridge
– HIG
Experienced management team
– Average of over 20 years experience
Corporate Strategy: Lead the transition to digital power
conversion and control
– 20+ fundamental architectural patents being filed
– First IC, ZL2005, introduced October 3, 2005
– Second IC, ZL2105, introduced July 31, 2006
2
3. Why Austin?
Mixed-signal design talent
Local venture capital
Infrastructure
– Assembly
– Failure analysis
– Contract engineering available
3
4. Today’s Power Issues
Dense boards with thermal
and board space challenges
Low voltages, high currents
Complex power
management requirements
– Sequencing/tracking
– Voltage margining
– System monitoring
– Fault detection and response
– Etc…
4
5. Zilker Labs Digital-DCTM Technology
Power management integrated with conversion
Mixed-signal implementation in digital CMOS
Easy-to-use: no programming required
Industry leading efficiency
Flexible design environment
Wide operating range
5
6. Complete System Power Solutions
ZL2105 1A to 3A
ZL2005 3A to 6A
Intermediate Bus
Thermal
control
ZL2005 6A to 30A
Multi
SMBus >30A
phase
3
Wide portfolio of digital power conversion/management ICs
Easy-to-implement management functions
System compatibility simplifies design process
Easy to use development tools – PowerPilot™, Demo Board, App Notes
6
7. Smaller Footprint
1.0” 1.0”
Zilker
Using same footprint
ZL solution has:
• Higher current 0.6” 0.4”
• More features 0.6”
Analog • Fewer components ZL2005
Optimizing 10A solution
Analog ZL2005 for very small size
ZL solution offers:
10.8V VIN min 4.5V
13.2V VIN max 14.0V • Rich feature set
• Fewer components
10 A IOUT max 12.5 A
• 60% smaller area
40 Components 15
Power
No Yes
Management
SMBus™
No Yes
PMBus™
7
8. Zilker Labs Design Team
Analog 30%
Digital 40%
Firmware 20%
DSP algorithm Development 10%
8
9. Verification Challenge
Analog block functionality
Digital functionality
Analog-Digital interface
Firmware actually defines product
How do you know you are done?
9
10. System Architecture
Intermediate Bus Voltage
Ramp Start Voltage Address/Phase
Pgood Enable Margin Rate Delay set Select
LDO
I2C, Power Management Logic
PMBus BST
MOSFET
MOSFET
Drivers
Drivers
RESET VOUT
DIGITAL
D-PWM SW
PID FILTER
Transient Detector
Sync PLL
- VSNS
MLC
Σ VDD
+
Digital Ref DAC TEMP
Legend
MUX I-LIMIT
ADC
TRIM/VSET High Voltage
Temp VREF
Management
Conversion
10
12. Digital
Two parts
– DSP functionality
– Control functionality
Directed tests
Verified as a platform
Emulation
– DSP function in real time
– Enables algorithm verification
– Simulation is TOO SLOW
12
